JPS60153122A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60153122A JPS60153122A JP908984A JP908984A JPS60153122A JP S60153122 A JPS60153122 A JP S60153122A JP 908984 A JP908984 A JP 908984A JP 908984 A JP908984 A JP 908984A JP S60153122 A JPS60153122 A JP S60153122A
- Authority
- JP
- Japan
- Prior art keywords
- film
- layer
- lift
- spacer
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、リフトオフ法により電極の形成がなされる半
導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which electrodes are formed by a lift-off method.
従来例の構成とその問題点
半導体装置の電極を形成する方法の１つに、リフトオフ
法がある。この方法は、電極金属膜の形成前に、電極パ
ターン形成部が開口されたホトレジスト層などのスペー
サを半導体基板上に形成したのち、電極金属層を全面に
被着し、次いで、スペーサを除去することによりこの上
に被着された電極金属層も併せて除去してスペーサの開
口内に被着された電極金属層を半導体基板上に残し、こ
れを電極あるいは電極配線層とする方法である。Conventional Structures and Problems One of the methods for forming electrodes of semiconductor devices is the lift-off method. In this method, before forming the electrode metal film, a spacer such as a photoresist layer with an electrode pattern forming part opened is formed on the semiconductor substrate, an electrode metal layer is deposited on the entire surface, and then the spacer is removed. This is a method in which the electrode metal layer deposited thereon is also removed, leaving the electrode metal layer deposited in the opening of the spacer on the semiconductor substrate and used as an electrode or an electrode wiring layer.
この方法によれば、電極金属層に対するパターンエツチ
ングが不要となり、基本的には、スペーサを形成するた
めのホトリソグラフィ精度により電極のパターン精度が
決定される。また、エツチングが困難な金塊で電極金属
層全形成しても、所望の電極パターンを容易に得ること
ができる。しかしながら、このリフトオフ法では、スペ
ーサとなと
るホトレジスト層の厚さを増す４′４像度が低下するた
め、十分な厚さのスペーサを設けることは許されない。According to this method, pattern etching for the electrode metal layer is not required, and the pattern accuracy of the electrode is basically determined by the accuracy of photolithography for forming the spacer. Further, even if the entire electrode metal layer is formed of gold ingots that are difficult to etch, a desired electrode pattern can be easily obtained. However, in this lift-off method, the 4'4 image resolution, which increases the thickness of the photoresist layer serving as the spacer, is reduced, and therefore it is not possible to provide a spacer with a sufficient thickness.
したがって、除去すべき電極金属ｊ曽と開口内の電極金
属層との間に十分な段差を付与することかできず、この
ため、不完全なリフトオフがなされるおそれがあった。Therefore, it is not possible to provide a sufficient level difference between the electrode metal layer to be removed and the electrode metal layer within the opening, which may result in incomplete lift-off.
発明の目的
本発明の目的は、従来のリフトオフ法に存在した問題点
を除き、完全なリフトオフを行なうことを可能にした半
導体装置の製造方法を提供することにある。OBJECTS OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that eliminates the problems that existed in conventional lift-off methods and makes it possible to perform complete lift-off.
発明の構成
本発明の半導体装置の製造方法は、電極形成用の開口を
もつ第１の絶縁膜で覆われた半導体基板または半導体基
板上の電極配線層の表面上に、第２の絶縁膜およびリフ
トオフ用スペーサ層を順次被着したのち、前記第１の絶
縁膜の開口の上部に位置するリフトオフ用スペーサ層部
分を少くとも除去し、次いで、リフトオフ用スペーサ層
をマスクにして前記第２の絶縁膜をエツチングしで除去
し、こののち、％極金属層の被着およびリフトオフ処理
を施す方法である。この製造方法によれば、第２の絶縁
膜によりリフトオフ用スペーサ上の電極金机層と、残存
させるべ＠電極金属層との間に十分な段差が＋ｊ与され
、確実なリフトオフが行なえる。Structure of the Invention The method for manufacturing a semiconductor device of the present invention includes forming a second insulating film and a surface of an electrode wiring layer on a semiconductor substrate or a semiconductor substrate covered with a first insulating film having an opening for forming an electrode. After sequentially depositing the lift-off spacer layers, at least a portion of the lift-off spacer layer located above the opening of the first insulating film is removed, and then, using the lift-off spacer layer as a mask, the second insulating film is deposited. This is a method in which the film is removed by etching, followed by deposition of a super metal layer and lift-off treatment. According to this manufacturing method, the second insulating film provides a sufficient step +j between the electrode metal layer on the lift-off spacer and the remaining electrode metal layer, so that reliable lift-off can be performed.
実施例の説明
以下に、第１図〜第４図を参照して本発明の半導体装置
の製造方法を説明する。DESCRIPTION OF EMBODIMENTS A method of manufacturing a semiconductor device according to the present invention will be described below with reference to FIGS. 1 to 4.
第１図は、リフトオフ用スペーサの形成までがなされた
半導体装置の断面形状を示す図であり、半導体基板１０
表面には、電極形成用の開口２が形成された二酸化シリ
コン（５ｉ０２膜）３、化学気相成長（ｃｖｎ）法で形
成した５ｉ０２膜４およびリフトオフ用スペーサとなる
ホトレジスト膜５が形成されている。なお、ホトレジス
ト膜５に形成されている開口６は、５ｉ０２膜３に形成
されている開口２の上部に位置している。次いで、ホト
レジスト膜６をマスクにして開口６の中に露出している
５ｉ０２膜４を、例えば、反応性プラズマエツチング処
理で異方性エツチングする。このエツチングにより、第
２図で示すように、垂直な断面エツチング処理ヲ泥すと
、５１０２膜４は水平方向にエツチングされ、第３図で
示すように、ホトレジストＩＩＩ ５が廂状に突出した
断面形状が得られる。FIG. 1 is a diagram showing a cross-sectional shape of a semiconductor device in which lift-off spacers have been formed.
On the surface, a silicon dioxide (5i02 film) 3 in which an opening 2 for forming an electrode is formed, a 5i02 film 4 formed by chemical vapor deposition (CVN), and a photoresist film 5 serving as a lift-off spacer are formed. . Note that the opening 6 formed in the photoresist film 5 is located above the opening 2 formed in the 5i02 film 3. Next, using the photoresist film 6 as a mask, the 5i02 film 4 exposed in the opening 6 is anisotropically etched, for example, by reactive plasma etching. As a result of this etching, as shown in FIG. 2, when the vertical cross-section etching process is removed, the 5102 film 4 is etched in the horizontal direction, and as shown in FIG. shape is obtained.
第４図は、上記の断面形状を得たのち、電極金属層、た
とえばアルミニウム層を蒸着で被着したのちの状態を示
す図であり、開口２の中に露出していた半導体基板１０
表面部分に被着するアルミニウム層７とホトレジスト膜
５の上に被着するアルミニウム層８は確実に分断されて
いる。また、両省間には十分な段差りが伺与される。こ
ののち、ホトレジスト膜５１ｆ：除去することにより、
同時にアルミニウム層８が除去され、半導体基板上には
電極となるアルミニウム層７のみが残され、電極の形成
がなされる。FIG. 4 is a diagram showing the state after obtaining the above-mentioned cross-sectional shape and depositing an electrode metal layer, for example, an aluminum layer, by vapor deposition, showing the semiconductor substrate 10 exposed in the opening 2.
The aluminum layer 7 deposited on the surface portion and the aluminum layer 8 deposited on the photoresist film 5 are reliably separated. Additionally, there is a significant gap between the two ministries. After that, by removing the photoresist film 51f,
At the same time, the aluminum layer 8 is removed, leaving only the aluminum layer 7 serving as an electrode on the semiconductor substrate, and the electrode is formed.
なお、以上の説明では、絶縁膜として５ｉＯｚ膜を例示
したが、これが窒化シリコン（ＳｉｓＮ’ａ）膜などの
他の絶縁膜でβつでもよい。また、形成する電極も、半
導体基板に直接的に接続される実施例のものに限られる
ものではなく、半導体基板の表面上に形成された電極配
線層にさらに接続される多層配線構造の上１１１１１電
極層であってもよい。In the above description, a 5iOz film was used as an example of the insulating film, but this may be another insulating film such as a silicon nitride (SisN'a) film. Furthermore, the electrodes to be formed are not limited to those of the embodiments in which the electrodes are directly connected to the semiconductor substrate; It may also be an electrode layer.
発明の効果
本発明の製造方法によれば、残存させるべき電極金属層
とリフトオフ用スペーサ」二の電極金属層との間に十分
な段差を付与することができ、両者が確実に分断される
ため、完全なリフトオフがなされる。このため、半導体
装置のリフトオフ工程における不良が排除され、その製
造歩留りを高める効果が奏される。Effects of the Invention According to the manufacturing method of the present invention, a sufficient step can be provided between the electrode metal layer to be left and the second electrode metal layer of the lift-off spacer, and the two can be reliably separated. , a complete lift-off is made. Therefore, defects in the lift-off process of the semiconductor device are eliminated, and the manufacturing yield of the semiconductor device is improved.
第１図〜第４図は、本発明の製造方法を説明するため、
製造工程に対応させて示したに″Ｔ面図である。
１・・・・・・半導体基板、２，６・・・・・・開口、
３，４・・・・・・二酸化シリコン膜、５・・・・・・
ホトレジスト膜（リフトオフ用スペーサ）、７，８・・
・・・・アルミニウム層。 ・ き
代理人の氏名 弁理士 中 尾 敏 男 ほか１名四
囮 区
−へ 曽
誠 ｆ６ 誠1 to 4 are for explaining the manufacturing method of the present invention,
It is a "T-side view shown corresponding to the manufacturing process. 1... Semiconductor substrate, 2, 6... Opening,
3, 4... Silicon dioxide film, 5...
Photoresist film (lift-off spacer), 7, 8...
...Aluminum layer.・Name of agent: Patent attorney Toshio Nakao and 1 other person
Decoy Ward-to Sosei f6 Makoto
Claims (1)
基板または半導体基板上の配線層の上面、に、第２の絶
縁膜およびリフトオフ用スペーサ層を順次被着したのち
、前記開口上に位置するリフトオフ用スペーサ層部分を
少くとも除去し、次いで、リフトオフ用スペーサ層ヲマ
スクにして前記第２の絶縁ｌＬ！２を除去し、こののち
、電極金属層の被着およびリフトオフ処理を施すことを
特徴とする半導体装置の製造方法。After sequentially depositing a second insulating film and a lift-off spacer layer on the upper surface of the semiconductor substrate or the wiring layer on the semiconductor substrate covered with the first insulating film having an opening for electrode formation, At least a portion of the lift-off spacer layer located at the lift-off spacer layer is removed, and then the lift-off spacer layer is used as a mask to form the second insulation lL! 1. A method for manufacturing a semiconductor device, which comprises removing the electrode metal layer 2, and thereafter applying an electrode metal layer and performing a lift-off process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP908984A JPS60153122A (en) | 1984-01-20 | 1984-01-20 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP908984A JPS60153122A (en) | 1984-01-20 | 1984-01-20 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60153122A true JPS60153122A (en) | 1985-08-12 |
Family
ID=11710887
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP908984A Pending JPS60153122A (en) | 1984-01-20 | 1984-01-20 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60153122A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4980973A (en) * | 1972-07-21 | 1974-08-05 | ||
| JPS526467A (en) * | 1975-07-07 | 1977-01-18 | Toshiba Corp | Manufacturing method of semi-conductors |
-
1984
- 1984-01-20 JP JP908984A patent/JPS60153122A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4980973A (en) * | 1972-07-21 | 1974-08-05 | ||
| JPS526467A (en) * | 1975-07-07 | 1977-01-18 | Toshiba Corp | Manufacturing method of semi-conductors |
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