JPH06204164A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH06204164A
JPH06204164A JP148793A JP148793A JPH06204164A JP H06204164 A JPH06204164 A JP H06204164A JP 148793 A JP148793 A JP 148793A JP 148793 A JP148793 A JP 148793A JP H06204164 A JPH06204164 A JP H06204164A
Authority
JP
Japan
Prior art keywords
photoresist
film
interlayer insulating
electrode
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP148793A
Other languages
Japanese (ja)
Inventor
Toshiharu Kumazawa
俊春 熊沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Yamagata Ltd
Original Assignee
NEC Yamagata Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Yamagata Ltd filed Critical NEC Yamagata Ltd
Priority to JP148793A priority Critical patent/JPH06204164A/en
Publication of JPH06204164A publication Critical patent/JPH06204164A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve step coverage of a second layer electrode in the electrode two-layered structure of a transistor. CONSTITUTION:Photoresist 4 is turned into a smooth form by baking, and subsequently turned into a form wherein the taper angle is gentle by anisotropically etching an interlayer insulating film 2. The step coverage of film thickness of a second layer electrode 3 is improved by 50%. Wire disconnection failure due to that the film is thinned down can be prevented.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置の製造方法
に関し、特にトランジスタの電極2層構造の改善された
スルーホール部の構造を有する半導体装置の製造方法に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having an improved through hole portion structure of a transistor electrode two-layer structure.

【0002】[0002]

【従来の技術】従来の電極2層構造を有する半導体装置
の電極2層構造部の断面図を図4に、その工程断面図を
図3に示す。
2. Description of the Related Art A sectional view of an electrode two-layer structure portion of a semiconductor device having a conventional electrode two-layer structure is shown in FIG. 4 and a process sectional view thereof is shown in FIG.

【0003】図4は第1層電極1の上に、層間絶縁膜2
を介して、第2層電極3が形成されている。次に図3に
よりその製造方法を説明する。まず図3(a)に示すよ
うに、第1層電極1の上に、被エッチング被膜である層
間絶縁膜2を膜厚約1.8±0.3μm形成し、その上
にエッチングマスクとなる。フォトレジスト膜4を膜厚
約2.0μm形成する。次に、図3(b)に示すよう
に、公知のフォトリソグラフィ技術により、フォトレジ
スト膜4を開口する。
FIG. 4 shows an interlayer insulating film 2 on the first layer electrode 1.
The second layer electrode 3 is formed via the. Next, the manufacturing method will be described with reference to FIG. First, as shown in FIG. 3A, an interlayer insulating film 2 which is a film to be etched is formed on the first layer electrode 1 to a film thickness of about 1.8 ± 0.3 μm, and an etching mask is formed thereon. . The photoresist film 4 is formed to a film thickness of about 2.0 μm. Next, as shown in FIG. 3B, the photoresist film 4 is opened by a known photolithography technique.

【0004】次いで図3(c)に示すように、層間絶縁
膜2とフォトレジスト4の密着性を良くするためベーク
(温度135℃、時間50分)を行なう。次に、図3
(d)に示すように、フォトレジスト膜4をマスクにし
てドライエッチで等方性エッチングを施こす。
Next, as shown in FIG. 3C, baking (temperature 135 ° C., time 50 minutes) is performed to improve the adhesion between the interlayer insulating film 2 and the photoresist 4. Next, FIG.
As shown in (d), isotropic etching is performed by dry etching using the photoresist film 4 as a mask.

【0005】次に図3(e)に示すように、フォトレジ
スト膜4の除去を行ない、第2層電極3を公知の技術で
約2.0μm蒸着形成すると電極2層構造が図3(f)
に示す構造として得られる。
Next, as shown in FIG. 3 (e), the photoresist film 4 is removed, and the second layer electrode 3 is formed by vapor deposition to a thickness of about 2.0 μm by a known technique. )
It is obtained as a structure shown in.

【0006】[0006]

【発明が解決しようとする課題】上述した従来の半導体
装置の製造方法は、層間絶縁膜2の形状がスルーホール
部端で鋭くエッチカットされるため、第2層電極3の電
極膜のステップカバレッジが悪化し、膜厚が薄くなるこ
とによる断線不良という問題点があった。
In the conventional method for manufacturing a semiconductor device described above, since the shape of the interlayer insulating film 2 is sharply cut at the end of the through hole portion, the step coverage of the electrode film of the second layer electrode 3 is covered. However, there was a problem of disconnection failure due to deterioration of the film thickness and thin film thickness.

【0007】本発明の目的は断線不良を起こすことのな
い電極2層構造を有する半導体装置の製造方法を提供す
ることにある。
An object of the present invention is to provide a method of manufacturing a semiconductor device having a two-layer structure of electrodes which does not cause disconnection failure.

【0008】[0008]

【課題を解決するための手段】本発明の半導体装置の製
造方法は、下層第1電極上に形成された層間絶縁膜上の
開口されたフォトレジスト膜のベーク温度を高くするこ
とにより、フォトレジストの開口部端の形状をなめらか
にし、さらに開口端のなめらかにされたフォトレジスト
膜をマスクとして層間絶縁膜を異方性エッチングするこ
とにより、スルーホール部のテーパ角をなめらかに形成
し、上層第2電極を形成することにより構成される。
According to the method of manufacturing a semiconductor device of the present invention, the photoresist temperature is increased by increasing the baking temperature of the opened photoresist film on the interlayer insulating film formed on the lower first electrode. By smoothing the shape of the opening end of the mask, and by anisotropically etching the interlayer insulating film using the photoresist film having the smoothed opening end as a mask, the taper angle of the through hole is formed smoothly, and the upper layer first layer is formed. It is configured by forming two electrodes.

【0009】[0009]

【実施例】次に、本発明について図面を参照して説明す
る。図1は本発明の一実施例のトランジスタの電極2層
構造のスルーホール部製造工程断面図であり、図2は本
発明の一実施例により製造された半導体装置の電極2層
構造部の断面図である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of a through-hole manufacturing process of a two-layer electrode structure of a transistor according to an embodiment of the present invention, and FIG. 2 is a cross-section of the two-layer electrode structure of a semiconductor device manufactured according to an embodiment of the present invention. It is a figure.

【0010】図1(a)に示すように、第1層電極1の
上に、被エッチング被膜である層間絶縁膜2を膜厚約
1.8μm±0.3μm形成し、その上にエッチングマ
スクとなるフォトレジスト膜4を膜厚約2.0μm形成
する。次いで図1(b)に示すように、公知のフォトリ
ソグラフィ技術により、フォトレジスト膜4を開口す
る。次いで図1(c)に示すように、ベークを温度16
0℃、時間50分で行ないフォトレジスト膜4をなめら
かな形状にする。
As shown in FIG. 1A, an interlayer insulating film 2 which is a film to be etched is formed on the first layer electrode 1 to have a film thickness of about 1.8 μm ± 0.3 μm, and an etching mask is formed thereon. A photoresist film 4 having a thickness of about 2.0 μm is formed. Next, as shown in FIG. 1B, the photoresist film 4 is opened by a known photolithography technique. Then, as shown in FIG. 1C, baking is performed at a temperature of 16
The photoresist film 4 is formed into a smooth shape at 0 ° C. for 50 minutes.

【0011】次に、図1(d)に示すように、なめらか
な形状にしたフォトレジスト膜4をマスクにしてRIE
で、層間絶縁膜2を垂直な方向に異方性エッチングする
ことによりエッチングの形状は、なめらかな形状にした
フォトレジスト膜4とほぼ同形になる。その結果形成さ
れた、層間絶縁膜2は図示のように、テーパ角がなめら
かになる。
Next, as shown in FIG. 1D, RIE is performed using the photoresist film 4 having a smooth shape as a mask.
Then, by anisotropically etching the interlayer insulating film 2 in the vertical direction, the etching shape becomes almost the same as that of the smoothed photoresist film 4. The interlayer insulating film 2 formed as a result has a smooth taper angle as illustrated.

【0012】次に、図1(e)に示すように、フォトレ
ジスト膜4を除去した後、図1(f)に示すように、第
2層電極3を公知の技術で約2.0μm蒸着して形成す
る。
Next, as shown in FIG. 1 (e), after removing the photoresist film 4, a second layer electrode 3 is vapor-deposited by a known technique to a thickness of about 2.0 μm as shown in FIG. 1 (f). To form.

【0013】以上の工程によれば、層間絶縁膜2の形状
のテーパ角がなめらかになっているため、図3(f)に
示すように第2層電極3の膜厚が薄くなったり、あるい
は断線したりして蒸着形成されることがなく、ステップ
カバレッジが向上し、膜厚が薄くなることによる断線不
良となることがない。
According to the above steps, since the taper angle of the shape of the interlayer insulating film 2 is smooth, the film thickness of the second layer electrode 3 becomes thin as shown in FIG. There is no disconnection or vapor deposition formation, step coverage is improved, and there is no disconnection failure due to a thin film thickness.

【0014】次に従来方法及び本発明の実施例により形
成された電極窓に対するステップカバレッジの結果を表
1に示した。
Table 1 shows the results of step coverage for the electrode windows formed by the conventional method and the embodiment of the present invention.

【0015】[0015]

【表1】 [Table 1]

【0016】表1の結果から、層間絶縁膜厚が規格内に
変動してもステップカバレッジは従来例に比べ約50%
向上することが実験データから得られている。
From the results of Table 1, the step coverage is about 50% compared with the conventional example even if the interlayer insulating film thickness fluctuates within the standard.
Improvements have been obtained from experimental data.

【0017】[0017]

【発明の効果】以上説明したように本発明は、トランジ
スタの電極2層構造において、ベークでフォトレジスト
をなめらかな形状にして層間絶縁膜を異方性エッチング
し、テーパ角をなめらかに形成することにより第2層電
極の膜厚のステップカバレッジを約50%向上し、膜厚
が薄くなることによる断線不良を防ぐことができる。
As described above, according to the present invention, in the two-layer structure of the electrode of the transistor, the photoresist is made into a smooth shape by baking, and the interlayer insulating film is anisotropically etched to form a smooth taper angle. Thereby, the step coverage of the film thickness of the second layer electrode can be improved by about 50%, and the disconnection defect due to the thin film thickness can be prevented.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を説明するために工程順に示
したトランジスタの電極2層構造部の断面図である。
FIG. 1 is a cross-sectional view of an electrode two-layer structure portion of a transistor, which is shown in order of steps for explaining an embodiment of the present invention.

【図2】本発明の一実施例により形成されたトランジス
タの電極2層構造の断面図である。
FIG. 2 is a cross-sectional view of a two-layer structure of electrodes of a transistor formed according to an embodiment of the present invention.

【図3】従来の半導体装置の製造方法の一例を説明する
ために工程順に示したトランジスタの電極2層構造部の
断面図である。
FIG. 3 is a cross-sectional view of the electrode two-layer structure portion of the transistor shown in the order of steps for explaining an example of the conventional method for manufacturing a semiconductor device.

【図4】従来例により形成されたトランジスタの電極2
層構造部の断面図である。
FIG. 4 is an electrode 2 of a transistor formed by a conventional example.
It is sectional drawing of a layer structure part.

【符号の説明】[Explanation of symbols]

1 第1層電極 2 層間絶縁膜 3 第2層電極 4 フォトレジスト膜 1 First Layer Electrode 2 Interlayer Insulation Film 3 Second Layer Electrode 4 Photoresist Film

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 第1層電極を形成する工程と、前記第1
層電極上に層間絶縁膜を形成する工程と、前記層間絶縁
膜上にフォトレジスト膜を形成し、該フォトレジスト膜
に開口を形成する工程と、開口の形成されたフォトレジ
スト膜を高い温度でベークし、フォトレジストの開口部
端の形状をなめらかにする工程と、前記フォトレジスト
をマスクにしてRIEで層間絶縁膜を垂直方向に異方性
エッチングし層間絶縁膜にフォトレジストと同形状のテ
ーパー角がなめらかなスルーホールを形成する工程と、
フォトレジストを除去した後第2層電極を形成する工程
とを有することを特徴とする半導体装置の製造方法。
1. A step of forming a first layer electrode and the first step
A step of forming an interlayer insulating film on the layer electrode, a step of forming a photoresist film on the interlayer insulating film and forming an opening in the photoresist film, and a step of forming the opening-formed photoresist film at a high temperature. Baking and smoothing the shape of the opening end of the photoresist; and anisotropic etching of the interlayer insulating film in the vertical direction by RIE using the photoresist as a mask to taper the interlayer insulating film to the same shape as the photoresist. A step of forming a through hole with smooth corners,
A step of forming a second layer electrode after removing the photoresist, a method of manufacturing a semiconductor device.
JP148793A 1993-01-08 1993-01-08 Manufacture of semiconductor device Pending JPH06204164A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP148793A JPH06204164A (en) 1993-01-08 1993-01-08 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP148793A JPH06204164A (en) 1993-01-08 1993-01-08 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH06204164A true JPH06204164A (en) 1994-07-22

Family

ID=11502802

Family Applications (1)

Application Number Title Priority Date Filing Date
JP148793A Pending JPH06204164A (en) 1993-01-08 1993-01-08 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH06204164A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108383077A (en) * 2018-02-05 2018-08-10 上海华虹宏力半导体制造有限公司 Ramped shaped amorphous silicon membrane film build method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108383077A (en) * 2018-02-05 2018-08-10 上海华虹宏力半导体制造有限公司 Ramped shaped amorphous silicon membrane film build method

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