JPS60149164A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain the SCR device of high sensitivity by a method wherein a layer of the same conductivity type separated from the gate connection layer of an SCR of short-circuit emitter structure is provided with an MOS gate signal supply part in the neighborhood of the gate connection layer of an MOS structural photo transistor. CONSTITUTION:PB layers 41-44 are formed in an SCR NB layer 3, and a P- layer 11 is formed between the layers 41 and 43. NE layers 51 and 52 and a short-circuit emitter cathode 13 are formed in the layer 41. The photo transistor 19 of MOS structure 18 having an electrode 17 on NE layers 14 and 15 and an insulation film 16 is formed in the layer 42. Then, the layers 15 and 42 are short-circuited with an electrode 20 and connected as required, and the MOS gate signal supply part 21 is made of the layers 11, 41, and 43. When the terminal voltage VAK is less than a constant value VL determined by the interval l of the layer 11, on application of photo trigger signals to the device 19, a gate current flows through the layer 41 and the SCR ignites. When the VAK becomes more than the threshold value VT of the device 19, the layer 14 is short-circuited with the layer 42 via a layer 15 and electrode 20, and then does not ignite because of an supply of current to the layer 41. With this construction, in spite of a large current and a high withstand voltage, the SCR of small size and high sensitivity can be obtained with good yield.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a composite semiconductor device in which, for example, a Zyristor and a control element of the Zyristor are formed on the same semiconductor substrate in a nonlithic manner. In particular, a high-power, high-sensitivity semiconductor device that is small and highly sensitive despite its large current and high surface pressure, and can be manufactured with high yield using conventional manufacturing technology. There are many people involved in this.

``Technical weight of the invention'' Recently, a power semiconductor device has been developed in which a MO8 structure is provided between the gate and cathode of a Zyristor, and the trigger function is controlled by short-circuiting the gate and cathode using this MaSIM structure. Proposed.

FIG. 1 shows an example of a power semiconductor device using such a trigger control method (see Japanese Patent Application Laid-Open No. 105572/1983). In the figure, 1 is a semiconductor substrate, 2 is the substrate 1
a P-type anode region formed on one main surface of the substrate 1; 3 an N-type base region forming the other main surface of the substrate 1;
5 is a P-type base region which is a gate connection region, and 5 is an N-type cathode region formed in the P-type base region 4.

An annular N-type region 6 is formed around the N-type cathode region 5 with the P-type base region 4 in between.
An insulating film 7, an electrode 8, etc. are provided on the surface of the P-type base region 4 between both regions 5°6 so as to straddle the mold region 6. A MO3 structure 9 is formed between each electrode 8 and a P-type region 10 at a position away from the P-type base region 4 in order to supply a bias to the MO8 structure 9. The P-type region 10 and the electrode 8 of the MO3 structure 9 are electrically connected via a conductor.

The above-mentioned well-known semiconductor device was developed as an SSR element having a zero-crossing function, and is
8 structure 9 allows the trigger function to be suppressed. That is, in the above structure, when the anode-cathode voltage VAK exceeds the voltage VAKc determined by the position of the P-type region 10, the N-type Since the cathode region 5 and the N-type region 6 are electrically connected through the channel, the cathode region 5 and the N-type base region 4 are ultimately short-circuited, and as a result, the anode-cathode voltage is higher than the above-mentioned Vxc. In this case, 1 to 1 function is suppressed.

[Problems with Background Art] The above-mentioned known semiconductor devices were developed as highly sensitive elements having a zero-crossing function, and are not suitable as high-voltage, large-current switching elements.

In general, when designing a power semiconductor device U, -C takes into account various points such as increasing the current and withstand voltage of the device, as well as increasing the sensitivity of the switching function, ease of manufacturing, and maintaining manufacturing yield above a certain level. The first thing you have to do is
When attempting to increase the current and withstand voltage of a semiconductor device as shown in the figure, the following problems arise.

■ In order to increase the current of the device, the device area must be increased, but in the device structure shown in Figure 1, the can and gate are shunted by the MOS 4M structure, so it is difficult to make the device large. In order to avoid current concentration, M
O8M? #Zuko's channel ``[] will also become noticeably larger.

However, since there is a limit to the size of the pellet 1, a more precise inlay forming technique than before is required to enlarge the MOS channel 11 within the limited size of the vane 1. For this reason, when a semiconductor device having a structure as shown in FIG. 1 is made to carry a large current, there is a possibility that the manufacturing yield will be significantly lowered. In addition, increasing the element area also increases the junction capacitance.
dv/dtT#! There were problems such as a decrease in Ji.

■Generally, it is desirable that a semiconductor device for use in microscopy be configured so that it can be triggered by light, but if the semiconductor device shown in Figure 1 is made into a high-power semiconductor device by increasing the withstand voltage and current, the following will occur. For this reason, the sensitivity to light 1 to 1 is lowered, making it unsuitable for use as a semiconductor device for power incoming horns. To increase the withstand voltage of the area
However, as the diffusion depth of each diffusion region increases, the effective photocurrent generated when light is irradiated decreases, so the sensitivity to optical triggers decreases to <<. Become. (As mentioned in ■, if the semiconductor device shown in Figure 1 is made to have a large current, a large gate current will be required. However, if the voltage is increased, the effective photocurrent when performing optical 1-regulation will decrease.) Therefore, in order to compensate for such a decrease in sensitivity, a light source with a higher output than the conventional light source used for the optical trigger than the U8 LE [) is required. However, the place of 3T2 Ir,
The current output level of LED is the best, and
Other light sources with higher output power are unsuitable for SSR due to their power consumption and size, and therefore it is impossible to compensate for the decrease in taste sensation.

[Object of the Invention] The object of the present invention is to solve the above-mentioned problems and to provide a thyristor for high power use having a MO8 structure as shown in FIG. semiconductor′
In particular, it is an object of the present invention to provide a high-sensitivity, high-power semiconductor device that can be manufactured using conventional manufacturing techniques without reducing yield.

[Summary of the Invention] A semiconductor device of the present invention shown in a preferred embodiment of the present invention includes a phototransistor formed in a region of the same conductivity type at a position away from a gate connection region of the thyristor, an MO8 structure formed within the transistor;
and a MOS gate signal supply section formed near the gate connection region, and each of these sections is monolithically formed on the same semiconductor substrate, and the cathode of the thyristor has a short emitter structure. shall be.

In such a semiconductor device manufactured by WJ (13), Part 1
Because Noirisk's gate circuit is equipped with photo 1~transistors, it can be triggered by a relatively low-output light source, and even with a high-voltage element with a large diffusion depth, the output is relatively low. Can be light triggered by a light source. Moreover, the MO that controls the zero cross function
Since the 'S structure is installed in the il-1 transistor, the same high sensitivity as the conventional device shown in FIG. 1 can be imparted to the il-1 transistor.

In addition, in the semiconductor device of the present invention, a transistor is provided in the gate circuit of the Noiristor (1) and a transistor is provided in the gate circuit () and the signal is amplified. can.

[Embodiment of the Invention An embodiment of the invention is not shown in FIG. In this embodiment, the semiconductor device of the present invention is configured as a composite thyristor of the play type.

In FIG. 2, 2 is a P-type anode region that constitutes the main surface on the anode side of the semiconductor substrate 1 and is also exposed on the main surface on the cathode side, and 3 is a P-type anode region that is exposed on the main surface on the cathode side of the semiconductor substrate 1. This is an N-type base region. Within the N-type base region 3 are P-type head regions 41 to 4 exposed on the main surface on the cathode side.
4 and 11 are formed, except for one P-type head region 11, the others are P-type base regions of the thyristor.

One of the P-type base regions 41 is provided with two N-type regions 51+52 exposed on the main surface on the cathode side, and both N-type regions 5.1.52 and P-type base region 41 are in contact with each other. A cathode electrode 12 is provided on the main surface on the cathode side, and a thyristor cathode portion 13 is formed there. As seen in the figure, this thyristor cathode section 13 has an emitter structure to show 1, and has a structure suitable for increasing the dv/dt withstand capability.

Two N-type regions 14 and 15 are provided in another P-type base region 42 located away from the P-type base region 41 constituting the thyristor cathode portion 13, and both N-type regions 14 and An insulating layer 1G is formed in contact with the P-type base region 42 between the two ends of the insulating layer 15, and a conductor electrode 17 is provided on the insulating layer 16. N-type regions 14 and 1
] The type base region 42 and the N type base region 3 are
On the other hand, the N-type regions 14 and 15 and the P-type base region 42 and the insulating layer 16 therebetween form a transistor 19.
A MOS structure 18 is formed by the conductor electrode 17 and the conductor electrode 17 . The N-type region 14 forming the transistors 19 is connected to the " ]-type base region 41 (
or -C is electrically connected to the connection area). On the other hand, the other N type region 15 is connected to the UP type base region 42 (i.e.,
)A1 to the base of the transistor).

An additional P-type head region 11 for supplying a zero-crossing control signal to the groove 1- of the MO8 structure 18 is located between the P-type base region 41°43.44 of the thyristor cathode portion 13 and the other P-type base region 43. It is formed at an intermediate position, and the P-type region 11 constitutes a MOS game signal supply section 21 .

In the semiconductor device of the present invention having the above-described structure, when a voltage is applied between the 7 node A and the cathode and the voltage is increased, the depletion layer generated around the P-type base region 41 mainly forms in the N-type base region. 3, but the voltage spreads toward the anode side at a certain value VL (this is the P wall region 11 and P
When the outer line of the depletion layer reaches a value predetermined by the distance 1 from the type base regions 41 and 43, the outer line of the depletion layer becomes the P wall region 1.
1 and the voltage rises above V1, the P wall region 11 becomes surrounded by a depletion layer and the potential of the P wall region 11 is maintained at a constant value.

Note that when the applied voltage V'A is smaller than V,
The potential of the P wall region 11 is the same as the anode potential, and the P wall region 11 has the same potential as the anode potential.
M OS electrically connected to wall area 11 @Zobu 1
The potential of No. 8 is also the same potential as the anode potential.

When the potential of the P wall region 11 is below a certain value (that is, when the applied voltage VAx is below Vt), when a phototrigger signal is input to the phototransistor, a photocurrent is generated in the phototransistor, and this is amplified. from the emitter (N-type region 14) to the silice cathode section 13 via a conductor connection.
The P-shaped beam flows into the forked area 41, and as a result, the silisk is ignited.

However, when the applied voltage V AK h' The N-type region 14 (i.e., the emitter), which is electrically coupled to the N-type region 15 and thus joined to the []-type base region 41 via a conductive connection, is connected to the N-channel and the other N-type region 14 (i.e., the emitter). Phototransistor 1 via mold region 15 and shorting electrode 20
It is short-circuited to two base regions (ie, type 1 base region 42).

Therefore, in this state (Rinawara, the applied voltage VAK
is MO8l! (a state in which the threshold voltage VT of the manufactured product 18 is exceeded) Even if an optical trigger signal is input to the phototransistor 19, the current is not supplied from the phototransistor 19 to the P-type base region 41 of the thyristor. 1 Nyrister will not be fired because it will run out.

Therefore, the phototransistor 19 can supply current to the thyristor 1 at the anode-cathode voltage V AK
is below V1.

Incidentally, in this example, in order to make V□ 5 to 6 V, the surface concentration of the single type base region 41.43 is set to 1x 10".
/cm3. Interfacial charge density IX 10”/cm
2. Also, the oxidation IIAj of the MO8 structure; p is 1500λ
As a matter of fact, the dielectric breakdown voltage of this oxide film is 120
~130V. Therefore, the value of the interval l that causes bunch-through at around 120 cm is such that the concentration of the N-type base region 3 is 1. x 10" 7cm3. If the diffusion depth of the P-type region is increased to 40μIll, the depletion layer will expand by about 30μm1, so one line of 30μm or less is taken.

"Effects of the Invention" The features and advantages of the semiconductor device of the present invention are as follows.

(a > j on the conventional device side in Figure 1: In the configuration in which the MO3 structure is formed between the goo 1 and the cathode of the sea urchin, when the size of the beret 1 is increased to increase the current, the M The channel width of the OS structure also has to be significantly increased, but increasing the channel width of the MO3 structure requires high-precision manufacturing technology in the element manufacturing process, which reduces yield. There was a risk of a significant decline.

In the semiconductor device of the present invention, the thyristor transistors are provided in the thyristor P-type base region located away from the thyristor cathode portion, and the MOS M4 structure is formed in the phototransistor. Channel I of the MO8 structure even if the current capacity is increased
11. Therefore, even when manufacturing an element with a large current capacity, a special high-precision manufacturing technique 4i1. Since J is not required, there is no risk of yield reduction.

b) In the semiconductor device of the present invention, a phototransistor is provided in the P-type base region of the 4-no-iristor, and the gate signal of the thyristor is supplied from the phototransistor. Even the signal is amplified and the thyristor can be reliably triggered. Therefore, it is possible to realize a semiconductor device with a deep diffusion region (that is, a high breakdown voltage) using an optical trigger method, and it is also possible to realize a semiconductor device with a deep diffusion region (that is, a high breakdown voltage) using a light trigger method. 1- A high breakdown voltage semiconductor device that can be triggered can be realized.

(C) The surface capacity of the phototransistor can be set independently of the current capacity of the thyristor, and since the MOS structure is made of the phototransistor, even if the current capacity of the thyristor is very large. The element area can be small, and therefore a semiconductor device can be provided that is small compared to its current capacity.

(d.) Since the phototransistor is formed within the P-type base region of the υ iristor, the phototransistor is shielded from the high electric field of the thyristor, and therefore the phototransistor can be formed with high sensitivity.

Therefore, a highly sensitive semiconductor device can be obtained.

(e) Since the square emitter structure is adopted for the quad portion of the thyristor, the origin arc of the thyristor itself due to external noise etc. is prevented, and high dV/dt resistance is guaranteed.

(f) By setting the threshold voltage VT in the MOS structure to 5 V or less, electromagnetic interference caused by ignition can be almost completely prevented.

As described above, according to the present invention, the problems inherent in conventional devices are solved, and the input current, high withstand voltage, and high II! A semiconductor device with high efficiency and high yield is provided.

In the above embodiments, only the case where the present invention is applied to a reverse blocking three-terminal one-noir resistor has been described, but it is clear that the present invention can be applied to other types of control elements.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a conventional semiconductor device, and FIG. 2 is a sectional view of a semiconductor device according to an embodiment of the present invention. 1... Semiconductor substrate, 2... Anode region, 3.
...N-type base region, 4...P-type base region, 5
...Cathode region, 6...N-type region, ``7-insulating film, 8...electrode, 9...MOS JM construction,
10... P type region, 11... P type region, 12...
- Cathode region, 13... thyristor cathode section,
14... N-type region, 16... Insulating layer, 17...
Gate electrode, 18...MOS structure section, 19...7
711-1-ransistor, 20... short circuit electrode, 2
1...MOS gate signal supply section, 41-44...P
mold base region, 51, 52... cathode region;

Claims (1)

[Claims] a semiconductor substrate of a first conductivity type having first and second main surfaces parallel to each other; a first area;
a second region of the first conductivity type formed in the second region and exposed on the first main surface; a first electrode formed on the surface of the second region; a third region of a second conductivity type formed at a predetermined distance or apart from the first region and exposed on the first main surface; A fourth region of the second conductivity type formed at a distant position and exposed on the second main surface, and a fourth region of the second conductivity type formed at a distance from each other within the fourth region. fifth and sixth regions of the first conductivity type exposed on the surface; an insulating layer formed across the fifth and sixth regions and disposed on the fourth region; a second electrode formed on the insulating layer; a second region of the second conductivity type formed on the first or second main surface of the substrate; and a second region of the second conductivity type formed on the surface of the second region. It has three electrodes, and the third region and the fifth region are electrically connected, and the third region and the second electrode are electrically connected. A semiconductor device characterized by: