JPS60148252A - 並列メモリスイツチ方式 - Google Patents

並列メモリスイツチ方式

Info

Publication number
JPS60148252A
JPS60148252A JP395984A JP395984A JPS60148252A JP S60148252 A JPS60148252 A JP S60148252A JP 395984 A JP395984 A JP 395984A JP 395984 A JP395984 A JP 395984A JP S60148252 A JPS60148252 A JP S60148252A
Authority
JP
Japan
Prior art keywords
data
memory
buffer memory
buffer
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP395984A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0315865B2 (cg-RX-API-DMAC7.html
Inventor
Kenji Miyayasu
憲治 宮保
Yasuharu Kosuge
小菅　康晴
Hiroshi Ishikawa
宏 石川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP395984A priority Critical patent/JPS60148252A/ja
Publication of JPS60148252A publication Critical patent/JPS60148252A/ja
Publication of JPH0315865B2 publication Critical patent/JPH0315865B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
JP395984A 1984-01-12 1984-01-12 並列メモリスイツチ方式 Granted JPS60148252A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP395984A JPS60148252A (ja) 1984-01-12 1984-01-12 並列メモリスイツチ方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP395984A JPS60148252A (ja) 1984-01-12 1984-01-12 並列メモリスイツチ方式

Publications (2)

Publication Number Publication Date
JPS60148252A true JPS60148252A (ja) 1985-08-05
JPH0315865B2 JPH0315865B2 (cg-RX-API-DMAC7.html) 1991-03-04

Family

ID=11571633

Family Applications (1)

Application Number Title Priority Date Filing Date
JP395984A Granted JPS60148252A (ja) 1984-01-12 1984-01-12 並列メモリスイツチ方式

Country Status (1)

Country Link
JP (1) JPS60148252A (cg-RX-API-DMAC7.html)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6447152A (en) * 1987-08-18 1989-02-21 Nec Corp Digital cross connect network
JPS6482838A (en) * 1987-09-25 1989-03-28 Matsushita Electric Industrial Co Ltd Digital exchange
JPH07321841A (ja) * 1991-11-27 1995-12-08 Internatl Business Mach Corp <Ibm> 並列ネットワークを介してデータを送受信するための変換アダプタ装置及びコンピュータ・システム

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6447152A (en) * 1987-08-18 1989-02-21 Nec Corp Digital cross connect network
JPS6482838A (en) * 1987-09-25 1989-03-28 Matsushita Electric Industrial Co Ltd Digital exchange
JPH07321841A (ja) * 1991-11-27 1995-12-08 Internatl Business Mach Corp <Ibm> 並列ネットワークを介してデータを送受信するための変換アダプタ装置及びコンピュータ・システム

Also Published As

Publication number Publication date
JPH0315865B2 (cg-RX-API-DMAC7.html) 1991-03-04

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term