JPS60142545A - 多層複合構造体 - Google Patents

多層複合構造体

Info

Publication number
JPS60142545A
JPS60142545A JP59242568A JP24256884A JPS60142545A JP S60142545 A JPS60142545 A JP S60142545A JP 59242568 A JP59242568 A JP 59242568A JP 24256884 A JP24256884 A JP 24256884A JP S60142545 A JPS60142545 A JP S60142545A
Authority
JP
Japan
Prior art keywords
layer
metal
deposited
layers
rie
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59242568A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0224019B2 (index.php
Inventor
ハーバンス・シン・サチデヴ
クリシユナン・サチデヴ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS60142545A publication Critical patent/JPS60142545A/ja
Publication of JPH0224019B2 publication Critical patent/JPH0224019B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H10P14/662—
    • H10P14/6336—
    • H10P14/683—
    • H10P14/6922—
    • H10W20/058—
    • H10W20/4473—
    • H10W70/69—

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
JP59242568A 1983-12-27 1984-11-19 多層複合構造体 Granted JPS60142545A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US56556283A 1983-12-27 1983-12-27
US565562 1983-12-27

Publications (2)

Publication Number Publication Date
JPS60142545A true JPS60142545A (ja) 1985-07-27
JPH0224019B2 JPH0224019B2 (index.php) 1990-05-28

Family

ID=24259173

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59242568A Granted JPS60142545A (ja) 1983-12-27 1984-11-19 多層複合構造体

Country Status (3)

Country Link
EP (1) EP0150403B1 (index.php)
JP (1) JPS60142545A (index.php)
DE (1) DE3473198D1 (index.php)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6009308A (en) * 1996-06-21 1999-12-28 Nec Corporation Selective calling receiver that transmits a message and that can identify the sender of this message
US7947375B2 (en) 2001-05-11 2011-05-24 Panasonic Corporation Interlayer dielectric film
JP2011527832A (ja) * 2008-07-11 2011-11-04 サンディスク スリーディー，エルエルシー 不揮発性メモリデバイスを製作する方法

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4519872A (en) * 1984-06-11 1985-05-28 International Business Machines Corporation Use of depolymerizable polymers in the fabrication of lift-off structure for multilevel metal processes
US4764644A (en) * 1985-09-30 1988-08-16 Microelectronics Center Of North Carolina Microelectronics apparatus
US4667404A (en) * 1985-09-30 1987-05-26 Microelectronics Center Of North Carolina Method of interconnecting wiring planes
DE3604917A1 (de) * 1986-02-17 1987-08-27 Messerschmitt Boelkow Blohm Verfahren zur herstellung eines integrierten verbandes in reihe geschalteter duennschicht-solarzellen
US5141817A (en) * 1989-06-13 1992-08-25 International Business Machines Corporation Dielectric structures having embedded gap filling RIE etch stop polymeric materials of high thermal stability
EP0507881A1 (en) * 1990-01-04 1992-10-14 International Business Machines Corporation Semiconductor interconnect structure utilizing a polyimide insulator
US5300813A (en) * 1992-02-26 1994-04-05 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
US5550405A (en) * 1994-12-21 1996-08-27 Advanced Micro Devices, Incorporated Processing techniques for achieving production-worthy, low dielectric, low interconnect resistance and high performance ICS

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5745952A (en) * 1980-08-18 1982-03-16 Ibm Method of producing integrated circuit
JPS57211239A (en) * 1981-06-22 1982-12-25 Nippon Telegr & Teleph Corp <Ntt> Formation of insulating film

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4001870A (en) * 1972-08-18 1977-01-04 Hitachi, Ltd. Isolating protective film for semiconductor devices and method for making the same
US3985597A (en) * 1975-05-01 1976-10-12 International Business Machines Corporation Process for forming passivated metal interconnection system with a planar surface

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5745952A (en) * 1980-08-18 1982-03-16 Ibm Method of producing integrated circuit
JPS57211239A (en) * 1981-06-22 1982-12-25 Nippon Telegr & Teleph Corp <Ntt> Formation of insulating film

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6009308A (en) * 1996-06-21 1999-12-28 Nec Corporation Selective calling receiver that transmits a message and that can identify the sender of this message
US7947375B2 (en) 2001-05-11 2011-05-24 Panasonic Corporation Interlayer dielectric film
JP2011527832A (ja) * 2008-07-11 2011-11-04 サンディスク スリーディー，エルエルシー 不揮発性メモリデバイスを製作する方法

Also Published As

Publication number Publication date
JPH0224019B2 (index.php) 1990-05-28
DE3473198D1 (en) 1988-09-08
EP0150403B1 (en) 1988-08-03
EP0150403A1 (en) 1985-08-07

Similar Documents

Publication Publication Date Title
JP3418458B2 (ja) 半導体装置の製造方法
EP0046525B1 (en) Planar multi-level metal-insulator structure comprising a substrate, a conductive interconnection pattern and a superposed conductive structure and a method to form such a structure
JP3189781B2 (ja) 半導体装置の製造方法
US4692205A (en) Silicon-containing polyimides as oxygen etch stop and dual dielectric coatings
US3985597A (en) Process for forming passivated metal interconnection system with a planar surface
JPS613411A (ja) リフトオフ処理方法
US4447824A (en) Planar multi-level metal process with built-in etch stop
JP2003504693A (ja) フォーミングガスプラズマを用いたフォトレジスト除去プロセス
US4451971A (en) Lift-off wafer processing
US5407529A (en) Method for manufacturing semiconductor device
US7022582B2 (en) Microelectronic process and structure
JPH02151030A (ja) パターン形成方法
US6333258B1 (en) Method of manufacturing a semiconductor device
JPS60142545A (ja) 多層複合構造体
JPH0221640A (ja) 半導体装置
JP2849286B2 (ja) 半導体装置の製造方法
JPH0653134A (ja) 半導体装置の製造方法
JPH0677208A (ja) 半導体装置の製造方法
US20050158666A1 (en) Lateral etch inhibited multiple etch method for etching material etchable with oxygen containing plasma
KR0168461B1 (ko) 반도체장치의 제조방법
EP0204631A2 (en) Semiconductor structures having polysiloxane leveling film
JPH11168141A (ja) 半導体装置及びその製造方法
JPH09213796A (ja) 半導体装置及びその製造方法
JP2000349151A (ja) 半導体装置およびその製造方法
JPS60121795A (ja) 多層配線板の製造方法