JPS60142537U - Nonlinear digital-to-analog converter - Google Patents

Nonlinear digital-to-analog converter

Info

Publication number
JPS60142537U
JPS60142537U JP2820784U JP2820784U JPS60142537U JP S60142537 U JPS60142537 U JP S60142537U JP 2820784 U JP2820784 U JP 2820784U JP 2820784 U JP2820784 U JP 2820784U JP S60142537 U JPS60142537 U JP S60142537U
Authority
JP
Japan
Prior art keywords
circuit
signal
control signal
analog
digital
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2820784U
Other languages
Japanese (ja)
Inventor
松浦 達広
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP2820784U priority Critical patent/JPS60142537U/en
Publication of JPS60142537U publication Critical patent/JPS60142537U/en
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のディジタル−アナログ変換器の構成を示
すフ]ロック図、第2図は来者、案の実施例を示すブロ
ック図、第3図a及びbは第2図に示したノコギリ波発
生回路の出力波形を示す図である。    − 1−1〜1−n・・・・・・nビットディジタル入力信
号、2・・・・・・ゲート回路、3−1〜3−n・・・
・・・抵抗回路網入力信号、4・・・・・・抵抗回路網
回路、5・・・・・・アナログ電圧、6・・・・・・増
幅回路、7・・・・・・アナ9グ出力電圧、訃・・・・
・入力データ変更回路、9・・・・・・制゛    −
両信号発生回路、10・・・・・・カウンタ回路、11
・・・・・・データ比較回路、12・・・・・・ノ、コ
ギリ波発生回路、13・・・・・・アナログスイッチ回
路、14−1〜14−m・・・・・・基準データ選択信
号、15−1〜1  ′5−n・・・・・−nビット基
準データ、116・・・・・・タイミング信号、17・
・・・・・カウンタリセット信号、18・・・・・・カ
ウンタ駆動クロック信号、19−1〜19−(n−1)
・・・・・・カウントアツプデー′夕、20・・・・・
・サンプリング信号、21・・・・・・選択信号、22
・・・・・・ノコギリ波A123・・・・・・ノコギリ
波B124・・・・・・アナログサンプル信号。
Figure 1 is a block diagram showing the configuration of a conventional digital-to-analog converter, Figure 2 is a block diagram showing an embodiment of the proposed system, and Figures 3a and b are the saws shown in Figure 2. FIG. 3 is a diagram showing an output waveform of a wave generation circuit. - 1-1 to 1-n... n-bit digital input signal, 2... gate circuit, 3-1 to 3-n...
... Resistance network input signal, 4 ... Resistance network circuit, 5 ... Analog voltage, 6 ... Amplification circuit, 7 ... Analyzer 9 output voltage, etc.
・Input data change circuit, 9... Control -
Both signal generation circuits, 10...Counter circuits, 11
......data comparison circuit, 12..., sawtooth wave generation circuit, 13...analog switch circuit, 14-1 to 14-m...reference data Selection signal, 15-1 to 1 '5-n...-n bit reference data, 116... Timing signal, 17.
... Counter reset signal, 18 ... Counter drive clock signal, 19-1 to 19-(n-1)
・・・・・・Count up day 'evening, 20...
・Sampling signal, 21...Selection signal, 22
...Sawtooth wave A123...Sawtooth wave B124...Analog sample signal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 、   入力されるディジタル信号に対し、任意のアナ
ログ電圧を出力するための前記ディジタル入力信−号を
変更する入力データ変更回路と、制御信号を発生する制
御信号発生回路と、この制御信号発生回路によってディ
ジタル信号をカウントアツプする一カウント回路と、前
記入力データ変更回路から、  −供給される基準デー
タと前記カウンタ回路から供、  給されるカウントア
ツプデータとを比較照合するデータ比較回路と、2種類
のノコギリ波を発生するノコギリ波発生回路と、前記デ
ータ比較回路からの制御信号によりノコギリ波発生回路
で発生し−たアナログ信号をサンプリングするアナログ
スイッチ回路と、サンプリングされたアナログ信号を増
幅する増幅回路とを備えてなることを特徴とする非直線
ディジタル−アナログ変換器。
, an input data changing circuit that changes the digital input signal to output an arbitrary analog voltage in response to the input digital signal; a control signal generating circuit that generates a control signal; and a control signal generating circuit that generates a control signal. A count circuit that counts up a digital signal, and a data comparison circuit that compares and verifies the reference data supplied from the input data change circuit and the count up data supplied from the counter circuit; a sawtooth wave generation circuit that generates a sawtooth wave; an analog switch circuit that samples the analog signal generated by the sawtooth wave generation circuit according to a control signal from the data comparison circuit; and an amplifier circuit that amplifies the sampled analog signal. A nonlinear digital-to-analog converter comprising:
JP2820784U 1984-02-28 1984-02-28 Nonlinear digital-to-analog converter Pending JPS60142537U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2820784U JPS60142537U (en) 1984-02-28 1984-02-28 Nonlinear digital-to-analog converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2820784U JPS60142537U (en) 1984-02-28 1984-02-28 Nonlinear digital-to-analog converter

Publications (1)

Publication Number Publication Date
JPS60142537U true JPS60142537U (en) 1985-09-20

Family

ID=30525877

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2820784U Pending JPS60142537U (en) 1984-02-28 1984-02-28 Nonlinear digital-to-analog converter

Country Status (1)

Country Link
JP (1) JPS60142537U (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0192797A (en) * 1987-10-05 1989-04-12 Hitachi Ltd Halftone display device
JPH02264295A (en) * 1989-04-04 1990-10-29 Sharp Corp Display device
JPH02264294A (en) * 1989-04-04 1990-10-29 Sharp Corp Driving circuit for display device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0192797A (en) * 1987-10-05 1989-04-12 Hitachi Ltd Halftone display device
JPH02264295A (en) * 1989-04-04 1990-10-29 Sharp Corp Display device
JPH02264294A (en) * 1989-04-04 1990-10-29 Sharp Corp Driving circuit for display device

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