JPS60138594A - Time base inverting circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a digital image processing circuit. In particular, the present invention relates to a circuit for reversing the time axis of an image.

[Description of Prior Art] ゛The time axis reversal circuit is used for the special effect of horizontally reversing television images;7. Further, this circuit has a wide range of uses, such as being used in combination with a recursive filter to compensate for the phase delay of the recursive filter and optimize amplitude characteristics.

FIG. 1 is a circuit diagram showing the configuration of a conventional time axis inverting circuit. An image signal is input to terminal -F1, and an image signal whose time axis is reversed with respect to the input image year is output from terminal 2. When the switching signal input to terminal 3 is a line flip-flop signal (hereinafter referred to as an LFF signal) that switches for each scanning line, the period of this inversion is the time corresponding to the image signal for one scanning line. In addition, when the switching signal is a field-off signal (hereinafter referred to as FO/E signal) that switches every one image field, the time corresponds to the image signal for one image field.

The operation when the L and FF signals are input to the terminal 3 will be described below. When the LFF signal is at the ruJ level, the connection state of the selector circuit 30 is such that the output of the up counter 20 is connected to the address input of the RAM circuit IO, and the output of the down counter 25 is connected to the address input of the RAM circuit 15. In the RAM circuit 10, this input gate is opened, the trench output gate is closed, and the RAM circuit 15 is controlled so that this input gate is closed and the output gate is closed. opened,
Furthermore, it is controlled to be in a read state.

Therefore, in the RAM circuit 10, information for one scanning line is stored in the RAM circuit 10 while being addressed so that the number of addresses increases from the smallest address (hereinafter referred to as up-count addressing). . On the other hand, RAM
In the circuit 15, the information of the previous scanning line of only one of the scanning lines for which the write operation is being performed in the R, AM circuit 1O is being written in, and the information is being written in synchronization with the operation of the RAM circuit 10. , information for one constant scanning line is read out from the RAM circuit 15 while being addressed in such a way that the number of addresses decreases from the maximum address where the information is stored (hereinafter referred to as down count addressing). That is, in this process, an image signal whose time axis is inverted with respect to the input image signal is output.

Next, when the birFfg signal is inverted to the rLJ level, the connection state of the selector 30 and the input states of the terminals of the RAM circuit 10 and the RAM circuit 15 are inverted, and the RAM circuit 10 performs a read operation, and the RAM circuit 15 performs a write operation. is executed. By alternately and repeatedly performing these two types of operations, the image signal time axis is inverted in real time.

However, this device uses two counters, is provided with a selector circuit, and requires two systems of address buses, which has the drawback of complicating the circuit.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a circuit for controlling a memory circuit of a time axis inversion circuit and a circuit with simplified connections.

[Key points of the invention]

The present invention simplifies the circuit configuration of the time axis inverting circuit, and includes two RAM circuits, and at a predetermined period, the above-mentioned RAM
When one of the M circuits is in a read state, the other RAM circuit is in a write state, and the write address and the read address are shifted by a time axis inversion circuit so that their order is reversed. , one counter capable of up-counting and down-counting, and configured to give a common address signal to the above two RAM circuits from this one counter, and this counter is synchronized with the above cycle. The present invention is characterized in that the up-count addressing and down-count addressing are performed alternately.

[Explanation based on examples]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A circuit according to an embodiment of the present invention will be described below based on the drawings. FIG. 2 is a circuit diagram showing the configuration of this embodiment circuit.

First, the configuration and connections of this example circuit will be described.

This embodiment circuit is composed of RAM circuits 10 and 15, a counter circuit, and a signal inversion circuit 5.

An image signal source (not shown) is connected to the RA via terminal l.
The M circuits are connected to the input terminals of the RAM circuit 150, and the output terminals of the RAM circuit IO and the RAM circuit 15 output image signals to the outside via the terminal 2. The LFF signal is connected via the terminal 3 to be input to the even-odd terminals of the RAM circuit 10, the read/write terminals of the RAM circuit 15, and the signal inversion circuit 5. The output of the Ib inversion circuit 5 is connected to the read/write terminal of the RAM circuit IO, the even/odd terminals of the RAM circuit 15, and the up/down terminals of the counter 40. A clock terminal of the counter 40 is connected via a terminal 4 to a clock signal source (not shown). The output terminal of the counter 40 is connected to each address terminal of the R, AM circuit IO and RAM circuit 15.

The feature of the present invention is the operation of the counter 4(). This operation will be explained below. First, which LP is input to terminal 3? When the signal is at the rI (J level), the counter 40 receives an address signal for performing up-count addressing to each address terminal of the RAM circuit IO and the RAM circuit 15 according to the input signal from the signal inverting circuit 5. It will be done.

Therefore, in the RAM circuit 10, the up count
While addressing is being performed, information for one scanning line is stored in the RAM'M circuit IO. On the other hand, the RAM circuit 15
1. In this case, the information of one scanning line before the scanning line being written in the RAM circuit 10 has already been written. In synchronization with the operation of the RAM circuit IO, one scanning line's worth of information is read out from the RAM circuit 15 while being subjected to up-count addressing.

However, the information written in this RAM circuit 15 is down when the LFF signal is at the "L" level.
This is information for one scanning line written while being counted and addressed. Therefore, the above-mentioned RAM circuit 1
The reading in 5 is also performed when the LFF signal is inverted to the "L" level, and the time axis from the RAM circuit 10 is inverted.

Extrusion is executed. By repeating these operations 2a@ alternately, the time axis of the image (g) is reversed in real time.

The case where the input signal to the terminal 3 is the LFF signal has been explained above, but when this input signal is FO/Fi, the time axis is reversed in field units.

〔Effect of the invention〕

As described above, the present invention provides a circuit for controlling the two circuits of the time axis inversion circuit and a connection pl? Comparing , with the conventional circuit, we find that: 1. The number of counter circuits is now 1, compared to 2 in the conventional circuit; 2. The conventional circuit required a selector circuit, but the present invention does not require it. 3. The conventional circuit had two address buses, but
In the present invention, there is only one system.

As described above, the present invention has the effect of simplifying the circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of a conventional circuit. FIG. 2 is a circuit diagram showing the configuration of the embodiment circuit. 1.2, 3.4...Terminal, 5...Signal inversion circuit, 1
0, 15...RAM circuit, 20, 25, 40-
...Counter, 30...Selector circuit. Patent applicant NEC Corporation Representative Patent attorney Naotaka Ide M2 (21

Claims (1)

[Claims] (1) It includes two RAM circuits, and is configured such that when one of the RAM circuits is in a read state at a predetermined period, the other RAM circuit is in a write state, and the write address and the read address are different. A time axis inversion circuit provided so that the order is reversed is provided with one counter that can perform up-counting and down-counting, and a common address signal from this one counter to the above two RAM circuits. , and the counter is configured to alternately perform the up-count addressing and down-count addressing in synchronization with the period.