JPS63224098A - Control signal generatng circuit - Google Patents

Abstract

PURPOSE:To miniaturize he scale of a circuit by constituting a timing signal generating part among a starting signal generating part, the timing signal generating part and a signal synthesizing part, by using a shift register. CONSTITUTION:The starting signal generating part 1 which generates a starting signal showing the point of time of the start of a processing from an inputted processing classification signal and the timing generating part 4 generating a necessary timing signal for the processing, by using the starting signal and the signal synthesizing part 2 synthesizing the necessary control signal for the processing, from the processing classification signal and a timing signal, are provided. Herein, the timing signal generating part 4 is constituted by using the shift register. Since the timing signal generating part 4 constituted of a counter and a decoder hitherto is constituted of only the shift register and an OR gate, the scale of the circuit is miniaturized.

Description

[Detailed Description of the Invention] [Summary] In a control signal generation circuit, among the start signal generation section, timing signal generation section, and signal synthesis section that are the constituent parts of this circuit, the timing signal generation section is configured using a shift register. By doing so, the circuit scale can be reduced.

[Industrial application field]

The present invention relates to an improvement in a control signal generation circuit 2, for example, a control signal generation circuit that generates control signals for a dynamic random access memory.

Generally, the number of signal lines between circuits tends to increase with the complexity of the circuit's operation, but to avoid this, the time relationship between signal lines is also used as part of the control information, and the number of signal lines increases. Techniques to reduce this are now being used.

This example will be explained with reference to FIG. 4, which is an explanatory diagram of control signals for a dynamic random access memory (hereinafter abbreviated as DRAM).

First, if 16 bits are required as a DRAM address, but there are only 8 address lines, then as shown in Figure 4 (al,
As shown in (b), the 16-bit address is divided in half by a selector.For example, the first 8 bits (this is called the row address) are row address strobe 1? In synchronization with AS, the next 8 bits (referred to as column address) are sent out in synchronization with column address strobe CAS.

At this time, if the relationship between RAS and CAS is as shown in Figure 4 (bl), the DRA old book write/read operation is performed, but as shown in Figure 4 (C), the relationship between RAS and CAS is When the relationship is reversed, a DRAM reflation/nosh operation is performed.

Now, it is necessary to reduce the circuit scale of such a control signal generation circuit as well, in accordance with the trend of miniaturization of storage devices.

[Conventional technology]

FIG. 5 is a block diagram of a conventional example, and FIG. 6 is an explanatory diagram of the operation of FIG. 5. Note that the symbols on the left side of FIG. 6 indicate the waveforms of the portions with the same symbols in FIG.

Hereinafter, the operation of FIG. 5 will be explained with reference to FIG. 6 assuming that the DRAM is controlled by a control signal.

First, for example, refresh signals and read signals.

The write signals are called processing type signals, and these signals are
When the level is high, the DRAM performs refresh/read/write operations.

Now, at the left end of Figure 6-■, ■, and ■, the processing type signals are all at L level (hereinafter abbreviated as L), so A of Figure 6-■
As shown in FIG.
outputs L.

Therefore, the counter 31 in the timing generator 3 is in a clear state, but for example, when the glue fresh in FIG.
When this happens, the clear state is released and the counter 31 starts operating, and outputs as shown in Figure 6-0 are applied from the 10 to Q2 terminals to the decoder 32.

Therefore, the decoder is set to 000, for example, as shown in Figure 6.
When is input, H is input from Y0 terminal, when it is 001, ■ is input from Y1 terminal, and so on, Y0 to Y, according to the output of the counter.
Outputs H from one of the terminals.

However, at B in Figure 6-■, it becomes L again, so the counter 3
1 becomes a clear state and repeats this process.

The output from the decoder 32 (i.e., the timing signal) is sent to the OR gates 21 to 24 in the signal synthesis section 2 in FIG.
A switching write/read switching signal that drives the selector 25 as shown at @ is used for reading when WE is H.

Then, NAND gate 26~2 days and OR gate 22~
The output of 24 is NANDed with the start signal indicating the processing start time from OR gates 1 and 12, and the result is
Synthesize the RAS, CAS, and WE control signals as shown in [Phase].

For example, when a 16-bit address is input, the row address selected by the selector 25 driven by the output of the OR gate 21 becomes RA as shown in FIG.
After being sent out in synchronization with S, the column address is sent out in synchronization with CAS.

[Problem that the invention seeks to solve]

However, since a counter and a decoder are used to generate the timing signal, there is a problem in that the circuit size increases.

[Means for solving problems]

The above problems are solved by the control signal generation circuit shown in FIG. 4 is a timing signal generating section configured using a shift register.

[Effect]

In the present invention, a shift register is used in the timing signal generating section 4 to generate a timing signal.

Conventionally, this has been generated using a counter and a decoder, which reduces the circuit scale.

〔Example〕

FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is an explanatory diagram of the operation of FIG. 2. Note that the same reference numerals indicate the same objects throughout the figures. Further, the symbols on the left side of FIG. 3 indicate the waveforms of the portions with the same symbols in FIG.

The operation of the timing signal generator, which is a part of the present invention, will be described below with reference to FIG. 2.

First, H shown on the left side of FIG. 3 is applied from the OR gate 11 only to the 00 terminal of the shift register 41.

At this time, the LOAD terminal has H as shown on the left side of Figure 3-0.
is added, the H of the +OS terminal is loaded and the H is output from the Q0 terminal as shown in FIG. 3--00. However, as shown in FIG. 3--, the L level from the NOR gate 42 is applied to the LOAD terminal, so the output of the OR gate 11 input at the next timing is not loaded.

On the other hand, the loaded H is shifted one after another by the clock shown in Figure 3-■, from 00 to Q, and an output as shown in Figure 3-■ is obtained from the terminal, but if all the H level signals pass through, Since the output of the NOR gate 42 becomes H as shown in FIG. 3-2, the above operation is repeated.

Therefore, since we were able to obtain the same output as shown in Figure 6-■ using a shift register, we can combine the output of the shift register 41 with the OR gate 11.1 shown in
OR gates 21 to 24 and NAND using the output of 2
At gates 26 to 28, RAS and C shown in Figure 3-〇 to ■
AS, WE control signals and selector switching signals are synthesized.

That is, since the timing signal generation section made up of a counter and a decoder is made up of only a shift register and an OR gate, the circuit scale is reduced.

〔Effect of the invention〕

As described in detail above, according to the present invention, the effect of reducing the circuit scale can be obtained.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 is an explanatory diagram of the operation of Fig. 2, Fig. 4 is an explanatory diagram of DRAM control signals, Fig. 5 6 is a block diagram of a conventional example, and FIG. 6 is an explanatory diagram of the operation of FIG. 5. In the figure, 1 is the start signal generating section, 2 is the signal synthesizing section, and between Kiari ≦, the team is in charge of the operation. ■■■ ■[phase] ■

Claims (1)

[Scope of Claims] A start signal generation section (1) that generates a start signal indicating a processing start point from an input processing type signal, and a timing signal generation section that uses the start signal to generate a timing signal necessary for processing. (4) and a signal synthesizing section (2) that synthesizes a control signal necessary for processing from the processing type signal and the timing signal, in which the timing signal generating section (4) is connected to a shift register. A control signal generation circuit characterized in that it is configured using.