JPS61241851A - Reading circuit - Google Patents

Abstract

PURPOSE:To attain the correspondence between the addresses and data by using a high-speed data read/write circuit to write the low-speed data given from a low-speed data read circuit to the same address of a high-speed memory circuit and to read out the written high-speed data when no write pulse is available. CONSTITUTION:The low-speed data D1-D11 are written to a low-speed memory circuit 2 and a high-speed clock is divided into two frequencies and applied to an address counter 1. Then the data D1-D11 of a ROM2 corresponding to the low-speed addresses A1-A11 sent from the counter 1 are read out and also applied to an address coincidence circuit 8. While the high-speed addresses A1-A10 corresponding to high-speed clocks are partly applied also to the circuit 8. A high level is delivered from an EX-NOR circuit 8-1 when the coincidence is obtained between addresses of both sides. This high-level output and the reverse output of the high-speed clock are applied to a NAND circuit 8-2 together with the output of a low level applied to a high-speed memory circuit RAM9. Then the low-speed data having the coincidence of addresses at its fall point is written to the same address of the RAM9. Thus the correspondence is secured between addresses and data.

Description

[Detailed Description of the Invention] [Summary] As a low-speed data reading circuit of a low-speed memory circuit that stores a control l sequence, a low-speed address that accesses the low-speed memory circuit and a high-speed address that accesses the high-speed memory circuit match in content. Then, by writing this low-speed data to the same address in the high-speed memory circuit, the data in the low-speed memory circuit can be indirectly read out at high speed.

[Industrial application field]

The present invention relates to improvements in readout circuits used, for example, in switching devices.

In recent years, there has been a trend to reduce the amount of hardware by writing all the contents of the sequences used in the switching circuit into a storage circuit. However, some memory circuits cannot read out addresses and data in correspondence when the access speed becomes high, but such memory circuits have characteristics such as low power consumption and low price, so they are widely used. There are some that are used.

Therefore, there is a need for a readout circuit that allows addresses and data to correspond even when the access speed increases.

[Conventional technology]

Figure 3 is a circuit diagram of a conventional example of a readout circuit, and Figure 4 is a circuit diagram of a conventional example of a readout circuit.
The time chart shown in the figure is shown.

Note that the numbers on the left side of Figure 4 indicate the time charts for the parts with the same numbers in Figure 3, so please refer to this figure
The operation of the circuit shown in the figure will be explained.

First, low-speed memory circuits such as read-only memory (
In the ROM (hereinafter abbreviated as ROM) 2, for example, two data DI and D2 are written in parallel, as shown in ◯ and ◯ in Fig. 4. On the other hand, in order to convert the manually inputted read clock (see Figure 4-■) to a speed that can be accessed by ROM 2,
For example, the frequency is divided by 2 in the flip-flop circuit 5 as shown in Fig. 4-■
It is converted into a two-phase clock as shown in 1. Of these clocks, the clock shown in FIG. 4-■ is added to the address counter 1, and the address ^1 shown in FIG. 4-■ is sent to the ROM 2. Data is output in parallel, not shown in ■ and ■.

These parallel data are read out by AND circuits 3 and 4 having a multiplexer function and an OR circuit 6, for example, two data of D 1.02 as shown in No. 4-2 during the period of address ^1.

[Problem that the invention seeks to solve]

However, in this conventional circuit, at address ^1, D
Since two pieces of data, I and D2, are read out, there is a problem that the address and data do not correspond.

[Means for solving problems]

The above problem is that the low-speed data corresponding to low-speed addresses 1 to (M+1) are not read out sequentially from the low-speed memory circuit at a period of 1/N of the high-speed clock, and the low-speed data reading circuit and the high-speed address 1 corresponding to the high-speed clock are required. An address-number construction circuit outputs a write pulse when both addresses of ~M and the low-speed address 1~(M+1) match, and the write pulse from the address match detection circuit is added to the high-speed storage circuit. When a write pulse is applied, the low-speed data successively output from the low-speed data reading circuit is written to the same address of the high-speed storage circuit, and when the cough write pulse is not applied, the high-speed data that has been written is not read and high-speed data read/write is performed. The problem is solved by the readout circuit of the present invention, which comprises a circuit.

[Effect]

In the present invention, a high-speed clock is frequency-divided by N and added to an address counter, and low-speed data corresponding to the output of this counter is read from a low-speed storage circuit and added to the high-speed storage circuit. However, this low-speed data is not written into the high-speed memory circuit while the low-speed address and high-speed address do not match, but is written only when they match. Therefore, addresses and data will correspond. Note that N is selected to be a value that allows access to the low-speed memory circuit.

(Embodiment) FIG. 1 is a block diagram of an embodiment of the present invention of a readout circuit.
FIG. 2 shows the time chart of FIG.

Note that the numbers on the left side of FIG. 2 indicate the time charts of the same numbered portions in FIG. Also, the second
The figure shows the case where N=2.

Also, the area within the dotted line 11 constitutes a low-speed data successive output circuit, and the area within the dotted line 12 constitutes a high-speed data read/write circuit.

First, low-speed memory circuits such as read-only memory (
Low-speed data D1 to D11 are written in the ROM (hereinafter abbreviated as ROM) 2, as shown in FIG.

In addition, 2, 3... is 82. A3 or D 2. D3・
・Indicates.

Then, the high-speed clock shown in Figure 2-0 is set to N=2, that is, 2
The frequency is divided and added to address counter 1, and the ROM corresponding to 11 is added to the low-speed address from 7 address counter l.
2 data D1 to D11 are read out, and the address -
Add several components to the output circuit 8.

On the other hand, a part of the high-speed addresses ^1 to Δ10 shown in Figure 2-0 corresponding to the high-speed clock shown in Figure 2-0 is also added to the address-number configuration circuit 8, and when the two addresses match, The EX-NOR circuit 8-1 outputs a high level as shown in FIG. 2--.

Note that the reason why the low-speed address is one address lower than the high-speed address is to ensure that there is always a point where the addresses match.

This high level output and the inverted output of the high speed clock as shown in Figure 2-■ are added to the NAND circuit 8-2 and the second
The low level output as shown in Figure -■ is used in high-speed storage circuits such as random access memory (hereinafter abbreviated as RAM).
Added to 9.

Therefore, low-speed data with matching addresses are written to the same address in the RAM 9 at the falling edge of FIG.

Note that while the addresses do not match, the data corresponding to the high-speed address in Figure 2-■ (see Figure 2-■°) is stored in the RAM 9.
The data is read out from the buffer circuit 10 at the rising edge of the clock shown in FIG. 2-1, and is outputted as shown in FIG. 2-2.

〔Effect of the invention〕

As explained above, since data in the low-speed ROM is written to the high-speed RAM at the same address and read out at high speed, there is an effect that the address and data correspond.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
3 shows a circuit diagram of a conventional example, and FIG. 4 shows a time chart of FIG. 3. In the figure, ■ is an address counter, 2 is a ROM, 7 is a frequency divider, 8 is an address match circuit, 9 is a RAM, 10 is a buffer circuit, 11 is a low-speed data continuous output circuit, 12 is a high-speed data read/write circuit shows.

Claims (1)

[Claims] Low-speed addresses 1 to (M
+1) Sequential low-speed storage circuit (2) for low-speed data corresponding to
a low-speed data reading circuit (11) that reads data from the high-speed clock, and an address match detection circuit (8) that outputs a write pulse when the high-speed addresses 1 to M corresponding to the high-speed clock match the low-speed addresses 1 to (M+1). When the write pulse from the address match detection circuit is applied to the high speed storage circuit (9), the low speed data read circuit (9)
The low speed data read from the high speed storage circuit (9
), and reads out the written high-speed data when the write pulse is not applied.