JPS61241851A - Reading circuit - Google Patents

Abstract

PURPOSE: To attain the correspondence between the addresses and data by using a high-speed data read/write circuit to write the low-speed data given from a low-speed data read circuit to the same address of a high-speed memory circuit and to read out the written high-speed data when no write pulse is available.

CONSTITUTION: The low-speed data D1WD11 are written to a low-speed memory circuit 2 and a high-speed clock is divided into two frequencies and applied to an address counter 1. Then the data D1WD11 of a ROM2 corresponding to the low-speed addresses A1WA11 sent from the counter 1 are read out and also applied to an address coincidence circuit 8. While the high-speed addresses A1WA10 corresponding to high-speed clocks are partly applied also to the circuit 8. A high level is delivered from an EX-NOR circuit 8-1 when the coincidence is obtained between addresses of both sides. This high-level output and the reverse output of the high-speed clock are applied to a NAND circuit 8-2 together with the output of a low level applied to a high-speed memory circuit RAM9. Then the low-speed data having the coincidence of addresses at its fall point is written to the same address of the RAM9. Thus the correspondence is secured between addresses and data.

COPYRIGHT: (C)1986,JPO&Japio