JPH01166147A - Memory control circuit - Google Patents

Abstract

PURPOSE:To simultaneously connect a SRAM and a DRAM to one memory control circuit by sending an address signal at the time of designating the DRAM and a bite address signal at the time of designating the SRAM from an address control circuit. CONSTITUTION:At the time of a DRAM write, a line address is outputted to A0-A8 and it is latched to a memory by a RAS signal. Continuously, a digit address is outputted and latched by a CAS signal. At this time, the data of the DRAM are not passed through a series parallel circuit 4 and inputted and outputted in a basic cycle. At the time of a SRAM write, a bite address is sent to A3-A17 buses and the CAS signal is used as a chip select signal. The input output of the data is executed in a period 1/8 as much as the basic signal. Thus, the SRAM for reproducing messages and the DRAM for recording and reproducing in an automatic answering telephone system can be connected to one control circuit.

Description

[Detailed description of the invention] [Overview] Static RAM (or ROM) and dynamic R
Regarding the memory control circuit used for AM, a one-chip memory control circuit can handle static RAM and dynamic RAM.
The purpose of this design is to simultaneously connect the Dynamic RAM and Dynamic RAM to each block of the memory space. Consists of an address control circuit that sends out non-multiplexed signals, a serial/parallel conversion circuit that converts data input/output, a processing circuit, a gate circuit, and a timing generator that process and control the address control circuit and serial/parallel conversion circuit. do.

[Industrial application field]

The present invention relates to a memory control circuit used for static RAM (hereinafter referred to as SRAM) and dynamic RAM (hereinafter referred to as DRAM).

Conventionally, voice recording and playback circuits using semiconductor memory used in answering machine recording telephones, etc., have been converted into LSI as dedicated ICs, but these ICs have built-in memory control circuits, and can be used only for DRAM or SRAM (ROM). Some are dedicated or switch between DRAM and SRAM. However, even when DRAM and SRAM are used by switching between them, in actual use, one or the other is used.

In terms of product applications, there are many cases where it is desired not only to simply record and play back audio, but also to play back fixed messages. If the recording time is short, use SRAM IC.
Although RAM and ROM can be connected and used, DRAM is more economical and can be made smaller for long-term recording.

In this case, an SRAM IC is used for message reproduction.

A separate DRAM IC must be used for recording and playback. Therefore, at this time, R is applied to - recording and playback ICs.
If OM and DRAM can be connected, it will be advantageous in terms of cost and size.

[Conventional technology]

A block diagram of a conventional memory control circuit is shown in FIG. Figure (a) shows the one for DRAM connection, and Figure (b) shows the one for SRAM connection.

In the DRAM connection memory control circuit shown in FIG. 4(a), the row (RAW) address signal 8.
9~al? is sent first, and then digit (COLUMN) address signals a0 to a are sent from the address switching circuit to the memory. These address signals are transferred by the control timing signals of RAS and CAS, and processed by the processing circuit.
0 data is serially sent or read into memory. A read/write (R/W) switching control signal is sent from the timing generator. Also, the switching timing signal of row and digit address signals, RAS, CAS
Signals are also sent to control the memory.

In the memory control circuit for SRAM connection shown in FIG. 4(b), 1
Byte addresses 83-alt are always sent to the memory on the five address buses A3-Lt, so D
It does not have the address switching circuit used in RAM, and the CAS signal is also used as a chip select signal to select a memory chip. Also, a serial/parallel conversion circuit is added to convert serial data from the processing circuit into parallel data, and data 00 to D are sent to the memory in parallel.

[Problem that the invention seeks to solve]

Therefore, in the conventional memory control circuit, SRAM (ROM
) or DRAM must be fixed from the beginning, and one memory control circuit can be used for SRAM, l!
: DRAMs cannot be connected at the same time and switched. In the present invention, one memory control IC includes SRAM.
The purpose is to connect (ROM) and DRAM at the same time and switch between them for use as SRAM or DRAM.

[Means for solving problems]

A diagram of the principle of the present invention is shown in FIG. In the figure, 1 is a memory control circuit, 2 is an SRAM/DRAM specification circuit, 3 is an address control circuit, 4 is a serial/parallel conversion circuit, 5 is a processing circuit,
6 is a gate circuit, and 7 is a timing generator.

2 to 7 constitute a memory control circuit, and SRAM21 and DR
Controls switching between AMII and AMII.

The address line indicates the bit address, to 〇～to, is DR
It is connected to AM and outputted in a time-division manner, and A3 to AI7 are outputted to SRAM as byte addresses.

The data is sent serially to the DRAM, and the SR
00 to 00 are transmitted in parallel to AM. Sho RAS
, CAS is the row selection and digit selection control timing signal, R/
W indicates a read/write control signal.

[Effect]

S RAM/D RAM designation circuit 2 has a memory space of 4
Divide into two blocks, each block has SRAM or DR
Block designation is performed by providing a signal for selecting AM. The address control circuit 3 uses this block designation to
If specified, row address signals a9 to a+t are first sent to the time division address lines 0 to A and the bus, and then digit address signals 80 to as are sent to the DRAM. Also SRA
If it is rated M, is it 3~AI? The bus sends byte address signals to the SRAM. Signals RAS and CAS for latching these addresses are output from the timing generator 7 and connected to corresponding terminals of the memory.

The CAS signal also serves as a chip select signal for the SRAM, and is output only when accessing the corresponding block. The block designation of the serial/parallel converter circuit 4 is SRAM.
If specified, serial data from the processing circuit 5 is converted into parallel data, data D0 to D are connected in parallel to the SRAM, and D
If RAM is specified, serial data D0 is sent to DRAM. Note that the timing generator 7 sends an R/W signal to the memory to control reading and writing of the memory.

〔Example〕

FIG. 2 shows an embodiment of the present invention. (a) is a block diagram,
(b) shows an S/DRAM specification circuit diagram, (C) shows a serial/parallel conversion circuit diagram, and (d) shows a gate circuit diagram. Figure 2(a)
In the address control circuit 3, the address switching circuit 31
, refresh counter 32, address register L33
, an address register M34, and an address register H35, and the register is an address signal a. -a8 is launched, register M is a register that latches address signals a, ~a17, and register H is a register that latches address signals a18+
This is a register that latches al'l.

As shown in FIG. 2(b), the S/DRAM designation circuit 2
The 1 megabit memory space is divided into four blocks, each divided into blocks 0-3 with 256 bits of memory. By setting the block signal to "H" or "L", the selector specifies DRAM or SRAM. Note that by sending "H" and "L" signals to the A and B terminals, the CAS signal can be designated as a block by the decoder of the gate circuit.

As shown in Figure 2 (C), the serial-to-parallel conversion circuit consists of a shift register and an 8-1 selector, and the write data is shifted by the shift register in response to a clock signal, and data from 00 to D is sent to the memory. At the same time, the read data is read through the 8-1 selector. In case of RAM write, 0 is written without passing through the shift register.
Write data is sent to the 0 terminal.

As shown in FIG. 2(d), the gate circuit is a circuit that controls the CAS signal and the shift clock, and controls the shift clock using the lower address signals a0 to a2 from the 〇 to ^2 buses. Furthermore, signals from the address buses ^, θ, ^l from the address register H allow the decoder to latch the CAS signal by specifying a block, and also to latch the CAS signal from the timing generator.

Data read/write operations will be explained using the time yards shown in FIG. (a) is for DRAM write, (b)
is for SRAM write, (c) is for SRAM, DRAM
The case of lead is shown.

In Figure (a), in the case of DRAM write, the R/W signal indicates an "H" signal in the write state. To〇～A2 bus (
A, ~A, at the same timing), the row addresses a, ~A,
all is output and latched into the memory by the RAS signal,
Subsequently, digit addresses a0 to a2 are output and latched by the CAS signal. See you again, ~Al? The bus has an upper address a
, ~al'F are always output. However, the CAS signal is controlled by the type of memory of the block, the bit address at that time, etc. In the case of DRAM, data does not pass through a series/parallel circuit. It is output or input in basic cycles using terminals. In figure (b), in the case of SRAM write, the byte addresses are A3 to A8 and A, to Al
? The C/Is signal is sent to the bus and is used as a chip select signal for the SRAM. Data input/output is performed through the serial/parallel conversion circuit for SRAM at a period of 1/8th of the basic cycle, so
When writing to SRAM, lower address ao%
1 to the shift register until all 3 bits of az become 1
The bits are shifted bit by bit, and when all the lower addresses become 1, they are written to the memory together with the data in the shift register. Connect D and terminal by shift register. - Processing data is sent to the D6 terminal.

00-D, the data of the terminals are shifted by the shift clock. In figure (c), in the case of read, DRAM, S
It is the same with RAM, when the Rh signal becomes "L" level, CA
The data is passed through the 8-1 selector by the S signal, and the bit selected by the bit address is read.

〔Effect of the invention〕

According to the present invention, SRAM (ROM) and DRAM can be controlled simultaneously, so in a device that records and plays back audio and plays fixed messages, DRAM and RO can be controlled in one circuit.
M can be connected at the same time, which is effective in terms of cost and size.

[Brief explanation of the drawing]

Fig. 1 is a diagram of the principle of the present invention, Fig. 2 (a), (b) (C)
, (d) is a block diagram and circuit diagram of the embodiment, and (a) of FIG.
), (b), and (c) are time charts of the embodiment, and FIGS. 4(a) and (b) are block diagrams of the conventional example. In the figure, l is a memory control circuit, 2 is an S/DRAM specification circuit, 3 is an address control circuit, 4 is a serial/parallel conversion circuit,
5 is a processing circuit, 6 is a gate circuit, 7 is a timing generator, 11 is a DRAM, and 21 is an SRAM. 52 is similar

Claims (1)

[Claims] Static RAM (or ROM) and dynamic RA
In the memory control circuit used for M, each block of memory space has static RAM or dynamic RAM.
an S/DRAM designation circuit (2) that selects whether the data It consists of a serial/parallel conversion circuit (4) that converts the input/output of the S, a processing circuit (5) that processes and controls the address control circuit and the serial/parallel conversion circuit, a gate circuit (6), and a timing generator (7). /Static RAM by selecting the DRAM designation circuit
A memory control circuit characterized by switching and controlling a dynamic RAM and a dynamic RAM.