JPH0394538A - Data replacement circuit - Google Patents

Abstract

PURPOSE:To eliminate the need for complicated constitution such as duplicate constitution of memories or the like or a reset signal generating circuit or a delay circuit by generating a data of positive and reverse phase with a positive reverse phase data generating section and selecting 2 kinds of data. CONSTITUTION:A positive reverse phase data generating section 2 inputs an output at a terminal Q of an F/F circuit 11 to terminals D of 2 F/F circuits 21, 22 to connect the output from the terminal Q to input terminals A, B of a selection circuit 31 respectively. The output of the terminal Q of the F/F circuits 21, 22 is data having positive and negative half phase difference. A phase comparison section 5 receives an output signal at an output terminal Y of a selection circuit 32 and an in-station clock and compares them and outputs a phase coincidence signal when they are coincident. The switching operation is executed by the selection circuit 31 with the phase coincidence signal to switch the positive reverse phase of the output data and outputs the result, then a stored data is outputted as an in-station data in matching with the in-station phase by the in-station clock.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transfer circuit that transfers received data from a transmission line, etc., which is independent of the phase within the station, to the phase within the station without error. [Prior Art] Conventionally, this type of data transfer circuit performs writing by specifying a write address in a read/write memory, and performs reading by specifying a read address on the read side, and double arrangement is used for data protection. It was a method. In addition, when using elastic memory, the write clock and write reset signal write serial data, the read clock and read reset signal perform reading, and a phase comparison circuit is provided to protect the data. The output of the circuit controlled the switching of the delay circuit on the write side. [Problems to be Solved by the Invention] In the conventional data transfer circuit described above, when a read/write memory is used, a counter circuit for address specification is required on both the writing side and the reading side, and because of the double buffer system, Since the TF4 standard requires two physical read/write memories, there is a problem in that a large amount of mounting space is required.

Similarly, when using elastic memory, it requires a write reset signal and read reset signal generation circuit, as well as a phase comparator circuit and a delay circuit. Similarly, there was the problem that a large amount of implementation space was taken up. An object of the present invention is to provide a data transfer circuit that solves the above problems.

[Means to solve the problem]

The data transfer circuit of the present invention inputs transmission line data and generates two pieces of data with a 1/2 phase shift, respectively, in the data transfer circuit that adjusts each transmission line data to the phase within the station and outputs it as intra-station data. A positive and negative phase data generation unit, and a selection unit that inputs the two data of the positive and negative phases and switches the output from one data to the other data when a phase matching signal is received, and also outputs the phase of the data currently being output. and a phase comparison section that compares the phase output by the selection section with the phase of the local clock and outputs a phase matching signal when they match.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a functional block diagram showing one embodiment of the present invention.

In FIG. 1, this circuit includes a transmission line data latch section, a positive/inverse phase data generation section 2, a selection section 3, and an in-office data latch section 4.
, and a phase comparator 5.

The transmission line data latch unit 1 is a flip-flop (hereinafter referred to as F/
F) The circuit 11, the forward/reverse phase data generation section 2 is the F/F circuit 21, 22 and the inverter 23, the selection section 3 is the selection circuit 31, 32, and the local data latch section 4 is the F/F circuit 4.
1, respectively.

The transmission line data latch unit 1 inputs parallel-converted n-bit transmission line data to the terminal D of the F/F circuit l1, and temporarily stores it in positive phase using the transmission line clock. The forward/reverse phase data generator 2 converts the output of the terminal Q of the F/F circuit 11 into two F/F circuits.
The input signal is input to the terminal D of the F circuits 21 and 22, and the output from the terminal Q is connected to the input terminal A-B of the selection circuit 31, respectively.

The transmission line clock is input to the terminal C of the F/F circuit 22 and the inverter 23, and the output of the inverter 23 is connected to the terminal C of the F/F circuit 21, so the output of the terminal Q of the F/F circuits 21 and 22 is The data has a 1/2 phase difference between forward and reverse. The selection circuit 31 of the selection section 3 connects the terminals Q of the F/F circuits 21 and 22 to each of the input terminals A-B, and selects one terminal A-B from the other according to the phase matching signal outputted from the phase comparison section 5. Execute the connection change to output terminal Y. In the selection circuit 32, each of the input terminals A-B is F/
Since the inputs to the terminals C of the F circuits 21 and 22 are connected, the output signal from the output terminal Y matches the phase of the output data of the selection circuit 31. The local data latch section 4 is a selection circuit 31
Connect the output terminal Y of the F/F circuit 41 to the input terminal D of the F/F circuit 41,
Input data is temporarily accumulated, and when the internal clock is inputted at terminal C, the accumulated data is outputted from output terminal Q as internal data. The phase comparator 5 inputs and compares the output signal of the output terminal Y of the selection circuit 32 and the local clock, and outputs a phase matching signal when they match.

With this phase matching signal, the selection circuit 31 performs a switching operation to switch and output the positive and negative phases of the output data, so this output data is temporarily stored in the station data latch section 4 and adjusted to the station phase using the station clock. This accumulated data is output as internal data.

〔Effect of the invention〕

As explained above, the present invention generates data of positive and negative phases by a positive and negative phase data generating section, and selects these two types of data to create a duplex structure for memory, etc., or for a reset signal generation circuit and a delay circuit. This has the effect of eliminating the need for a complicated structure and simplifying it.

[Brief explanation of drawings]

FIG. 1 is a functional block diagram showing an embodiment of the data reassignment circuit of the present invention. DESCRIPTION OF SYMBOLS 1... Transmission line data latch section, 2... Positive/inverse phase data generation section, 3... Selection section, 4... Internal data latch section, 5... Phase comparison section.

Claims (1)

[Claims] In a data transfer circuit that adjusts the transmission line data to the internal phase of the station and outputs it as internal data, there is a forward and reverse phase data generation section that inputs the transmission line data and generates two data with a 1/2 phase shift, and a A selection section that inputs two data of opposite phases and switches the output from one data to the other data when a phase matching signal is received, and also outputs the phase of the data being output, and the phase that this selection section outputs. 1. A data transfer circuit comprising: a phase comparison section that compares the phase of the internal clock with the phase of the local clock and outputs a phase matching signal when they match.