JPH0455964A - Terminal equipment - Google Patents

Terminal equipment

Info

Publication number
JPH0455964A
JPH0455964A JP2166495A JP16649590A JPH0455964A JP H0455964 A JPH0455964 A JP H0455964A JP 2166495 A JP2166495 A JP 2166495A JP 16649590 A JP16649590 A JP 16649590A JP H0455964 A JPH0455964 A JP H0455964A
Authority
JP
Japan
Prior art keywords
memory
parity
user
user ram
control part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2166495A
Other languages
Japanese (ja)
Inventor
Shuji Sugiyama
修司 杉山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Gunma Ltd
Original Assignee
NEC Gunma Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Gunma Ltd filed Critical NEC Gunma Ltd
Priority to JP2166495A priority Critical patent/JPH0455964A/en
Publication of JPH0455964A publication Critical patent/JPH0455964A/en
Pending legal-status Critical Current

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  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE:To apply a parity memory as a user RAM by providing a switch means to use a parity memory area as a user memory area. CONSTITUTION:A parity control part 1 is provided together with a user RAM generation control part 2, and a switch 3. When the generation of a user RAM is set by the switch 3, a parity memory 6 functions as a user RAM. Meanwhile a memory control part 4 generates the signals of RAS, CAS, etc., to the memory 6 and the memory addresses synchronous with these signals. Then a data control part 5 converts the 1-bit data given from the memory 6 into the 8-bit parallel data in a reading state of a bus master and then reverses this operation in a writing state of the bus master respectively through a serial/parallel conversion operation. Thus the memory 6 can serve as the user RAM.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は端末装置、特に、パリティメモリのユーザＲＡ
Ｍ化機能を有する端末装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a terminal device, particularly a user RA of a parity memory.
The present invention relates to a terminal device having an M function.

〔従来の技術〕[Conventional technology]

従来の端末装置は、パリティメモリをＲＡＭに対するパ
リティ制御としてのみ存在させていた。In conventional terminal devices, the parity memory existed only as a parity control for the RAM.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の端末装置は、パリティエラー検出よりも
ユーザＲＡＭ領域の拡大を望むユーザにとっては、パリ
ティメモリが無駄な存在になるという欠点があった。The conventional terminal device described above has the disadvantage that the parity memory becomes a waste for users who desire expansion of the user RAM area rather than parity error detection.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の端末装置は、パリティメモリ領域をユーザのメ
モリ領域として使用するための切り換え手段を備える。The terminal device of the present invention includes switching means for using the parity memory area as a user's memory area.

〔実施例〕〔Example〕

次に、本発明について図面を参照して詳細に説明する。 Next, the present invention will be explained in detail with reference to the drawings.

第１図は本発明の一実施例を示すブロック図である。FIG. 1 is a block diagram showing one embodiment of the present invention.

第１図に示す端末装置は、パリティ制御部１と、ユーザ
ＲＡＭ化制御部２と、スイッチ３とを含んで構成される
。The terminal device shown in FIG. 1 includes a parity control section 1, a user RAM conversion control section 2, and a switch 3.

スイッチ３により、ユーザＲＡＭ化の設定をした場合、
パリティメモリ６はユーザＲＡＭとして動作する。If switch 3 is used to configure user RAM,
Parity memory 6 operates as user RAM.

第２図は第１図に示すユーザＲＡＭ化制御部２の詳細を
示すブロック図である。FIG. 2 is a block diagram showing details of the user RAM conversion control unit 2 shown in FIG.

メモリコントロール部４は、パリティメモリ６に対する
ＲＡＳ、ＣＡＳ等の信号およびそれに同期したメモリア
ドレス生成を行なう。The memory control unit 4 generates signals such as RAS and CAS for the parity memory 6 and a memory address in synchronization with the signals.

データコントロール部５は、パスマスタがリードすると
きは、パリティメモリ６からの１ビツトデータを８ビッ
ト並列データに変換し、ライト時はその逆の動作をする
シリアル・パラレル変換を行なう。The data control section 5 converts 1-bit data from the parity memory 6 into 8-bit parallel data when the path master reads, and performs serial-parallel conversion to perform the opposite operation when writing.

第３図（ａ）〜（Ｃ）はユーザＲＡＭ化制御部２の動作
を説明するための模式図である。FIGS. 3(a) to 3(C) are schematic diagrams for explaining the operation of the user RAM conversion control section 2. FIG.

パスマスタ７が任意のパリティメモリ６上のアドレスを
リードした場合、メモリコントロール部４は、その対応
した８回の（８ビット分の）メモリアドレスおよびＲＡ
Ｓ、ＣＡＳ等を発生し、データコントロール部５にたく
わえる。When the path master 7 reads an address on an arbitrary parity memory 6, the memory control unit 4 reads the corresponding eight times (8 bits worth) of the memory address and the RA.
S, CAS, etc. are generated and stored in the data control section 5.

そして、パスマスタデータバスに対応した８ビット並列
データがそろった時点で、パスマスタ７にデータを渡す
。Then, when the 8-bit parallel data corresponding to the path master data bus is ready, the data is passed to the path master 7.

ライトサイクルの場合は、その逆の８ビツト→１ビツト
処理を行なう。In the case of a write cycle, the reverse process is performed, from 8 bits to 1 bit.

〔発明の効果〕〔Effect of the invention〕

本発明の端末装置は、ユーザが任意にスイッチを切り替
えることにより、パリティメモリをユーザＲＡＭとして
活用できるという効果がある。The terminal device of the present invention has the advantage that the parity memory can be utilized as the user RAM by switching the switch arbitrarily by the user.

【図面の簡単な説明】[Brief explanation of the drawing]

第１区は本発明の一実施例を示すブロック図、第２図は
第１図に示すユーザＲＡＭ化制御部２の詳細を示すブロ
ック図、第３図（ａ）〜（ｃ）はユーザＲＡＭ化制御部
２の動作を説明するための模式図である。 １・・・・・・パリティＩ１１御部、２・・・・・・ユ
ーザＲＡＭ化制御部、３・・・・・・スイッチ、６・・
・・・・パリティメモリ、７・・・・・・バスマスタ。 代理人　弁理士　　内　原　　晋 工　ｌ　園 刀　２　困 （ｂ） 第 阻 ″：、区区区のくThe first section is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing details of the user RAM conversion control unit 2 shown in FIG. 1, and FIGS. 2 is a schematic diagram for explaining the operation of the conversion control section 2. FIG. 1...Parity I11 control section, 2...User RAM conversion control section, 3...Switch, 6...
...Parity memory, 7...Bus master. Agent Patent Attorney Shinko Uchihara l Sonto 2 trouble (b) No. 1”:, ku ku ku noku

Claims (1)

【特許請求の範囲】[Claims] パリテイメモリ領域をユーザのメモリ領域として使用す
るための切り換え手段を備えることを特徴とする端末装
置。A terminal device comprising switching means for using a parity memory area as a user's memory area.
JP2166495A 1990-06-25 1990-06-25 Terminal equipment Pending JPH0455964A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2166495A JPH0455964A (en) 1990-06-25 1990-06-25 Terminal equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2166495A JPH0455964A (en) 1990-06-25 1990-06-25 Terminal equipment

Publications (1)

Publication Number Publication Date
JPH0455964A true JPH0455964A (en) 1992-02-24

Family

ID=15832430

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2166495A Pending JPH0455964A (en) 1990-06-25 1990-06-25 Terminal equipment

Country Status (1)

Country Link
JP (1) JPH0455964A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102703099A (en) * 2012-06-19 2012-10-03 安徽明太生物科技有限公司 Vertical moving bed rice hull carbonization furnace and rice hull carbonizing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102703099A (en) * 2012-06-19 2012-10-03 安徽明太生物科技有限公司 Vertical moving bed rice hull carbonization furnace and rice hull carbonizing method thereof

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