JPS63180154A - Semiconductor memory of page address system - Google Patents

Abstract

PURPOSE:To select a desired address system by selecting a lower rank bit of a page address or a higher rank bit of an address in a page by a selection signal and inputting the selected bit to a prescribed bit of an address decoder. CONSTITUTION:When a page number switch signal 11 is equal to 1, an AND gate 6A transmits the output 14 of a latch circuit 5. Thus the signal 14 is inputted to an input terminal A4 of a column address decoder 4 via an OR gate 6C and decoded there. Therefore a page of a memory matrix 1 is designated by a page address of 2 bits which is inputted to the circuit 5 via a data bus. Thus the matrix 1 has 4(=2<2>) pages. While an AND gate 6B masks the output 12 of a column address buffer 2C. Thus the column address inputted to a decoder 4 is limited to only the signals supplied to a terminal A3. Then the intra-page capacity is equal to (2<3>X2=16). When the signal 11 is equal to 0, the signal 14 is masked by a gate 6A and the output 12 is inputted to the terminal A4 via both gates 6B and 6C and decoded there. As a result, the number of pages are cut down in half together with double capacity.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a page address type semiconductor memory device.

[Conventional technology]

Generally, the page address method uses CP without any external parts.
It is used to manage a memory space larger than the address space of U.

FIG. 6 is a block diagram of a conventional example of a page address type semiconductor memory device, and FIG. 7 is a diagram illustrating the allocation of 10 pages of a memory matrix in the conventional example of FIG. 6.

This memory matrix 1 has addresses O to 63, addresses O to 15, addresses 16 to 31, addresses 32 to 47,
48~631! The addresses are 1 page, 2 pages, 3 pages, and 4 pages, respectively, and the 6-bit address Ao
, A1. ..., A5 is given. The row address of this memory matrix 1 consists of the lower three bits Ao, A1 .
A2, and the column address is the upper 3 bits A3
．． A4. 2 bits of A5 A4. A, 5 is the page address (equal to the page number minus 1), 1 bit A3
is given as a column address within the page.

The case of reading data from this semiconductor storage device will be explained. First, out buffer 8 is output enable signal @
OE puts it in a high impedance state. After this,
A page address is output onto data bus 10 and latched by latch circuit 5 in response to write signal W-E. on the other hand,
An address is output onto the address bus 9, the lower 3 bits are taken into the row address buffer 2R, and the higher 1 bit is taken into the column address buffer 2C. The row address decoder 3 decodes the row address of the memory matrix 1 from the address of the O address puffer 2R and outputs O selection signals. On the other hand, the column address decoder 4 receives the page address 2 bits from the latch circuit 5 at the input terminal A4.
．． At A5, one bit of the in-page column address is input from the column address buffer 2C to the input terminal A3, decoded, and a column selection signal is output.

As described above, the specified address in the memory matrix 1 is accessed. Note that the column address decoder 4 converts the column addresses A3 to A6 of the memory matrix 1 into upper two bits A4. The operation is exactly the same as that of the row address decoder 3, except that A5 (page address) and the lower 1 bit A3 (intra-page column address) are input separately.

By inputting part of the column address as a page address from the data bus 10 in this way, it is possible to manage a memory space larger than the address space of the CPU.

[Problem that the invention seeks to solve]

In general, when the number of pages is large, the memory space that can be managed by the CPLJ is also large, but page switching may occur frequently.On the other hand, when the number of pages is small, the memory space that can be managed by the CPU is small, but There is a possibility that fewer page changes will be required.

However, the above-mentioned conventional page address semiconductor memory device has a fixed number of pages determined by the manufacturer, and therefore has the disadvantage that it is difficult for users to handle.

[Means for solving problems]

The page address type semiconductor storage device of the present invention has a memory matrix in which a column address is given by a page address and a column address within a page, a row address buffer that takes in a row address from an address bus, and the output of the row address buffer as input. , a row address decoder that outputs a row selection signal to the memory matrix, and a latch circuit that latches a page address from a data bus.
Switch the number of pages between the column address buffer that takes in the column address within the page from the address bus, the lower n bits of the page address latched in the latch circuit, and the upper n bits of the address within the page output from the column address buffer. The page number switching circuit that selects and outputs based on the signal, the lower bits other than the upper n bits of the column address within the page that the column address buffer outputs, the output of the page number switching circuit, and the page latched by the latch circuit. It has a column address decoder that receives upper bits other than the lower n bits of the address and outputs a column selection signal to the memory matrix.

[Operation] In this way, by selecting either the lower bit of the page address or the upper bit of the intra-page address by the selection signal and inputting it to the predetermined bit of the address decoder, the number of pages can be reduced even though the storage capacity per page is small. It is possible to select a page address method with a large number of pages, or a page address method with a large storage capacity per page but with a small number of pages, and it is possible to provide a page address method semiconductor memory device suitable for use by users.

(Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the page address type semiconductor memory device of the present invention, FIG. 2 is a diagram explaining the page allocation of the memory matrix 1 in this embodiment, and FIGS. 3 and 4 are respectively 2 is a circuit diagram of a page number switching circuit 6 and a page number switching signal generation circuit 7. FIG.

In this embodiment, a page number switching circuit 6 and a page number switching signal generation circuit 7 are added to the page address type semiconductor memory device shown in FIG. is input to the page number switching circuit 6, the other high-order 1 bit 15 is input to the input terminal A5 of the column address decoder 4 as in the conventional device, and the in-page column address (2 bits) output from the address buffer 2C is input to the page number switching circuit 6. ), the upper 1 bit 12
is input to the page number switching circuit 6, and the other 1 bit 13 is input to the input terminal A3 of the column address decoder 4 like the conventional Sa.

The page number switching signal generation circuit 7 is composed of N-channel FETs Trl and Tr2 whose gates and sources are connected and which are connected to each other in cascade as shown in FIG.
The positive and negative electrodes of a power source (not shown) are connected to the drain of the FET Trl and the source of the FET Tr2, respectively. Connection point of cascade connection is page number switching signal 1
1 output end.

This circuit outputs "1" or "0" as the page number switching signal 11 by implanting ions into either FET Trl or Tr2.

As shown in FIG. 3, the page number switching circuit 6 is composed of AND gates 6A, 6B, an OR gate 6C, and an inverter 6D. This is a 2-man power, 1-output multiplexer.

Next, the operation of this embodiment will be explained.

(1) When the page number switching signal 11 is “1” (see Fig. 2)
^)). In this case, since the AND gate 6A passes the output 14 of the latch circuit 5, this page address signal 1
4 is input to the input terminal A4 of the column address decoder 4 via the OR gate 6C and decoded. Therefore, in this case, the pages of the memory matrix 1 are designated by the 2-bit page address input to the latch circuit 5 via the data bus 10, and the number of pages is 22=4. On the other hand, since the AND gate 6B masks the output 12 of the column address buffer 2C, the in-page column address input to the column address decoder 4 is only the signal input to the input terminal, and the in-page address capacity is 23x.
It becomes 2-16.

(2) When the page number switching signal 11 is “0” (Fig. 2 (
B)). In this case, the address signal 14 of the latch circuit 5 is masked by the AND gate 6A, but the output 12 of the column address buffer 2C passes through the AND gate 6B, passes through the OR gate 6C, and is input to the input terminal A4 of the column address decoder 4. decoded. therefore,
In this case, the number of pages is 2, and each page contains 12 addresses.
3×4-32, the number of pages is half that of (1), and the address capacity within the page is twice.

FIG. 5 is a circuit diagram of another example of the page number switching signal generation circuit 7.

This page number switching signal generation circuit 7 includes switches SW1.
Connect one of 8W2 with M etc. and set page number switching signal 1
1, the page number switching signal 11 is externally applied. In this way, the user can select the number of pages when using the page.

In the above embodiment, two types of page numbers can be selected, but by increasing the page number switching circuit 6 and the page number switching signal generation circuit 7, it is possible to select an even larger number of pages.

〔Effect of the invention〕

As explained above, the present invention selects either the lower bits of a page address or the upper bits of an intra-page address by a mask program or a selection signal generated by the user and inputs the selected bits to predetermined bits of an address decoder. Users can select the page address method, which has a small storage capacity per page but a large number of pages, or the page address method, which has a large storage capacity per page but a small number of pages. A storage device can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the page address type semiconductor memory device of the present invention, FIG. 2 is a diagram illustrating page allocation of the memory matrix 1 in this embodiment, and FIG. 3 is a page number switching circuit 6. , FIG. 4 and FIG. 5 are circuit diagrams of the page number switching signal generation circuit 7, FIG. 6 is a block diagram of a conventional example of a page address type semiconductor memory device, and FIG. 7 is a conventional example of FIG. 6. FIG. 2 is a diagram illustrating page allocation of a memory matrix 1 in FIG. 1...Memory matrix, 2R...Row address buffer, 2C...Column address buffer? , 3... Row address decoder, 4... Column address decoder, 5... Latch circuit, 6... Page number switching circuit, 7... Page number switching signal generation circuit, 8... Out buffer? , 9...Address bus, 10...Data bus, 11...Page number switching signal, 12.13...Intra-page column address signal, 14.
15... Page address signal, 6A, 6B... AND gate, 6C... OR gate, 6D... Inverter.

Claims (1)

[Claims] A memory matrix in which a column address is given by a page address and a column address within the page, a row address buffer that receives a row address from an address bus, and an output of the row address buffer is input to select a row in the memory matrix. A row address decoder that outputs a signal, a latch circuit that latches a page address from the data bus, a column address buffer that takes in a column address within a page from the address bus, and a lower n of page addresses latched in the latch circuit.
A page number switching circuit that selects and outputs one of the upper n bits of the in-page column address output from the bit and column address buffer using a page number switching signal; and Input the lower bits other than n bits, the output of the page number switching circuit, and the upper bits other than the lower n bits of the page address latched in the latch circuit,
A page address type semiconductor memory device having a column address decoder that outputs a column selection signal to a memory matrix.