JPH08172342A - Digital filter - Google Patents

Abstract

PURPOSE: To reduce chip size for LSI while executing operation similar to conventional operation by a data storing part in a digital filter using a ROM table. CONSTITUTION: A data storing part for storing the data of i words consisting of j-bit data successively inputted to an input register 30 is constituted of a static RAM 40 to be accessed from both of bit direction and word direction, i-bit data successively read out from the RAM 40 are supplied as an address to a table storing part 33 previously storing the sum total of filter coefficients (k) and the sum total successively read out from the storing part 33 is added by an adder 340 while weighting it to obtain a digital filter output. The digital filter is provided with a memory part for (j bits ×i words), a bit pointer for specifying an address in the bit direction, a word pointer for specifying an address in the word direction, and a buffer register for temporarily storing j-bit data specified by the word pointer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital filter using a summation table of filter coefficients composed of ROM or the like without using a multiplier.

[0002]

2. Description of the Related Art F is a typical example of a digital filter.
The IR filter is generally configured as shown in FIG. FIG. 8 shows a 13th-order FIR filter, which includes delay elements 1 to 12 that sequentially delay the input data Xn for one sampling period, and adders 13 to 18 that add the respective data.
It is composed of multipliers 19 to 25 that multiply the addition result by a coefficient km, and an adder 26 that adds the multiplication result.

Here, when the data X is represented by a two's complement, it is expressed by the equation (1),

[0004]

[Equation 1]

The filter coefficient is set to km (m = 0 to 6): 1
Assuming that the coefficient is a 6-bit coefficient, the output Yn is expressed by the equation (2).

[0006]

[Equation 2]

Here, the value in the parentheses shown in the following equation (3) is

[0008]

(Equation 3)

Since it is the result of 1-bit addition and the value is 0 or 1, the total sum of km according to the value of X is RO
If it is stored in M or the like as a table, the value in curly brackets in the equation (2) can be read from this sum table by using X as an address. Therefore, the FIR output Yn can be obtained without using a multiplier. Can be asked. Next, a conventional configuration of a digital filter using such a ROM table will be described with reference to FIG.

The input j-bit data is first input to the input register 30 and stored in the data storage unit 31 via this register. The data storage unit 31 stores j-bit data for i words corresponding to the degree i, and is usually configured by using i j-bit shift registers. i shift registers 301, 302, 30
.. are serially connected, and the LSB or MSB of each shift register is connected to the input of the ROM pointer register 32 at the next stage. And 1
R is shifted by 1 bit in the sampling period.
The contents of the OM pointer register 32 are updated. The ROM pointer address 32 is for addressing the ROM table 33 in which the sum of the above-mentioned coefficients km is stored in the form of a table.
From the table 33, the total sum of the coefficients according to the data X, that is, the value in the curly braces in Expression (2) is read.

The sequentially read sums are sequentially added by the arithmetic unit 34 including the adder 340 while being weighted by the equation (2), and the output Yn is output from the output register 35.
Is obtained.

[0012]

In the conventional configuration, the shift register is used as the data storage section,
A latch is usually used as an element constituting the shift register, but the static type is preferable because the shift register is used once in one sampling period. However, the static type latch occupies a very large area when integrated into an LSI, which leads to an increase in chip size.

Therefore, it is conceivable to use a dynamic type latch, but when the shift cycle is long or when the shift is temporarily stopped, the charge may be discharged and malfunction may occur. However, there is a problem in that the control becomes complicated.

[0014]

SUMMARY OF THE INVENTION The present invention provides an input register for inputting j-bit data, a data storage unit for storing i-word data of j-bit units sequentially input to the input register, and a filter coefficient. Is stored in advance, data that is sequentially read from the data storage unit every i bits is input, and a pointer register that specifies the address of the table storage unit by output is sequentially read from the table storage unit. The above problem is solved by providing an adder that adds the total sum weighted while adding the data sum, and by configuring the data storage unit with a static RAM circuit that is accessible from both the bit direction and the word direction.

The present invention also provides the static RAM described above.
It is characterized in that the circuit has a memory portion of j bits × i words, a bit pointer for designating an address in the bit direction, and a word pointer for designating an address in the word direction. The present invention also provides the static RAM described above.
The circuit further includes a j designated by the word pointer.
It is characterized by having a buffer register for temporarily holding bit data.

The present invention also provides the static RAM described above.
A circuit sets the word pointer to 0 and writes the j-bit data set in the input register to a word address 0 in response to the data being set in the input register, and then the bit By sequentially incrementing the pointer from 0 to j−1, i-bit unit data from bit addresses 0 to j−1 are sequentially read, and after reading, the word pointer is set to i.
-2, and then the j-bit unit data indicated by the word address is temporarily stored in the buffer register, and after the storage, the word pointer is incremented and the temporarily stored data is stored in the next word of the read address. It is characterized in that a series of shift processes for writing addresses are sequentially executed for word addresses i-2 to 0.

[0017]

According to the present invention, since the data storage section is composed of the static RAM circuit which can be accessed from both the bit direction and the word direction, it can be used in the same manner as the shift register using the static latch and the occupied area is reduced. Get smaller. Further, by incrementing the bit pointer, addresses can be sequentially input to a pointer register that designates an address in the table storage unit, and by word-direction shift processing using a buffer register and a word pointer, a j-bit unit word data shift operation is performed. Is realized.

[0018]

1 is a block diagram showing the structure of an embodiment of the present invention, and the same structures as those in FIG. 7 are designated by the same reference numerals. Here, the characteristic configuration is the data storage unit 40.
The data storage unit 40 is composed of a static RAM circuit that can be accessed in both the bit direction and the word direction.

A static RAM circuit is roughly
As shown in FIG. 1, a memory portion 4 of j bits × i words
01, a bit pointer 402 for designating a bit-direction address, a word pointer 403 for designating a word-direction address, and a buffer register 4 for temporarily holding j-bit data designated by the word pointer 403.
04 and a timing generation circuit 405.

The general operation of the static RAM circuit 40 will be described below with reference to FIG. First, in the memory portion 401 of the static RAM circuit 40, the current sampling data is stored at word address 0,
The larger the word address, the more data sampled in the past is stored,
The oldest data stored in word address i-1 will be discarded at the next sample.

Therefore, when j-bit data is set in the input register 30, both the bit pointer 402 and the word pointer 403 are set to 0, and the word address 0 indicated by the word pointer 403 is set in the input register 30. j-bit data is written. That is, writing in the word direction is performed. Next, the bit address indicated by the bit pointer 402 is 0 to 1 bit × i.
A word, i.e., i-bit data is read into the ROM pointer register 32, and then the bit pointer 402 is sequentially incremented.
Bit data is read. That is, bit data is sequentially read from the bit addresses 0, 1, 2, ..., J−1 in i-bit units, and reading in the bit direction is realized.

When the data reading in the bit direction is completed in this way, the word data shifting process by the writing and reading in the word direction is next executed.
Since this processing is performed after the reading in the bit direction is completed, i-2 is set in the word pointer 403 after the bit pointer 402 counts j-1.

Then, j-bit word data is read from the word address i-2 indicated by the word pointer 403, transferred to the buffer register 404, and temporarily held there. Then, the word pointer 403 is incremented, and the word data held in the buffer register 404 is written at this word address i-1.
After that, the word pointer is decremented by -2, and the same processing is performed on the word address i-3. That is, the data of a certain word address is read out and temporarily stored in the buffer register 4
After the data is held in 04, the word data is shifted by writing the data held in the word address next to the read word address.
Such shift processing is performed by word addresses i-1 to 0.
For each address up to and shifting all the data in the word direction. By this operation, new data can be input to the word address, and the data order is maintained.

When i-bit data is sequentially input to the ROM pointer register 32, these data are supplied to the ROM table 33 as sequential addresses.
Here, among the total sums of the coefficients shown in the curly brackets of the equation (2), the total sums corresponding to 2 0, 2 1 ... Then, S0, S1, ………
..., S15.

[0025]

[Equation 4]

Then, S0 is first output from the ROM table 33, is set in the shift register 341 via the adder 340, and is downshifted here to be divided into ½, and the next sum is added. S1 is R
When output from the OM table 33, S0 divided by S1 is added in the adder 340. And so on
The addition result is divided by the shift register 341, and a new total sum is added to this. Therefore, as a result, the sum total of Expression (2) is output from the calculation unit 34 to the output register 35.

However, since the highest power of 2 to the 15th power must be negative, the 2's complement processing unit 342 inverts the output sum S15 and adds 1 to this, and the result is sent to the multiplexer 343. Is output via. Of course, in the multiplexer 343, in other cases, R
The output of the OM table 33 is selected as it is. next,
Specific circuits of the bit pointer 402 and the word pointer 403 will be described.

FIG. 3 is a diagram showing a concrete circuit example of the bit pointer 402 and the word pointer 403. The bit pointer 402 is a five-stage D-type flip-flop 501.
502, 503, 504, 505, NOR gate 50
6, EX-OR gates 507, 508, 509, 51
0, AND gates 511, 512, 513, and the word pointer 403 is a four-stage D type flip-flop 601, 602, 603, 604, an edge detection circuit 7.
00, NOR gate 605, EX-OR gate 606,
607, 608, 609, 610, 611, OR gates 612, 615, 616, 617, 618, AND gates 613, 614, 619, 620, 621, 622.
623, 624, 625, 626.

The bit pointer 402 is a counter that operates only when the counter control signal 1 from the timing generation circuit 405 is L, and otherwise operates in the same manner as a normal counter. That is, when a data set signal indicating that data has been set in the input register 30 is output from the timing generation circuit 405, the bit counter 402 is reset, and thereafter, according to the count clock, as shown in FIGS. Simply repeat the count up as shown. Then, when the count content becomes j = 16, the counter control signal 1 becomes H level, the operation of the counter is stopped, and at the same time, the edge detection circuit 700 detects that the last bit BP3 becomes 1, and the word pointer Set 403 to i-2 = 11.

As shown in FIG. 4, the word pointer 403 operates only when the counter control signal 2 from the timing generation circuit 405 is at L level, and in addition to this, a read from the timing generation circuit 405 as a control signal. The write signal R / W is input. This signal R / W is a control signal for the memory and determines whether the counter operation is to be -2 or +1.
When the level is -2, the level is -2, and when the level is L, the level is +1. Therefore, as shown in FIGS. 4A to 4C, +1, -2, +1 and -2 are sequentially repeated from the initial setting value 11 and the process is terminated when the word address becomes 0. By this operation, word data shift processing is realized.

Next, a concrete circuit example of the static RAM is shown in FIGS. 5 and 6, and its operation will be described in detail. Figure 5
Shows the overall configuration of the static RAM circuit 40, and includes a plurality of memory cells 80, 81, ..., 82, 8
3 are arranged in a matrix in the X and Y directions.
The memory cell 80 comprises two inverters 801 and 802, each input of which is connected to the other output,
These inverters are composed of MOS transistors. The other memory cells have the same configuration.

An N-channel MOS transistor 803 is connected to one end P of the memory cell 80, a bit line B0x extending in the Y direction is connected through its source / drain path, and an N-channel MOS transistor 803 is connected to the other end Q. A transistor 804 is connected, and an inverted bit line B0x bar extending in the Y direction is connected through a source / drain path of the transistor 804. This N channel MOS transistor 80
The gates of 3,804 are connected to the address line Ax0 extending in the X direction. The memory cells 80, 83, ..., 86 arranged in the Y direction are connected to the same bit lines B0x, B0x bars, and the memory cells 80, 81 ,. , 82 are connected to the same address line Ax0. The other memory cells have the same configuration.

Here, the addresses Ax0, Ax1, ...
, Axj-1 are address signals obtained by decoding the contents of the bit pointer 402 by the decoder 92. For example, when the address Ax0 is selected, all the memory cells 8 in the X direction connected to this address line Ax0.
The data stored in 0, 81, ..., 82 are read by the read / write circuits 93, 94, ..., 95 through the bit lines Bx0, Bx1 ,. Of course, since the read / write circuit can also write, the X connected to the same address line
Writing to all memory cells in the same direction is also possible. However, this writing is not necessary to configure the digital filter.

Further, in the memory cell of this embodiment,
Another N-channel MOS transistor 805 is connected to one end P of the memory cell 80, a bit line B0y extending in the X direction is connected through its source / drain path, and the other end Q is connected to another N-channel MOS transistor 805. N channel M
The OS transistor 806 is connected, and the inverted bit line B0y bar extending in the X direction is connected through the source / drain path thereof. The gates of the N-channel MOS transistors 805 and 806 are connected to the address line Ay0 extending in the Y direction. The memory cells 80, 81, ..., 82 arranged in the X direction are connected to the same bit lines B0y, B0y bars, and the memory cells 80, 83 ,. , 86
Are connected to the same address line Ay0. The other memory cells have the same configuration.

Addresses Ay0, Ay1, Ay2, ...
, Ayi-1 are address signals obtained by decoding the contents of the word pointer 403 by the decoder 96. For example, when the address Ay0 is selected, all the memory cells 80 in the Y direction connected to the address line Ay0,
The data stored in 83, ..., 86 are read by the respective read / write circuits 97, 98, ..., 99 through the respective bit lines By0, By1 ,. Of course, since the read / write circuit can also write, it is possible to write to all memory cells in the Y direction connected to the same address line.

In FIG. 6, read / write circuits 93, 94, ...
.., 95, 97, 98, ..., 99 will be described in more detail with reference to specific circuit examples.
The bit lines B and B-bar are connected to the input terminals of the NOR gates 102 and 103 that form the flip-flop 101, respectively, and are also connected to the power supply voltage VDD through the P-channel MOS transistors 104 and 105 for precharging. Has been done. Also, flip-flop 1
The output 106 of 01 is a clocked CMO that opens and closes according to the inverter 107 and the output enable signal OE.
It is connected to the data bus 109 via the S inverter 108.

Further, the input line 110 from the data bus 109 is connected to the bit line B bar through the clocked CMOS inverter 111 which opens and closes according to the write signal WE, and the input line 11 from the data bus 109 is connected.
2 through an inverter 113 and a clocked CMOS inverter 114 that opens and closes according to a write signal WE,
It is connected to bit line B.

The read / write signal R / W described above is used as the output enable signal OE, and the inverted signal of the read / write signal R / W is used as the write signal WE. Therefore, first, the precharge signal PR
When B becomes L level, P channel MOS
The transistors 104 and 105 are turned on, and the bit lines B and B bar are both held at the H level. Now, assuming that the memory cell connected to the bit line B stores "1", next, when the signal OE goes to H level, the output "1" of the flip-flop 101 causes the two-stage inverter 107 to operate. And 108 to the data bus 109. On the other hand, when the signal WE becomes H level after precharge, the data on the data bus 109, for example, “1”
Is inverted by the clocked CMOS inverter 111 and added to the bit line B bar, so that the bit line B bar is pulled to the L level, and the inverters 113 and 114 bring the bit line B to the H level, and therefore the data "1" is written in the memory cell connected to the bit line.

In this way, the static RAM circuit 40 can be accessed from both the bit direction and the word direction.

[0040]

According to the present invention, the occupied area can be reduced while performing the same operation as in the conventional case in the data storage section, and therefore, the chip size can be reduced in the case of an LSI.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 2 is a block diagram showing a schematic configuration of a static RAM circuit according to the present invention.

FIG. 3 is a circuit diagram showing a specific circuit of a bit pointer and a word pointer in the present invention.

FIG. 4 is a timing chart for explaining operations of a bit pointer and a word pointer according to the present invention.

FIG. 5 is a circuit diagram of a main part showing details of a static RAM according to the present invention.

FIG. 6 is a detailed circuit diagram of a read / write circuit of the static RAM according to the present invention.

FIG. 7 is a block diagram showing a conventional configuration of the present invention.

FIG. 8 is a block diagram showing a configuration of a general FIR filter.

[Explanation of symbols]

 30 input register 31 data storage unit 301, 302, 303 shift register 32 ROM pointer register 33 ROM table 34 arithmetic unit 340 adder 35 output register 40 static RAM 401 memory unit 402 bit pointer 403 word pointer 404 buffer register 405 timing generation circuit 80 , 81, ..., 88 Memory cell 92, 96 Decoder 93, 94, 95, ..., 99 Read / write circuit

Claims (4)

[Claims] 1. An input register for inputting j-bit data, a data storage unit for storing i-words of j-bit unit data sequentially input to the input register, and a table storage in which a total sum of filter coefficients is stored in advance. Unit, data sequentially read from the data storage unit every i bits are input, and a pointer register for designating an address of the table storage unit by output and a total sum sequentially read from the table storage unit are weighted and added. A digital filter, comprising: an adder, wherein the data storage unit is composed of a static RAM circuit accessible in both the bit direction and the word direction. 2. The digital filter according to claim 1, wherein the static RAM circuit has a memory portion of j bits × i words, a bit pointer for designating a bit-direction address, and a word pointer for designating a word-direction address. A digital filter having: 3. The digital filter according to claim 2, wherein the static RAM circuit further has a buffer register for temporarily holding j-bit data designated by the word pointer. 4. The digital filter according to claim 3, wherein the static RAM circuit sets the word pointer to 0 and sets it in the input register in response to data being set in the input register. Write j-bit data to the word address 0, and then increment the bit pointer from 0 to j−1 in order to obtain the bit addresses 0 to j−.
The i-bit unit data up to 1 is sequentially read, and after reading, the word pointer is set to i-2, and then,
A series of shift processes in which j-bit unit data indicated by a word address are temporarily stored in the buffer register, and after the storage, the word pointer is incremented and the temporarily stored data is written to the word address next to the read address, A digital filter characterized by being sequentially executed for word addresses i-2 to 0.