JPH06103779A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce current consumption by making a part of address signals the selection signal of a memory cell array, operating only a required memory cell array at the time of sampling and keeping the other memory cell arrays to be the out of operation state. CONSTITUTION:A pre-charging period holds when a clock signal PHI is L, word lines 101-104 become L and bit lines 107, 108 become H while the line capacities 19, 20 are pre-charged. Similarly, bit lines 105, 106 become H. Then, a sampling period holds when the signal PHI is H, and when that addresses A0, A1 are L, H, respectively, lines 101-103 remain in L and only the line 104 becomes H. Then, the capacities 19, 20 are discharged through the lines 107, 108 so that the lines become L. At this time, lines 105, 106 hold H. Since a memory cell array 2 is selected when a signal A1 is H, selectors 9, 10 select the lines 107, 108. After that, when the signal PHI becomes L, the lines 107, 108 are pre-charged but the current for pre-charging does not flow through the lines 105, 106.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a ROM (Read Only Memory) and SRA.
The present invention relates to an M (static type random access memory) circuit.

[0002]

2. Description of the Related Art Recent ROM and SRAM circuits have been increasing in scale, and accordingly, the number of address signals has increased.
The speed of word lines and bit lines has become a problem. A method of dividing a memory cell array has been adopted to solve the problem of the speed of word lines.

FIG. 3 shows an example of a ROM circuit obtained by dividing a conventional memory cell array.

As shown in FIG. 3, the ROM circuit of this example has a Pc
A memory cell array 71 including word lines 303 and 304 and bit lines 307 and 308, and memory cell array 70 having the same configuration as the memory cell array 71, using the hMOS transistors 82 and 83 and the NchMOS transistors 84, 85, 86, and 87 as memory cells. , Inverters 72, 7
3, AND circuits 74, 75, 76 and 77, selectors 78 and 79, and latches 80 and 81.
A0 and A1 are address signals, D0 and D1 are data signals,
φ is a clock signal.

In the ROM of this example, data "1" and "0" are represented by whether or not the word line is connected to the gate and the drain of the NchMOS transistor of the memory cell whose source is grounded is connected to the bit line.

In FIG. 3, when the clock signal φ is at L level, it is the precharge period, and the AND circuits 74 and 7 are provided.
5, 76, 77 output word lines 301, 302,
303 and 304 become L level, and Nch of the memory cell
The MOS transistors 84, 85, 86 and 87 are "OF".
Since it becomes "F" and the PchMOS transistors 82 and 83 are turned "ON", the bit lines 307 and 308 precharge the bit line capacitors 88 and 89 and become H level. Similarly, the bit lines 305 and 306 are also set. H level,
The latches 80 and 81 do not open and hold the previous data.

Next, when the clock signal φ is at the H level, the sampling period is reached. For example, if the address signals A0 and A1 are at the H and H levels, the output of the inverter 72 is at the L level, and therefore the AND circuits 74 and 76 are operated. The output word lines 301 and 303 remain at L level, and AN
Word lines 302 and 304 output from the D circuits 75 and 77
Changes to H level. Then NchMO of memory cell
The S transistors 84 and 85 are turned off, and NchMO
The S transistors 86 and 87 are turned on.

NchMOS transistor 8 of memory cell
6 is not connected to the bit line 307, and Nch
Since the MOS transistor 87 is connected to the bit line 308, the bit line 307 keeps the H level at the bit line capacitance 8
8 and holds the bit line 308 with the bit line capacitance 8
Since it is discharged from 9 through the NchMOS transistor 87, it changes to the L level.

Similarly, the bit lines 305 and 306 are also discharged to either the L level or the H level as it is. The potentials of the bit lines 305, 306, 307, 308 are selected by the selectors 78, 79, but the address signal A1 is set to H level.
Since it is set to the level, the inverter 73 becomes the L level, and these are input to the selectors 78 and 79 as bit line selection signals. For example, the bit lines 306 and 308 are selected and held by the latches 80 and 81 to store the data D0 and D1.
Becomes

FIG. 4 shows operation waveforms at this time.

The SRAM circuit also operates almost the same as described above except that data can be input / output and the memory cell is changed to the SRAM circuit.

[0012]

However, in the above-mentioned conventional ROM and SRAM circuits having the divided memory cell array, only the word lines are divided, so that the divided memory cell arrays are all operated. There is. This is because all bit lines connected to the selector may be discharged during the sampling period depending on the address signal, and the bit lines not selected by the selector will be precharged again in the next precharge period. The problem is that it consumes unnecessary current.

The present invention has been made in view of the above-mentioned conventional circumstances, and therefore an object of the present invention is to provide a novel semiconductor integrated circuit capable of solving the above problems inherent in the conventional art. Especially.

[0014]

To achieve the above object, a ROM and SRAM circuit according to the present invention is a ROM and SRAM circuit in which a memory cell array is divided, and a plurality of memory cell arrays and each of these memory cell arrays are provided. An X decoder for exclusively selecting a word line for each memory cell array and a Y selector for selecting a bit line of the memory cell array are provided.

[0015]

By the X decoder exclusively selecting the word line for each memory cell array, when one memory cell array is operating, the other memory cell array is kept inactive (bit line is not discharged).

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will now be specifically described with reference to the drawings for each of its preferred embodiments.

FIG. 1 shows a first embodiment (ROM) according to the present invention.
It is a block diagram showing an example applied to a circuit.

As shown in FIG. 1, according to the first aspect of the present invention.
Of the PchMOS transistors 13 and 14 and N
A memory cell array 2 including chMOS transistors 15, 16, 17, 18 and word lines 103, 104 and bit lines 107, 108, a memory cell array 1 having the same configuration as the memory cell array 2, inverters 3, 4, and AN.
D circuits 5, 6, 7, 8 and selectors 9, 10 and latch 1
1 and 12, and is comprised. A0 and A1 are address signals, D0 and D1 are data signals, and φ is a clock signal.

Referring to FIG. 1, when the clock signal φ is at L level, it is a precharge period, and the AND circuit 5,
The word lines 101, 102, 10 which are the outputs of 6, 7, 8
3, 104 becomes L level, NchMOS transistors 15, 16, 17, 18 become "OFF", and Pc
Since the hMOS transistors 13 and 14 are turned on, the bit lines 107 and 108 have bit line capacitors 19 and 20.
Is precharged and becomes H level. Similarly, the bit lines 105 and 106 also become H level, and the latches 11 and 12
Does not open and retains previous data.

When the clock signal φ is at the H level during the sampling period, and the address signals A0 and A1 are at the L level and the H level, respectively, the inverter 3
The output of the AND circuit 5 becomes the H level and the output of the inverter 4 becomes the L level.
01, 102, and 103 remain L level, and only the word line 104 of the output of the AND circuit 8 becomes H level. Then, the NchMOS transistors 17 and 18 are "ON".
Therefore, the bit lines 107 and 108 have a bit line capacitance of 1
9 and 20 are discharged through the NchMOS transistors 17 and 18 and change to L level. At this time, the bit lines 105 and 106 hold the H level because the word lines 101 and 102 are at the L level.

When the address signal A1 is at the H level, the memory cell array 2 is selected, so that the selectors 9 and 10 select the bit lines 107 and 108, which are latches 11 ,.
It is transmitted to 12 and held, and becomes data D0 and D1. After this, when the clock signal φ enters the L-level precharge period again, the bit line 1 that was previously discharged is
07 and 108 are precharged through the Pch MOS transistors 13 and 14, and a charging current flows at this time, but since the bit lines 105 and 106 on the memory cell array 1 side have not been discharged, the current for precharging is Not flowing.

As described above, by selecting the memory cell array by the address signal A1 and not operating one of them, the current consumption can be halved.

FIG. 2 is a block diagram showing a second embodiment of the present invention (when the present invention is applied to an SRAM circuit).

As shown in FIG. 2, the second embodiment according to the present invention is a RAM cell 34 including NchMOS transistors 32 and 33 and inverters 30 and 31, and this RAM.
RAM cells 35, 36, 37 similar to cell 34, and Pc
Memory cell array 38 including hMOS transistors 39, 40, 41, 42 and word lines 203, 204
A memory cell array 47 having the same configuration as the memory cell array 38, inverters 52 and 53, AND circuits 48, 49, 50 and 51, selectors 54 and 55, and read / write buffers 56 and 57. Has been done.

Further, φ is a clock signal, A0 and A1 are address signals, D0 and D1 are data signals, RD is a RAM read signal WR, and a RAM write signal.

Referring to FIG. 2, first, when the clock signal φ is at L level, it is a precharge period, and the AND circuit 4
8, 49, 50, 51 output word lines 201, 20
2, 203, and 204 become L level, and the RAM cell 34
NchMOS transistors 32 and 33 in the
F ″, the RAM cells 35, 36, 37 operate in the same manner, and PchMOS transistors 39, 40, 41, 42
Bit line 209, 210, 21
1, 212 are PchMOS transistors 39, 40, 4
Bit line capacitors 43, 44, 45, 46 via 1, 42
Is precharged and becomes H level.

Similarly, the bit lines 205, 206, 207 and 208 on the memory cell array 47 side are also precharged to H level.
Become a level.

Next, it is assumed that the clock signal φ is at the H level during the sampling period, and for example, both the address signals A0 and A1 are at the H level. First of all, writing data will be described. The write signal WR becomes H level, and the read / write buffers 56 and 57 function as write buffers. The data signal D0 is input to the read / write buffer 56, from which true and bar data is transmitted to the selector 54.

Since the memory cell array 38 is selected when the address signal A1 is at the H level, the selector 54 outputs the signals of true and bar to the bit line pair 20.
9 and 210, one of the bit lines is discharged to the L level according to the value of the data signal D0, and the other holds the H level due to the bit line capacitance.

Similarly, the data signal D1 also passes through the read / write buffer 57 and the selector 55, and then passes through the bit line pair 211,2.
Discharge one of 12 and hold one.
At this time, since the outputs of the inverters 52 and 53 are both at the L level, the word lines 201, 202 and 204 which are the outputs of the AND circuits 48, 49 and 51 remain at the L level, and the word lines which are the output of the AND circuit 50. Only 203 becomes H level. Then, NchM in the RAM cell 34
The OS transistors 32 and 33 are turned on, the potential of the bit line pair 211 and 212 is transmitted to the inverters 30 and 31, and the data is held.

The RAM cell 35 operates in the same manner and holds data. At this time, the bit lines 205, 206, 207, and 208 on the memory cell array 47 side are not discharged and are held at the H level, so that the precharge current is not consumed in the next precharge period.

Next, the data reading in the sampling period will be explained using the same address signal as in the data writing.
At the level, the word lines 201, 202 and 204 are at the L level. Then, the NchMOS transistors 32 and 33 in the RAM cell 34 are turned on, and the inverters 30 and 3 are turned on.
The data held at 1 is transmitted to the bit line pair 211 and 212, one of the bit lines is discharged to the L level, and similarly, either of the bit line pair 209 and 210 changes to the L level. At this time, the bit lines 205, 206, 207, 208 on the memory cell array 47 side
Holds the H level because the word lines 201 and 202 are at the L level. From the potentials of these bit lines, the selectors 54 and 55 select the bit line pair 20 in the same manner as in writing.
9, 210 and bit line pairs 211, 212 are selected, and the potentials thereof are transmitted to the read / write buffers 56, 57.

At the time of reading, the signal RD becomes H level, the read / write buffers 56, 57 become read buffers, data is taken out from the potentials of true and bar transmitted from the selectors 56, 57 and held, and the data signals D0, D1 are output. . Even at this time, the memory cell array 4
Since the bit lines 205, 206, 207, and 208 on the 7 side hold the H level, the precharge current is not consumed in the next precharge period.

In this way, by selecting the memory cell array by the address signal A1 and not operating one of them, the SR
Even with AM, the current consumption can be halved.

[0035]

As described above, according to the present invention,
In the ROM and SRAM circuits in which the memory cell array is divided, by using a part of the address signal as a selection signal of the memory cell array, only the memory cell array necessary for sampling operates, and the other memory cell arrays keep the non-operation state, The effect that the memory cell array which is in the non-operating state at the time of precharging does not consume current is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment according to the present invention.

FIG. 2 is a block diagram showing a second embodiment according to the present invention.

FIG. 3 is a block diagram showing a conventional example.

FIG. 4 is an operation waveform diagram in a conventional example.

[Explanation of symbols]

1, 2, 38, 47, 70, 71 ... Memory cell array 3, 4, 30, 31, 52, 53, 72, 73 ... Inverter 5, 6, 7, 8, 48, 49, 50, 51, 74, 7
AND circuit 9, 10, 54, 55, 78, 79 ... Selector circuit 11, 12, 80, 81 ... Latch circuit 13, 14, 39, 40, 41, 42, 82, 83 ... P
chMOS transistors 15, 16, 17, 18, 32, 33, 84, 85, 8
6, 87 ... NchMOS transistors 19, 20, 43, 44, 45, 46, 88, 89 ... Bit line capacitances 34, 35, 36, 37 ... RAM cells 56, 57 ... Read / write buffers 101, 102, 103, 104, 201, 202, 2
03, 204, 301, 302, 303, 304 ... Word line 105, 106, 107, 108, 205, 206, 2
07, 208, 209, 210, 211, 212, 30
5, 306, 307, 308 ... Bit line φ ... Clock signal A0, A1 ... Address signal D0, D1 ... Data signal RD ... RAM read signal WR ... RAM write signal

Claims (2)

[Claims] 1. A read only memory comprising a plurality of memory cell arrays, a plurality of X decoders for selecting word lines of the memory cell arrays, and a plurality of Y selectors for selecting bit lines of the memory cell array. A semiconductor integrated circuit, which is a static random access memory, wherein the X decoder exclusively selects the memory cell array. 2. The semiconductor integrated circuit according to claim 1, wherein the X decoder uses a part of an address signal as a selection signal of the memory cell array.