JPS58133695A - Page size change system - Google Patents
Page size change systemInfo
- Publication number
- JPS58133695A JPS58133695A JP57013950A JP1395082A JPS58133695A JP S58133695 A JPS58133695 A JP S58133695A JP 57013950 A JP57013950 A JP 57013950A JP 1395082 A JP1395082 A JP 1395082A JP S58133695 A JPS58133695 A JP S58133695A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- page size
- circuit
- map
- given
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Memory System (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はマルチレベルアドレッシング７ｊＫ（二おける
マツピングの基本ＪＩＬ位（ページ）の大きさＶ動的６
１」可能としたページサイズを更方式に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention provides multi-level addressing 7jK (basic JIL mapping in two pages)
1" relates to a method for changing the page size that is possible.
１２＋従来技拘と藺一点
メモリ拳域Ｐ１ｔｌ＃定的εユページ区分し，処坤ｙｒ
ｈなう従来のべ一ジング万式では．ページサイズ（ペー
ジの大きさＪと実打されるジ曹プの大ささとの関連で使
用されない都会がメモリの参職中に散在し．メ％９の
使用効率が曇化するフラグメンテ−シーンが間組となる
。12 + Conventional technique and one point memory range P1tl
In the conventional basing Manshiki. Page size (Due to the page size J and the actual size of the map being used, unused cities are scattered throughout the memory process. Fragmentation scenes where the usage efficiency of Me%9 is clouded) becomes the interlude.
斯かるフラグメンテ−シーンン解決するため１二は．ペ
ージサイズを小さくシ．＃め細かＴＫメモリ管理を行な
えばよいが．この方法では反対に広いメモリ領域ン発す
る場合１：メモリ管理のオーバヘッドが増加するという
欠点がある。In order to solve such fragmentation scenes, 12. Reduce page size. # It would be nice if you could manage the TK memory in detail. On the other hand, this method has the disadvantage that when a large memory area is used, 1: memory management overhead increases.
又，従来よりページングは馬連で且つ大規模な計算機ν
ステムで用いられて来た技術であるが，近年のマイクロ
プロセッサの高性能化Ｃ二伴い，メモリ容量がｌｍバイ
ト以下の小規模システムに於いてもベージングの喪掌が
高まっている。In addition, paging has traditionally been done by horse operators and large-scale computers.
Although this technique has been used in systems, as the performance of microprocessors has improved in recent years, bazing has become increasingly popular even in small-scale systems with a memory capacity of 1m bytes or less.
しかし、前述の固定ページサイズによるぺ一シングでは
．上記フラグメンテーシ嘗ン．メモリ管瑯のオーバヘッ
ドの増加等の原因で小規模νステムへの４入が困難であ
る。However, with the pacing using the fixed page size mentioned above. Fragmentation example above. It is difficult to input four into a small-scale ν stem due to an increase in the overhead of the memory tube.
０１発明の１的
本＠一の１的は前述の欠点な改害し，ページサイズをシ
ステム運用中に於けるソフトウエアからの制御ｌ１１Ｃ
二より可変とすることにより適正なデータ処理ｖＷｌ能
とするページサイズ髪更方弐臀轡供することＣ二あ、る
。01 Part 1 of the invention @ Part 1 of the invention is to improve the above-mentioned disadvantages and to control the page size from software during system operation l11C
By making the page size more variable, proper data processing capability can be provided.
４１発明の構成 マルチレベルアドレプシング方式にＶいて。41 Composition of the invention It's based on the multi-level addressing method.
データメモダ（主記憶装置）に与えるアドレス蜘χ、マ
ツプメモ９を経由する場合と経由しない場合に選択し、
切替可能とする切替娶歓蟹具備することである。Select the address given to the data memo da (main memory), whether to go through map memo 9 or not,
It is equipped with a switching device that can be switched.
１ｆｉ１発明の実施例
以下１に示す木精−の実施＠Ｃ二ついて説明する。％ｌ
ｋは木精−の一実施一を示す一取１で、ページを指定す
るアドレスは１本のアドレス婦により４えられる。その
うち上位１本はマツプメモ５ｈｍｅ、下位ｊ−１本はデ
ータメモリＤｉｅ−二ｍ接４えられる６′１Ｉｈ１晧１
においてマツプメモ９ ＭＭの出力５本のうち１位１本
は胞路Ｐムン弁しデータメモ９Ｄνに与えられ上位ｊ−
１本は直接データメモ９ Ｄ−Ｍ ｇ−４えられる。１
修の７９ツブフロツプで形成されるマツプアドレス制限
レジスタ勧ムＤＲン設け、該細ムＤＲ（二遍当な制御デ
ータを設定することＣ二よって、Ｉ白路Ｐム中の対応位
置のスイッチ８Ｗヶ切替え、【１路アムを介する場合と
介さない場合と（二切替える。即ち、＠路Ｐムによって
データメモツＤＭｉ二与えられるアドレス線は。1fi1 Embodiments of the Invention Two examples of the implementation of the lumber shown in 1 will be described below. %l
k is 1, which indicates the number of times a wood spirit is used, and the address specifying a page is given by one address. Among them, the top one is map memo 5hme, and the bottom j-1 is data memory Die-2m connection 4 6'1Ih1 晧1
Out of the five outputs of map memo 9 MM, the first one is given to data memo 9 Dν for the cell path P mun valve and the top j-
One can be obtained directly from the data memo 9 D-M g-4. 1
A map address restriction register DR formed by a modified 79 block flop is provided, and the 8W switch at the corresponding position in the I white path P is provided. The address line given by the data memory DMi2 by the @path Pm is switched.
Φマツプメモツレ一によりｔ＊されたもの［株］を換さ
れないもの
のいずれか−ｙｊ（二選択されることとｒｘる。ΦMap Memories One of those that are t* [shares] and those that are not replaced -yj (two selected and rx).
そこで、ページサイズは、マツプメモシＭｌによ・−を
押されｔいアドレス１の本数ｙｎとした場合に、 １”
ワード（勤ｌ栖において９回路Ｐム円でに本のアドレス
鹸がよ記■Ｃ：遺択されている場合はｎ：に＋ Ｊ−１
）と１ｊる。Therefore, the page size is 1'' when the map memory Ml presses - and the number of addresses 1 is yn.
Word (at work, write the address of the book in 9 circuits Pm circle ■C: If it is selected, n: + J-1
) and 1jru.
′＃％２馳は１路アムとマツプアドレス制限レジスメ麺
ムＤＢの関連しついて具体例を示す回路１でｘＭマはイ
ンバータ、Ｂはｔライステート・パテフチを示す。弗Ｓ
−はｊ冨１の時回路アムがアドレス−の’Ｆ［４本をマ
ツプメモ９ＭＭ％ブｒ′：！−ないように選択されてい
る壷金のｌｌ５Ｉｒ！ｊ！Ｊの等＊［！！Ｉｐｍを不し
ている。この時ページサイズは％ａＩ＋１６ワードとな
り、またマツプアドレス制限レジスタームＤＲの設定は
ソフトウェアによ°リデータ処瑯を開始する前−二行な
う。'#%2 CH is a circuit 1 showing a specific example of the relationship between the 1-way am and the map address restriction regimen noodle DB.弗S
- is j when the circuit am is address -'F [Map 4 memo 9MM% BR':! - Il5Ir of urn gold selected as not! j! J etc. *[! ! Ipm is not working. At this time, the page size is %aI+16 words, and the map address restriction register DR is set by software -2 before starting redata processing.
曲１１ｉ？；明の効果
このようＣ二して本発明Ｃ二よ１１ばページサイズ馨簡
＠４二月つジ璽プのスささ砿ユ適合するようＣ：ｆすで
きるため、フラグメンテーシーンを少なくするようなメ
モリ管珍か可能となる。Song 11i? Effect of brightness In this way, the present invention C2 to C11 can be adjusted to fit the page size of the page size of the letter @4, reducing the number of fragmentation scenes. Such a memory tube becomes possible.
第ｌ−は本発明の一実施例の構成融、
ｂａｈは第１ ｔｋｒ中の回路Ｃユついての剖分評細し
１、
ｌＰＩ３１は具体例による轡価回路―を示す。
ＭＭ−・・マ雫プメモ９ ＤＭ・・・データメモシＰ
ム・・・１路 ａＷ−スイッチ細ムＤｌ・・
・マツプ了ドレス制限レジスタ特許出願人 １十通株式
会社
代 珊 人 弁趣土鈴木宋祐1-th shows the configuration of one embodiment of the present invention, bah shows the detailed analysis of the circuit C unit in the 1st tkr, and lPI31 shows the evaluation circuit according to a specific example. MM-...Map Memo 9 DM...Data Memo P
Mu...1 path aW-switch thin Dl...
・Matupure Dress Restriction Register Patent Applicant: 10th Co., Ltd. Representative: Sosuke Suzuki
Claims (1)
峠由する縁台と静由しない場合とＣ二辿択。 切替可能とする切Ｗ装重を具備することγ％徴とするペ
ージサイズ俟′斐方式。[Claims] In a multi-level addressing system. Data memo 91: Select the address WM to be given to the platform where the map memory is passed, the case where it is not passed, and the case where C is selected. The page size change method is characterized by having a cutting W weight that can be switched.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57013950A JPS58133695A (en) | 1982-01-30 | 1982-01-30 | Page size change system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57013950A JPS58133695A (en) | 1982-01-30 | 1982-01-30 | Page size change system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58133695A true JPS58133695A (en) | 1983-08-09 |
Family
ID=11847479
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57013950A Pending JPS58133695A (en) | 1982-01-30 | 1982-01-30 | Page size change system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58133695A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60144845A (en) * | 1983-12-30 | 1985-07-31 | Fujitsu Ltd | Ram address generating circuit |
| JPS61250752A (en) * | 1985-04-30 | 1986-11-07 | Fujitsu Ltd | Address expanding system |
| JPS61250753A (en) * | 1985-04-30 | 1986-11-07 | Fujitsu Ltd | Address expanding system |
| JPS63180154A (en) * | 1987-01-21 | 1988-07-25 | Nec Ic Microcomput Syst Ltd | Semiconductor memory of page address system |
-
1982
- 1982-01-30 JP JP57013950A patent/JPS58133695A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60144845A (en) * | 1983-12-30 | 1985-07-31 | Fujitsu Ltd | Ram address generating circuit |
| JPS61250752A (en) * | 1985-04-30 | 1986-11-07 | Fujitsu Ltd | Address expanding system |
| JPS61250753A (en) * | 1985-04-30 | 1986-11-07 | Fujitsu Ltd | Address expanding system |
| JPH0376504B2 (en) * | 1985-04-30 | 1991-12-05 | Fujitsu Ltd | |
| JPH0376503B2 (en) * | 1985-04-30 | 1991-12-05 | Fujitsu Ltd | |
| JPS63180154A (en) * | 1987-01-21 | 1988-07-25 | Nec Ic Microcomput Syst Ltd | Semiconductor memory of page address system |
| JPH058457B2 (en) * | 1987-01-21 | 1993-02-02 | Nippon Denki Aishii Maikon Shisutemu Kk |
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