KR950020144A - I / O processor for improving computer system performance - Google Patents

I / O processor for improving computer system performance Download PDF

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Publication number
KR950020144A
KR950020144A KR1019930027858A KR930027858A KR950020144A KR 950020144 A KR950020144 A KR 950020144A KR 1019930027858 A KR1019930027858 A KR 1019930027858A KR 930027858 A KR930027858 A KR 930027858A KR 950020144 A KR950020144 A KR 950020144A
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KR
South Korea
Prior art keywords
scsi
input
buffer memory
computer system
data
Prior art date
Application number
KR1019930027858A
Other languages
Korean (ko)
Other versions
KR960003650B1 (en
Inventor
이상민
김중배
김성국
한순섭
안희일
Original Assignee
양승택
재단법인 한국전자통신연구소
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 양승택, 재단법인 한국전자통신연구소 filed Critical 양승택
Priority to KR1019930027858A priority Critical patent/KR960003650B1/en
Publication of KR950020144A publication Critical patent/KR950020144A/en
Application granted granted Critical
Publication of KR960003650B1 publication Critical patent/KR960003650B1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1657—Access to multiple memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0036—Small computer system interface [SCSI]

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

본 발명은 컴퓨터 시스템의 성능향상을 위한 입출력 프로세서에 관한 것으로, 입출력 프로세서 내의 버퍼 메모리를 분리하여 다중의 SCSI 버스가 상기 버퍼 메모리를 공유하도록 하고, DMAC와 프로에서의 독립적인 동작을 위한 어드레스 및 데이타 패스를 구성한 입출력 프로세서에 관한 것이다. 이에 본 발명은 다중의 SCSI버스를 제어하는 복수개의 SCSI 제어기와, 하위어드레스 영역으로 SCSI#1과 SCSI#2가 공유하는 제1뱅크와 상위 어드레스 영역으로 SCSI#3과 SCSI#4가 공유하는 제2뱅크로 나누는 2개의 데이타 버퍼메모리와, 상기 데이타 버퍼메모리 뱅크를 제어하는 버퍼메모리 제어기로 구성된다. 상기한 구성요소에 의해 본 발명은 다중의 SCSI버스간의 충돌을 줄이는 작용을 한다.The present invention relates to an input / output processor for improving the performance of a computer system, and separates the buffer memory in the input / output processor so that multiple SCSI buses share the buffer memory, and addresses and data for independent operation in DMAC and PRO. The present invention relates to an input / output processor configured with a path. Accordingly, the present invention provides a plurality of SCSI controllers for controlling multiple SCSI buses, a first bank shared by SCSI # 1 and SCSI # 2 as a lower address area, and a SCSI # 3 and SCSI # 4 shared as upper address areas. Two data buffer memories divided into two banks, and a buffer memory controller for controlling the data buffer memory banks. With the above components, the present invention serves to reduce the collision between multiple SCSI buses.

Description

컴퓨터 시스템의 성능향상을 위한 입출력 프로세서I / O processor for improving computer system performance

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 따른 입출력 프로세서의 블럭도.1 is a block diagram of an input / output processor according to the present invention.

Claims (1)

중앙처리장치(1)와, 데이타를 저장하는 메모리와, 주변장치와 상기 메모리 사이의 데이타 전송을 위한 통로를 제공하는 입출력 프로세서와, 데이타의 입출력 전송이 상기 메모리 장치와 주변장치 사이에서 직접 이루어지는 인터페이트인 DMAC(2)로 구성되고 다중 SCSI버스를 사용하는 컴퓨터 시스템에 있어서, 상기 다중 SCSI버스를 제어하는 복수개의 SCSI제어기(5~8)와, 하위어드레스 영역으로 SCSI#1과 SCSI#2가 공유하는 제1뱅크와 상위 어드레스 영역으로 SCSI#3과 SCSI#4가 공유하는 제2뱅크로 나누는 2개의 데이타 버퍼메모리(4,4′)와, 상기 데이타 버퍼메모리(4,4′) 뱅크를 제어하는 버퍼 메모리 제어기(3,3′)로 구성된 컴퓨터 시스템의 성능 향상을 위한 입출력 프로세서.A central processing unit (1), a memory for storing data, an input / output processor for providing a passage for transferring data between the peripheral device and the memory, and an input / output transfer of data directly between the memory device and the peripheral device. In a computer system composed of DMAC (2), which is a paint, and using multiple SCSI buses, a plurality of SCSI controllers (5 to 8) for controlling the multiple SCSI buses, and SCSI # 1 and SCSI # 2 as lower address areas, Two data buffer memories (4,4 ') divided into a second bank shared by SCSI # 3 and SCSI # 4 as a shared first bank and an upper address area, and a bank of the data buffer memory (4,4'). Input / output processor for performance improvement of computer system composed of controlling buffer memory controller (3,3 ′). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930027858A 1993-12-15 1993-12-15 Input/output processor for improving computer system performance KR960003650B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930027858A KR960003650B1 (en) 1993-12-15 1993-12-15 Input/output processor for improving computer system performance

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930027858A KR960003650B1 (en) 1993-12-15 1993-12-15 Input/output processor for improving computer system performance

Publications (2)

Publication Number Publication Date
KR950020144A true KR950020144A (en) 1995-07-24
KR960003650B1 KR960003650B1 (en) 1996-03-21

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930027858A KR960003650B1 (en) 1993-12-15 1993-12-15 Input/output processor for improving computer system performance

Country Status (1)

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KR960003650B1 (en) 1996-03-21

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