JPH05289934A - Image memory device - Google Patents

Abstract

PURPOSE:To prevent writing or reading from being jumped in the display period of an image and to prevent a display from being disturbed by preparing a memory for two pictures and controlling writing and reading timing. CONSTITUTION:Writing operation is executed by specifying a vertical address (row address) and a horizontal address (column address) in a RAM 2 after outputting a write enable signal to the RAM 2, and setting up data in an I/O part. Reading operation outputs data from the I/O part by outputting a read enable signal to a SAM part 3, transferring data for one horizontal operation period to be read out from the RAM 2 to the SAM 3 and then sending serial clocks to the SAM 3. The image memory is managed in each field, and if the dangerousness of collision between reading and writing accesses is generated, the accesses are allowed to escape to idle fields, so that an image can be prevented from being disturbed due to the collosion of accesses.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image memory device, and more particularly to an image memory device which prevents an image from being disturbed when an image is taken in and displayed asynchronously.

[0002]

2. Description of the Related Art As a method of capturing and displaying an image via a memory, there are a synchronous method for completely matching the capturing and display of image data and an asynchronous method for not necessarily matching.

In the former case, the access to the write memory and the read memory can be completely separated in the field, so that the operation can be performed without any problem. In the latter case, the read and the write memory access cannot be completely separated from each other. In some cases, reading may overtake writing in the memory, and thus a time difference of one vertical scanning period may occur at the top and bottom of the screen.

[0004]

However, for example, in the case of the synchronous type, when either the writing or reading timing is deviated, the influence of the deviation also affects the other, which causes the inconvenience. .. Also, because the same sync signal must be used in all systems,
Since it can only be used in a closed system and has no potential for development, it was not found on many devices.

Further, in the case of the asynchronous type, since writing and reading are independently controlled, there is a disadvantage that reading overtakes writing during display or reading overtakes writing. As a result, a vertical scanning period shift occurs at the top and bottom of the screen, but in actuality there is almost no difference between the read and write timings, so overtaking rarely occurs. It wasn't a big problem because it wasn't known if the period was too late. However, if you try to perform image processing such as flipping the captured image upside down by this method, the image capture is accessed from the upper vertical address of the memory, and the read is accessed from the lower vertical address of the memory. There is an inconvenience that the access collides near the center of the directional address and a shift for one vertical scanning period is always generated near the center of the screen, so that a correct vertically inverted image is not displayed.

According to the present invention, a memory for two screens is provided, and by controlling the timing of writing and reading of them, the passing of writing or reading is eliminated during the display period of the image so that the display is not disturbed. This is a mechanism for doing so.

[0007]

SUMMARY OF THE INVENTION The present invention has been invented focusing on the above-mentioned problems of the prior art, and includes a first accumulator capable of randomly accessing data, and the accumulator. Receive data for one horizontal period in sequence and take 1
An image memory having a second storage unit for serially outputting the data for the horizontal period is provided for four fields, and the horizontal and vertical addresses of the first storage unit are designated for the input image data. Image data from the image memory by writing means for writing image data to the storage section of the image memory, and by transferring the image data from the first storage section to the second storage section and outputting the image data serially from the second storage section. Reading means, field address management means for managing independent field addresses on the image data writing side and reading side in the image memory for four fields, and means for counting field addresses on the image data writing side and reading side. And comparing means for comparing the field addresses of the writing side and the reading side of the image data, and the comparing means. Means for adding a predetermined number of addresses to the field address in accordance with the comparison result, and means for producing a data write permission signal from the writing side field address of the image memory and a data reading permission signal from the reading side field address. And an image memory device having:

The present invention further comprises means for giving initial values of horizontal and vertical addresses of image data, and means for controlling counting of horizontal and vertical addresses of image data,
An image memory device further comprising means for counting down the horizontal and vertical addresses of image data, respectively.

[0009]

The writing is performed by giving the vertical address, the horizontal address and the image data to the RAM portion of the image memory. Reading is performed by transferring data for one line from the RAM section of the image memory to the SAM section and requesting output from the SAM.

This image memory is managed on a field-by-field basis, and if read and write accesses are about to collide with each other, the access to the vacant field is escaped to prevent the image from being disturbed due to the collision of access.

Also, if the horizontal address count direction is reversed, a horizontally inverted image is obtained, and if the vertical address count direction is reversed, a vertically inverted image is obtained.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings. 1 is a block electric circuit diagram showing an embodiment of an image memory device according to the present invention, FIG. 2 is a block diagram of an image memory used in the present invention, and FIG. 3 is a write enable signal generator and a read enable signal generator. FIG. 4 is a flowchart showing a series of operations of the write enable signal generator, FIG. 5 is a flowchart showing a series of operations of the read enable signal generator, and FIG. 6 is a block diagram of a horizontal address generator. FIG. 7 is a flow chart showing a series of operations of the horizontal address generator, FIG. 8 is a block diagram of a vertical direction address generator, FIG. 9 is a flow chart showing a series of operations of the vertical address generator, and FIG. 10 is a transfer address. FIG. 11 is a block diagram of the generator, and FIG. 11 is a flowchart showing a series of operations of the transfer address generator.

1, FIG. 2, FIG. 3, FIG. 6, FIG. 8, and FIG. 10, 1 is an image memory, and 2 is an image memory RAM.
3, 3 is an image memory SAM unit, 4 is an A / D converter for converting an image signal into a digital signal which can be written in the memory, 6 to 9 are field banks, and 10 is a horizontal address generator for giving the memory in the field bank. , 11 is a vertical address generator, 12 is a transfer address generator, 13 is an address switcher for switching each address to send to the memory, 14 is a write enable signal generator for controlling writing in field units, and 15 is a field A read enable signal generator for controlling reading in units, 16 is a field address counter, 17 is a field address decoder, 18 is a field address comparator, 19 is an initial value setting unit for setting an initial value in the counter, 20 Inputs the clock to the counter Clock input, 21 counts up or down count Choices up-down counter 22 is up-counted dedicated counter.

In FIG. 2, the image memory 1 uses a dynamic RAM generally called a multiport memory. This is 256Kbit x 256Kbit x 8
RAM2 of bit and SA of 256Kbit x 8bit
It is composed of M3 and R
Arrange to perform the read operation on AM2 only on SAM3. The write operation is performed by issuing a write enable signal to the RAM 2 and then designating a vertical address (RAW address) and a horizontal address (Column address) of the RAM 2 and setting data in the I / O.

In the read operation, after issuing a read enable signal to the SAM3, the data for one horizontal operation period to be read is transferred from the RAM2 to the SAM3, and the serial clock is sent to the SAM3 to send from the I / O. Is output. When writing data to RAM2, the horizontal address is 0 → 255 and the vertical address is 0 → 2
A normal image can be obtained by counting up to 55.

When the horizontal address is counted down from 255 to 0, a horizontally inverted image is obtained, and when the vertical address is counted from 255 to 0, a vertically inverted image is obtained. At this time, it is assumed that the image memory 1 has separate banks for the image data Y, BY and RY, and one bank Y will be described below.

In the bank Y, the memory 1 has four fields, that is, two screens, as shown in FIG. A number from 0 to 3 is given to each field. These numbers are binary numbers (00), (01),
It corresponds to (10) and (11) and is managed as a field address. The same data and address (row address, column address, transfer address) are all applied to the field banks, and a write enable signal (Write Enable) is applied.
ble) and a read enable signal (Serial Output)
t Enable) controls writing and reading. The row address, column address, and transfer address are
The signals are output from the vertical address generator 11, the horizontal address generator 10, and the transfer address generator 12, respectively, switched by the address switching unit 13 at the timing specified by the memory used, and output to the memory.

As shown in FIG. 6, the horizontal address generator 10 comprises an initial value setting section 19, a clock input section 20, and an up / down counter 21. Hereinafter, description will be made according to the flowchart shown in FIG. When the writing side enters the horizontal blanking period (# 13), step #
At 18, the initial value setting unit 19 sets 0 (# 19) when the horizontal inversion signal is OFF, and sets 255 (# 20) when ON.
It is set as the initial value of the up / down counter 21. After the horizontal blanking period ends, step # 1
At 4, the up-down counter follows the horizontal inversion signal and counts up one horizontal address when the horizontal inversion signal is OFF (# 15), and counts down one horizontal address when it is ON (# 16). Then, the result is output to the address switch 13 (# 17).

On the other hand, the vertical address generator 11 is shown in FIG.
As shown in, the initial value setting unit 19 and the clock input unit 2
0, up / down counter 21. Hereinafter, description will be given according to the flowchart shown in FIG.

When the writing side enters the vertical blanking period (# 21), the initial value setting section 19 sets 0 (# 28) when the vertical inversion signal is OFF and 255 (# 29) when it is ON in step # 27. It is set as the initial value of the up / down counter 21. When the vertical blanking period ends, in step # 22, the clock input unit 20 determines whether it is the horizontal blanking period, and if it is the horizontal blanking period, outputs one clock to the up / down counter.

At this time, the up-down counter follows the vertical inversion signal (# 23), and when the vertical inversion signal is OFF, increments the vertical address by one (# 24),
When it is ON, the vertical address is counted down by one (# 25). Then, the result is output to the address switch 13 (# 26).

As shown in FIG. 10, the transfer address generator 12 is composed of a clock input section 20 and an up-counting dedicated counter 22. Hereinafter, description will be made according to the flowchart shown in FIG. When the reading side enters the vertical blanking period, the counter detects the vertical blanking signal as a transfer address reset signal (# 30) and turns it on.
If it is (# 34), the transfer address is set to 0. When the vertical blanking period on the reading side ends, the clock input unit 20 determines whether the reading side is on the horizontal blanking period, and if it is the horizontal blanking period, detects the horizontal blanking signal as a data transfer request signal (# 3
1), 1 clock is output to the counter, and the counter increments the transfer address by 1 (# 32). Then, the result is output to the address switch 13 (# 3
3).

The write enable signal generator 14 and the read enable signal generator 15 are, as shown in FIG. 3, composed of a 2-bit counter 16 of the previous field address and its decoder 17,
And an address comparator 1 that compares addresses
It is composed of 8.

The block configurations of the write enable signal generator 14 and the read enable signal generator 15 are exactly the same. When the count-up permission signal for the write (or read) field address is input, the field address counter 16 is incremented by 1 and the result is sent to the field address decoder. At this time, it is compared with the read field address (or write field address), and if they are the same, 2 is further added and the field address is sent to the decoder.

Since it is a 2-bit counter in the actual circuit diagram, it can be realized by inverting the output of the second bit. This series of operations will be described below with reference to the flowcharts shown in FIGS.

On the writing side, the counter is incremented by 1 (# 1) after writing for one vertical scanning period (# 2), and then compared with the field address on the reading side (#
3). If the write field address and the read field address are different, the write field address is output to the decoder as it is (# 5), and the result is output to each field as a write enable signal (# 6).

If the write field address and the read field address are the same, 2 is further added to the write field address (# 4), and the result of decoding is output as a write enable signal (#
6). The reason for adding 2 is to prevent the odd field and the even field from being reversed and to hold the interlace.

On the reading side, the counter is 1 in the same manner.
After reading the vertical scanning period (1) is added (# 7) (#
8) After that, it is compared with the field address on the writing side (# 9).

If the read field address and the write field address are different, the read field address is directly output to the decoder (# 1
1), the result is output to each field as a read enable signal (# 12).

If the read field address and the write field address are the same, 2 is further added to the read field address (# 10) and the result of decoding is output as a read enable signal (# 12). ). As a result, it is possible to prevent collision of accesses on the writing side and the reading side, and it is possible to eliminate the disturbance of the image being displayed.

[0031]

Since the present invention is configured as described above, when writing and reading are performed asynchronously when image processing is performed using the image memory, writing and reading do not pass each other. Therefore, it is possible to continuously transfer the image data to the image memory without disturbing the display of the image. Further, it is possible to provide an excellent image memory device capable of horizontally inverting and vertically inverting an image without disturbing the display of the image.

[Brief description of drawings]

FIG. 1 is a block-like electric circuit diagram showing an embodiment of an image memory device according to the present invention.

FIG. 2 is a diagram showing a configuration of an image memory applied to the present invention.

FIG. 3 is a block electric circuit diagram showing a write (read) permission signal generator.

FIG. 4 is a flowchart showing a series of operations of a write enable signal generator.

FIG. 5 is a flowchart showing a series of operations of the read enable signal generator.

FIG. 6 is a block electric circuit diagram of a horizontal address generator.

FIG. 7 is a flowchart showing a series of operations of the horizontal address generator.

FIG. 8 is a block electric circuit diagram of a vertical address generator.

FIG. 9 is a flowchart showing a series of operations of the vertical address generator.

FIG. 10 is a block electric circuit diagram of a transfer address generator.

FIG. 11 is a flowchart showing a series of operations of the transfer address generator.

[Explanation of symbols]

 1 Image Memory 2 RAM Section 3 SAM Section 11 Column Address Generator 12 Transfer Address Generator 13 Address Switcher 14 Write Enable Signal Generator 15 Read Enable Signal Generator 16 Field Address Counter 19 Initial Value Setting Section 21 Up / Down Counter

Claims (2)

[Claims] 1. In a system for temporarily storing image data in an image memory and performing image processing, a first storage unit capable of randomly accessing the data and data for one horizontal period sequentially from the first storage unit. In response to this, an image memory having a second storage unit for serially outputting data for one horizontal period is provided for four fields, and the input image data has horizontal and vertical directions of the first storage unit. Writing means for designating an address and writing image data in the first storage unit, and transferring the image data from the first storage unit to the second storage unit and serially transmitting the image data from the second storage unit. A means for reading out the image data from the image memory by outputting, and an independent file on the writing side and the reading side of the image data in the image memory for four fields. Field address management means for managing the field address, means for counting the field addresses on the writing side and the reading side of the image data, comparing means for comparing the field addresses on the writing side and the reading side of the image data, and the comparing means. Adder means for adding a predetermined number of addresses to the field address according to the comparison result, and means for producing a data write enable signal from the write side field address of the image memory and a data read enable signal from the read side field address. An image memory device comprising: 2. A means for providing an initial value of a horizontal address of image data, a means for controlling a count of a horizontal address of image data, and a horizontal address of image data according to claim 1. A means for counting down, a means for giving an initial value of the vertical address of the image data, a means for controlling the count of the vertical address of the image data, and a means for counting down the vertical address of the image data. Image memory device.