JP3343207B2 - Memory interface device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a memory interface device for writing and reading digital signals to and from a single port memory.

[0002]

2. Description of the Related Art In recent years, digital processing of signals has become widespread in the audio signal processing and video signal processing fields. The use of multimedia as a signal source has demanded higher processing contents for digital signals. At that time, processing using a memory is regarded as important. For example, video signals include NTSC, PAL, HDTV, VG
There are various types such as A, SVGA, and the like, and display devices are also diversified such as CRT, liquid crystal, and plasma display. A digital signal processing system using a memory is indispensable for converting the format of such various kinds of video signals and for synthesizing and outputting a plurality of asynchronous video signals. These processes require a high-speed real-time operation for writing and reading video signals without interruption.

Conventionally, processing for reading and writing video signals to and from a memory in real time has been realized by using a dual port memory such as a FIFO. Alternatively, real-time processing has been realized by alternately controlling writing and reading of two single-port memories. Also, when converting video formats and handling a plurality of asynchronous signals, each operation has been realized by designing a dedicated memory control device.

[0004]

However, in the above configuration, at least two single-port memories or one dual-port memory are required for real-time processing of a video signal, and the entire system is expensive. There was a problem of becoming. Furthermore, even if the memory is used, there is a problem that a bit width and a clock frequency of a video signal that can be handled are limited, and a flexible system cannot be realized.

An object of the present invention is to provide a memory interface device capable of realizing a video signal in real time using a single single port memory.

Another object of the present invention is to provide a system which can realize real-time processing of a video signal using a single single-port memory and which does not depend on the number of bits of input / output signals and the bus width of the single-port memory. Is to provide a memory interface device that can realize the above.

Another object of the present invention is to provide a memory interface device capable of realizing video signal real-time processing using a single single-port memory and enabling a plurality of asynchronous video signal processing. It is in.

[0008]

A memory interface device according to the present invention comprises an input buffer having a plurality of input areas, an output buffer having a plurality of output areas, the input buffer, the output buffer and a predetermined single port memory. And a control unit that controls the control unit, wherein the control unit transmits the signal stored in a specific input area of the plurality of input areas of the input buffer to the single port memory while transferring the specific The input buffer and the single-port memory are controlled to store an input signal in an input area other than an input area, and the control unit is configured to store the input signal in a specific output area of the plurality of output areas of the output buffer. While the output signal is output as an output signal, the signal stored in the single port memory is output to an output area other than the specific output area. Controlling said output buffer and the single port memory to forward. Thereby, the above object is achieved.

The memory interface device converts an output bus width of the input buffer into an input bus width of the single port memory, and converts an output bus width of the single port memory into an input bus width of the output buffer. A bus width conversion circuit may be further provided.

The input buffer is divided into a plurality of input areas corresponding to the bit direction and the word direction of the input buffer, and the output buffer corresponds to the bit direction and the word direction of the output buffer. May be divided into a plurality of output areas.

Each of the input buffer and the output buffer outputs an access request signal to the single port memory to the control unit, and the control unit assigns a priority to the access request signal according to a predetermined standard. May be provided.

[0012] The memory interface device may further include a circuit for directly writing a signal output from the input buffer to the output buffer.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. 1 shows a configuration of a memory interface device of the present invention. As shown in FIG. 1, the memory interface device includes an input buffer unit 1, an output buffer unit 2, a control unit 3 for controlling the input buffer unit 1, the output buffer unit 2, and the single port memory 6.
And

The control section 3 outputs an input buffer control signal to the input buffer section 1 in response to the synchronization signal, and outputs an output buffer control signal to the output buffer section 2 in response to the synchronization signal. Further, the control unit 3 receives an access request signal for the single port memory 6 from the input buffer unit 1 and the output buffer unit 2, and outputs an address and a control signal to the single port memory 6 in response to the access request signal.

In the present embodiment, it is assumed that the signal input to the memory interface device is a video signal, and that the video signal includes a luminance signal Y and a color difference signal C.

The input buffer unit 1 has an input buffer 1a for a luminance signal Y and an input buffer 1b for a chrominance signal C. The output buffer unit 2 has an output buffer 2a for a luminance signal Y and a chrominance signal. C output buffer 2b. The luminance signal Y is stored in the single port memory 6 via the input buffer 1a, and the signal read from the single port memory 6 is output via the output buffer 2a. The color difference signal C is stored in the single port memory 6 via the input buffer 1b, and the signal read from the single port memory 6 is output via the output buffer 2b. However, it is not the essence of the present invention that the input buffer unit 1 and the output buffer unit 2 are divided according to the use of the input signal. The case where the input buffer unit 1 includes a single input buffer or the case where the output buffer unit 2 includes a single output buffer is also included in the scope of the present invention.

FIG. 2 shows the configuration of the input buffer 1a.
The input buffer 1b has the same configuration as the input buffer 1a.

In FIG. 2, black circles 7 and white circles 8 indicate memory cells which are 1-bit storage units of the input buffer 1a. A black circle 7 indicates a state where 1-bit data is stored in the memory cell, and a white circle 8 indicates an empty state where no data is stored in the memory cell. The bit width of the input signal (luminance signal Y) input to the input buffer 1a is n bits, and the size of the input buffer 1a is m × n bits.
Here, n is any positive integer, and m is any positive integer 2
It is twice.

The input signal is first stored in the memory cell in the 0th column of the input buffer 1a. FIG. 2 shows a state where the input signal is stored in the memory cells of the 0th column to the 2nd column.

The input buffer 1a is logically divided into a region I ₁ and region I _2. Region I ₁ includes a memory cell from the 0th column to the (m-2) / 2 column. Area I
₂ includes memory cells from the (m / 2) th column to the (m-1) th column. Writing data from the input buffer 1a to a single port memory 6 (transfer) occurs when the data are stored in all of one of the memory cell area I ₁ or region I _2.

FIG. 3 shows the timing at which the input signal is temporarily stored in the input buffer 1a and then written into the single port memory 6. Input signal is input buffer 1b
The same applies to the timing at which the data is temporarily stored in the single port memory 6 and then written to the single port memory 6.

In the example shown in FIG. 3, a horizontal synchronizing signal is used as a reference signal. Of course, a signal other than the horizontal synchronization signal may be used as the reference signal.

The input buffer enable signal is a signal indicating whether writing to the input buffer 1a is permitted. In the example shown in FIG. 3, the H level of the input buffer enable signal indicates an enabled state, and the L level of the input buffer enable signal indicates a disabled state. The control unit 3 outputs an input buffer enable signal to the input buffer 1a in response to the horizontal synchronization signal. The input buffer enable signal is a type of the input buffer control signal.

A write request to the single port memory 6 occurs when data is stored in all of the memory cells in either the region I ₁ or the region I ₂ . Therefore,
When the input buffer enable signal is at the H level, the write request to the single port memory 6 is m / 2
Occurs every cycle.

[0025] In response to a write request to the first single-port memory 6, the data stored in the area I ₁ of the input buffer 1a is transferred to the single port memory 6, are written to it. While the data stored in the region I ₁ of the input buffer 1a is transferred to the single port memory 6, the input signal is accumulated in region I ₂ of the input buffer 1a.

[0026] As a response to the next write request to the single port memory 6, data stored in the area I ₂ of the input buffer 1a is transferred to the single port memory 6,
Written there. While the data stored in the area I ₂ of the input buffer 1a is transferred to the single port memory 6, the input signal is accumulated in the region I ₁ of the input buffer 1a. Thereafter, the same processing is repeated.

As described above, by dividing the input buffer 1a into two areas, while transferring the data stored in one area to the single port memory 6, the input signal is stored in the other area. be able to. As a result, without stopping the accumulation of the input signal in the input buffer 1a, the single-port memory 6
Can transfer the data.

Although the input buffer 1a is divided into two areas in FIG. 2, the number of divided areas is not limited to two. The input buffer 1a may be divided into L areas. Here, L is a natural number of 2 or more. The number of bits of the input signal may be any number as long as the relationship of row address size of input buffer 1a ≧ number of bits of input signal is satisfied. The same applies to the input buffer 1b.

FIG. 4 shows the configuration of the output buffer 2a.
The output buffer 2b has the same configuration as the input buffer 2a.

In FIG. 4, black circles 7 and white circles 8 indicate memory cells as 1-bit storage units of the output buffer 2a. A black circle 7 indicates a state where 1-bit data is stored in the memory cell, and a white circle 8 indicates an empty state where no data is stored in the memory cell. The bit width of the output signal (luminance signal Y) output from the output buffer 2a is n bits, and the size of the output buffer 2a is m × n bits.
Here, n and m are arbitrary positive integers.

The output signal is first output from the memory cell in the 0th column of the output buffer 2a. FIG. 4 shows a state where the data stored in the memory cells in the 0th column to the second column is output.

The output buffer 2a is logically divided into a region O ₁ and area O _2. The region O ₁ includes memory cells from the 0th column to the (m−2) / 2th column. Area O
₂ includes memory cells from the (m / 2) th column to the (m-1) th column. Reading of data from the single port memory 6 to the output buffer 2a (transfer) occurs when all of the one of the memory cell area O ₁ or area O ₂ is empty.

FIG. 5 shows the timing at which the data read from the single port memory 6 is temporarily stored in the output buffer 2a and then output outside the memory interface device. The same applies to the timing at which the data read from the single port memory 6 is temporarily stored in the output buffer 2b and then output to the outside of the memory interface device.

In the example shown in FIG. 5, a horizontal synchronizing signal is used as a reference signal. Of course, a signal other than the horizontal synchronization signal may be used as the reference signal.

The output buffer enable signal is a signal indicating whether or not reading from the output buffer 2a is permitted. In the example shown in FIG. 5, the H level of the output buffer enable signal indicates an enabled state, and the L level of the output buffer enable signal indicates a disabled state. The control unit 3 outputs an output buffer enable signal to the output buffer 2a in response to the horizontal synchronization signal. The output buffer enable signal is one type of an output buffer control signal.

A read request to the single port memory 6 occurs when all of the memory cells in either the region O ₁ or the region O ₂ become empty. Therefore, when the output buffer enable signal is at the H level, a read request to the single port memory 6 occurs every m / 2 cycles.

It is assumed that the output buffer 2a is empty when the horizontal synchronizing signal goes high. In this case, in response to a read request to the first single-port memory 6, the data read out from the single port memory 6 is transferred to the area O ₁ of the output buffer 2a, and written therein.

In response to the output buffer enable signal changing from L level to H level, output buffer 2
The output of the data stored in the area O ₁ of a is started.
While the data stored in the area O ₁ of the output buffer 2 a is being output, the data read from the single port memory 6 is output in response to the next read request to the single port memory 6. is transferred to the area O _2, it is written therein. Thereafter, the same processing is repeated.

As described above, by dividing the output buffer 2a into two areas, while the data accumulated in one area is output as an output signal, the data is read out from the single port memory 6 to the other area. The transferred data can be transferred. Thus, data can be transferred from the single port memory 6 to the output buffer 2a without stopping the output from the output buffer 2a.

Although the output buffer 2a is divided into two areas in FIG. 4, the number of divided areas is not limited to two. The output buffer 2a may be divided into N areas. Here, N is a natural number of 2 or more. The number of bits of the output signal may be any number as long as the relationship of row address size of output buffer 2a ≧ number of bits of output signal is satisfied. The same applies to the output buffer 2b.

The control unit 3 includes an input buffer 1a,
1b receives a write request to the single port memory 6 from the input buffer 1b in response to the write request.
By reading data from a and 1b and outputting an address and a control signal to the single port memory 6, write control for writing data to the single port memory 6 and a read request from the output buffers 2a and 2b to the single port memory 6 can be performed. The data is read from the single-port memory 6 by outputting the address and the control signal to the single-port memory 6 in response to the read request, and the data read from the single-port memory 6 is output to the output buffers 2a and 2b. Read control for storage is performed.

FIG. 6 shows a process of writing a video signal to the single port memory 6 while storing the video signal in the input buffers 1a and 1b and reading data from the single port memory 6 by using the memory interface device having the configuration shown in FIG. The timing when the process of outputting the video signal while storing the read data in the output buffers 2a and 2b is performed in parallel is shown.

In the example shown in FIG. 6, a horizontal synchronizing signal is used as a reference signal. Of course, a signal other than the horizontal synchronization signal may be used as the reference signal.

When the horizontal synchronizing signal goes high, it is assumed that the output buffers 2a and 2b are empty. In this case, a read request (a luminance signal Y read request, a color difference signal C read request) to the first single port memory 6 is sent to the control unit 3. In response to these read requests, the control unit 3 reads data from the single port memory 6 in the order of the luminance signal Y and the color difference signal C, and transfers the luminance signal Y read from the single port memory 6 to the area O _{1 of the} output buffer 2a. transferred to write therein, and transfers the color difference signal C read from the single port memory 6 to the area O ₁ of the output buffer 2b written therein.

The input buffer enable signal and the output buffer enable signal simultaneously change from L level to H level.

In response to the change of the input buffer enable signal from L level to H level, input buffer 1
a, the input of the input signal to the region I ₁ of 1b is started.

In response to the output buffer enable signal changing from L level to H level, output buffer 2
a, the output of the data stored in the area O ₁ and 2b is started.

Next, a read request to the single port memory 6 (a request to read the luminance signal Y and a request to read the color difference signal C) is sent to the control section 3. In response to these read requests, the control unit 3 reads data from the single port memory 6 in the order of the luminance signal Y and the color difference signal C, and transfers the luminance signal Y read from the single port memory 6 to the area O _{2 of the} output buffer 2a. transferred to write therein, and transfers the color difference signal C read from the single port memory 6 to the area O ₂ of the output buffer 2b written therein.

Further, after m / 2 cycles of a read request (a luminance signal Y read request and a color difference signal C read request) to the single port memory 6, a write request (a luminance signal Y write request, a color difference A signal C write request) and a read request to the single port memory 6 (a luminance signal Y read request, a color difference signal C read request) occur simultaneously.

The control unit 3 responds to the write request and the read request by responding to the area I _{1 of the} input buffer 1a.
Signal Y and the area I _{1 of the} input buffer 1b.
Are transferred to the single port memory 6 in the order of the luminance signal Y and the color difference signal C, and are written therein.
Thereafter, read data from the single port memory 6 luminance signal Y, the order of the color difference signal C, the writing thereto transfers the luminance signal Y read from the single port memory 6 to the area O ₁ of the output buffer 2a, the single port memory 6
The color difference signal C read out from the area O of the output buffer 2b.
Transfer to ₁ and write there. Such writing to the single port memory 6 and reading from the single port memory 6 are executed within one m / 2 cycle.

While the signal stored in the area I ₁ of the input buffers 1 a and 1 b is being transferred to the single port memory 6, the input signal is stored in the area I ₂ of the input buffers 1 a and 1 b. Output buffer 2a, while the data accumulated in the area of O ₂ 2b are output, the data output buffer 2a read from the single port memory 6, 2
It is transferred to the b region O ₁ of the. Thereafter, the same processing is repeated.

FIG. 7 shows an example of a memory map of the single port memory 6. The address 0 to n1-1 of the single port memory 6 is a luminance signal Y1 of the first field, and the addresses n1 to n2-1 are a color difference signal C of the first field.
1 is stored. Similarly, luminance signals Y2 to Y4 and color difference signals C2 to C4 corresponding to the second to fourth fields are stored in order. Assuming that the luminance signal Y2 and the color difference signal C2 in the second field are data currently input to the input buffers 1a and 1b, the data read out to the output buffers 2a and 2b are the luminance signals Y1 and
This is the color difference signal C1.

FIG. 8 shows the configuration of the input buffer unit 1.
Here, in order to simplify the description, the input buffer unit 1
Includes a single input buffer 1c. The same applies to the case where the input buffer unit 1 includes the input buffer 1a and the input buffer 1b as described above. It is also assumed that the input signal is 2 bits or 4 bits, and one word of the single port memory 6 is 2 bits or 4 bits.

The input buffer unit 1 includes an input signal write control unit 9 for controlling writing of an input signal, an input buffer 1c for temporarily storing an input signal, and a single port memory 6 for storing data stored in the input buffer 1c. And an input data read control unit 11 to be read.

FIG. 9 shows the configuration of the output buffer unit 2.
Here, in order to simplify the description, the output buffer unit 2
Includes a single output buffer 2c. The same applies to the case where the output buffer unit 2 includes the output buffer 2a and the output buffer 2b as described above.

The output buffer unit 2 includes an output signal read control unit 12 for controlling reading of an output signal, an output buffer 2c for temporarily storing input signals, and an output buffer 2c for storing data read from the single port memory 6. And an output data write control unit 13 stored in the memory.

Hereinafter, referring to FIG.
Will be described.

The video signal input to the input buffer unit 1 is sequentially written to the input buffer 1c.

FIG. 10 shows the configuration of the input buffer 1c. The input buffer 1c includes the memory cell array 10. 47 indicates a 1-bit memory cell in the memory cell array 10. Reference numerals 20 to 27 denote memory cells in which two 1-bit cells are paired. 28-37 is Wired OR
Is shown. 38 to 41 indicate flip-flops. Reference numeral 42 denotes a multiplexer for multiplexing data.
43 and 44 indicate selectors. Reference numerals 45 and 46 denote tristate buffers. Tri-state buffers 45, 4
6 outputs the input signal as it is when the control signal is at the L level, and outputs high impedance when the control signal is at the H level.

In the present embodiment, one column address is assigned to every four bits in the memory cell array 10 according to the internally input data and the bit width of the single port memory 6. The memory cell array 10 is divided into two regions, and the memory cells at column addresses 0 and ₁ are allocated to a region I ₁ , and the memory cells at column addresses 2 and 3 are allocated to a region I ₂ .

The memory cell array 10 is further divided into row addresses 0 and 1 every two bits in the horizontal direction. The memory cell of each address is wired-ORed with the corresponding bit of the memory bus. When the input video signal is 4 bits, data is written into both memory cells at row addresses 0 and 1, and when it is 2 bits, data is written only at row address 0.

When the input signal is a 2-bit data string, the data is first stored in the memory cell 20 at row address 0 and column address 0, and then stored in the memory cell 22 in the next cycle. Here, since the data is stored in all the memory cells belonging to the row address 0 in the area I ₁ , the data is read out to the memory bus in order to start writing to the single port memory 6. Since the memory bus is composed of 4 bits, the data of the memory cell 20 is stored in the wired OR2
8 and the data in the memory cell 22 is
The data is read out through the dOR 32, 4-bit data is assembled, and output to the flip-flops 38 to 41.

When the single-port memory 6 has four bits and one word, a clock signal having the same frequency as that for writing data to the single-port memory 6 is input to the flip-flops 38 to 41. Select signal L
By setting the level, the selector 43 outputs the output of the flip-flop 38 to the single-port memory 6, and the selector 44 outputs the output of the flip-flop 39 to the single-port memory 6. Similarly, the tri-state buffer 45 outputs the output of the flip-flop 40 to the single-port memory 6, and the tri-state buffer 46
The output of the flip-flop 41 is connected to the single port memory 6
Output to Therefore, the data output from the input buffer 1c is 4 bits, so that a 4-bit single port memory can be connected.

When the single-port memory 6 has two bits and one word, a clock signal having a frequency half the frequency of writing data to the single-port memory 6 is input to the flip-flops 38 to 41. The multiplexer 42 receives the outputs of the flip-flops 38, 39, 40, and 41 as inputs, and outputs the flip-flop 3
By selecting the signals 8 and 40, the data of the flip-flop 38 is output when the clock signal is at the H level, and the data of the flip-flop 40 is output when the clock signal is at the L level. The second output of the multiplexer 42 outputs the data of the flip-flop 39 when the clock signal is at the H level, and outputs the data of the flip-flop 41 when the clock signal is at the L level. Therefore, the multiplexer 42 outputs data at a data rate twice as high as that of the clock signal. By setting the select signal to the H level, the selector 43 outputs the first output of the multiplexer 42 to the single-port memory 6, and the selector 44
Outputs the second output of the multiplexer 42 to the single port memory 6. Tri-state buffers 45 and 46
Is in a high impedance state. Therefore, the data output from the input buffer 1c is 2 bits, and a 2-port single port memory can be connected. Region I ₂
When data is stored in the memory cells 24 and 26, the data can be output to the single port memory 6 by the same means.

When the input signal is a 4-bit data string, the first data is stored in the memory cells 20 and 21, and the second data is written in the memory cells 22 and 23. Here, since the data in all the memory cells belonging to the region I ₁ is stored, the data in the memory bus is read in order to start writing to the single port memory 6. Since the memory bus is composed of 4 bits, the first
The data in the memory cell 20 is read through the wired OR 28, the data in the memory cell 21 is read through the wired OR 29, and 4-bit data is assembled. Second, the data in the memory cell 22 is read through the wired OR 30 and the memory cell 23 is read. Is read through the wired OR 31 to assemble 4-bit data and output to the flip-flops 38 to 41.

With the above configuration, whether the input data is 2 bits or 4 bits, 4 bits 1 word or 2 bits 1 word
The data can be written in the single-port memory 6 having the word configuration. The input data is n bits (n is a natural number),
Even if one word of the single port memory 6 is m bits (m is a natural number), it can be realized by the same method. Further, the memory cell array of the output buffer unit 2 can be realized with the same configuration. Further, the order of the areas to be transferred to the single port memory 6 is not limited to the order shown in the present embodiment,
It is only necessary that all necessary data accumulated in the buffer can be transferred.

FIG. 11 shows the configuration of the write control unit 9.
In FIG. 11, reference numeral 50 denotes a differentiating circuit, 51 to 55 denote AND gates, and 57 to 60 denote flip-flops.
The reset signal is input to the differentiating circuit 50 and becomes a signal of one clock width. When the output of the differentiating circuit 50 is at the H level, the flip-flop 57 is set to the H level, and the flip-flops 58, 59, 60 are reset to the L level. In this state, the Write control unit 9 is in the initial state. Next, when the enable signal becomes H level, the clock signal is input to the flip-flops 57, 58, 59, 60, so that the value set in each flip-flop in the initial state is shifted to the right. That is, the output of the flip-flop 57 is at L level, the output of the flip-flop 58 is at H level,
Is at the L level, and the output of the flip-flop 60 is at the L level. At this time, the AND gates 52, 53, 54, 5
The outputs of No. 5 are at L, H, L and L levels, respectively. By connecting these signals to the write word line of the memory cell of the memory cell array 10, the input signals are sequentially stored.

FIG. 12 is a timing chart showing the operation of the write control unit 9. The output signal of the flip-flops 58 and 60, when the pointer output 1 and the output of the pointer 1 becomes H level, indicates that the region I ₁ of the input buffer 1c is satisfied, the output of the pointer 2 is H when it becomes level indicates that the region I ₂ of the input buffer 1c is satisfied. The pointer output is output from the input buffer to the control unit 3 as a write request to the single port memory 6. The output signal Read control unit 12 of the output buffer can be realized with the same configuration. The difference is that the pointer outputs 1 and 2 indicate that the output buffers are empty, respectively, and output a read request from the single port memory 6 to the control unit 3.

FIG. 13 shows the configuration of the input data read control unit 11. In FIG. 13, 70, 71, 72, 73
Shows the AND gate. Each AND gate outputs a signal indicating a column address of each area of the memory cell array 10 by decoding a control signal (address) output from the control unit 3. Note that the output data write control unit 13 can be similarly configured.

FIG. 14 shows the configuration of the control section 3. In FIG. 14, reference numerals 80 and 82 denote timing generators,
Reference numerals 81 and 83 denote address generators. Control part 3
Includes a buffer controller 4 having a timing generator 80 and an address generator 81, and a memory controller 5 having a timing generator 82 and an address generator 83.

FIG. 15A shows the structure of the timing generator 80. In FIG. 15A, reference numerals 84 and 87 indicate counters. Reference numerals 85 and 88 denote registers for setting initial values in the counter. 86 and 89 indicate RS flip-flops. 90 indicates an AND gate. The counter 84 is loaded with the value of the register 85 by the input vertical synchronization signal, and the RS flip-flop 86 is reset. The counting operation of the counter 84 starts from the next cycle, and n
After the count, a carry-out signal is output. The carry-out signal becomes a reset signal to the differentiating circuit 50 of the input signal Write control unit 9 in FIG. Further, the counter 87 stores the register 8 in response to the input horizontal synchronization signal.
The value of 8 is loaded and the RS flip-flop 89 is reset. The count operation of the counter 87 starts from the next cycle, and after the count of m times, the carry-out signal is output. The carry-out signal becomes a set signal of the RS flip-flop 89. The enable signal is the output of the AND gate 90 and goes high when the outputs of the RS flip-flops 86 and 89 are both high.

FIG. 15B shows the structure of the address generator 81. In FIG. 15B, reference numeral 91 denotes a counter. The counter 91 is reset by the pointer signal output from the input signal Write control unit 9 and counted from the next cycle. The counted value becomes an address output as it is, and is input to the input data read control unit 11. The timing generator 82 and the address generator 83 of the memory control unit 5 can be realized with the same configuration.

In this embodiment, the pointer output of the write control unit 9 is two because the area is divided into two parts. However, if the area is further subdivided, the pointer output increases accordingly. Since the area can be generally divided into L (L: a natural number of 2 or more), the number of pointers is also generally L. FIG.
In the case of the memory cell array 10 indicated by 0, four regions can be set by further dividing the regions I ₁ and I ₂ into two. That is, the memory cell at column address 0 is in area I
₁ , column address 1 is area I ₂ , column address 2 is area I ₃ ,
Column address 3 becomes area I ₄ . At this time, the Write
In the control unit, the output of the flip-flop 57 is the pointer 1, the output of the flip-flop 58 is the pointer 2, the output of the flip-flop 59 is the pointer 3, and the output of the flip-flop 60 is the pointer 4.

FIG. 21 shows a configuration when a pointer output is added to the input signal Write control section 9 of FIG. FIG.
, 50 is a differentiating circuit, 51 to 55, 130, 13
1 indicates an AND gate, and 57 to 60 indicate flip-flops. The mode selection signal is a signal that becomes L level when the area is divided into two and H level when the area is divided into four.

As shown in FIG. 21, in the present embodiment,
The output of AND gate 130 is pointer output 1, the output of flip-flop 58 is pointer output 2, AND gate 131
Is the pointer output 3 and the output of the flip-flop 60 is the pointer output 4. Each pointer output is
When the area is divided into two, the pointer 2 indicates that the area I ₁ has been filled, and the pointer 4 indicates that the area I ₂ has been filled. When the area is divided into four parts, the pointer 1 moves to the area I
₁ indicates that area ₁ has been filled, pointer 2 indicates that area I ₂ has been filled, pointer 3 indicates that area I ₃ has been filled, and pointer 4 indicates that area I ₄ has been filled. .

Mode selection signal and AND gates 130 and 13
Since the mode selection signal is at the L level when the area is divided into two by introducing the pointer output 1, pointer output 1,
No. 3 is always at the L level, the memory writing is not started, and when the pointer output 2 or 4 becomes the H level, the memory writing is started. When the area is divided into four, the mode selection signal becomes H level, so that memory writing is started in response to all pointer outputs. Therefore, by introducing a mode selection signal and an AND gate as shown in FIG. 21, it is possible to add a means for selecting the size of the area and changing the write control to the single port memory 6.

FIGS. 16A and 16B show Wr of FIG.
Single port memory 6 when using ite control unit 9
2 shows a memory map of the first embodiment. FIG. 16A shows an initial state. Figure 16 (b) is a memory map when data is written in the area I _1. When memory access is performed using the buffer in this manner, the single port memory 6
The minimum unit of access to is dependent on the size of the area.

FIGS. 17A to 17D show a memory map of the single-port memory 6 when the area is further subdivided and divided into four parts. FIG. 17A shows an initial state. FIG.
7 (b) is a memory map when data is written in the area I _1. FIG. 17 (c), the a memory map when (d) are written to the data region I _2. By subdividing the region, as shown in FIG. 17C, the same memory address as when the region is divided into two, that is, FIG.
Writing data in the same manner as in FIG.
Data can be written to completely different memory addresses as shown in FIG. When a memory interface device is configured using a buffer, since the control unit of the memory address depends on the size of the area of the buffer, by providing a means for selecting the size of the area, finer memory address control can be performed. It becomes possible.

Next, a method for handling a plurality of videos having different video signal rates and horizontal frequencies will be described.

FIG. 18 shows a configuration of an arbitration circuit for arbitrating a write request to the single port memory 6 and a read request from the single port memory 6. The arbitration circuit
It can be included in the control unit 3. In FIG.
Reference numerals 97 indicate registers for setting by the user. 9
8 to 101 are AND gates. Reference numeral 102 denotes an arbiter for arbitrating requests.

In this embodiment, the input signal 1 is stored in the input buffer, the signal indicating that the buffer is full is the pointer output A, the input signal 2 is stored in the input buffer, and the buffer is full. A signal indicating that the buffer output becomes empty, a pointer output B outputs an output signal 1 from the output buffer, a signal indicating that the buffer becomes empty outputs a pointer output C, and an output signal outputs from the output buffer 2 and the buffer becomes empty. Is a pointer output D. The priority of the write request and the read request of the single port memory 6 is represented by a register set value of 2 bits. The highest priority is "11", the second priority is "10", and the first priority is "01". "When lowest priority,"
When "00", it is assumed that there is no write or read request. Note that the priority order depends on the application in which the memory interface device is used.
Any number of register setting values may be used.

When the input signal 1 fills the first area of the input buffer, the pointer output A goes high, and the value set in the register 94 is sent to the arbiter 102 as a write request Write REQA signal through the AND gate 98. Is entered. Similarly, when the input signal 2 fills the second area of the input buffer, the set value of the register 95 changes to the write request Wri.
When the te REQB signal is input to the arbitrator 102 and the output signal 1 empties the first area of the output buffer, the set value of the register 96 is input to the arbitrator 102 as a read request Read REQA signal, and the output signal 2 Empties the second area of the output buffer, the set value of the register 97 is input to the arbitrator 102 as a read request Read REQB signal.

The arbitrator 102 has a priority determined in advance in terms of hardware. When a write request or a read request is made, the arbitrator 102 processes according to the priority. In this embodiment, Write REQA has the highest priority, Write REQB has the second priority, and Read REQA has the highest priority.
Is the third priority, and Read REQB is the lowest priority. If another priority is desired, the user of the memory interface device can use the register 94,
95, 96 and 97 are set. For example, if you want Read REQB to have the highest priority, register 97
Is set to "11".

FIG. 19 shows what value the arbitrator 102 outputs for each register setting.

In FIG. 1 is the register 94
Is set to “11”, and the output of the arbitrator 102 when the pointer output A becomes H level. In this case, the Write Mode A of the single port memory 6 always goes to the H level regardless of other write requests, read requests, and register settings. This is because the arbiter 102 is configured to process the request for pointer output A as the highest priority. For example, when the memory cell array of the input buffer is configured as shown in FIG. 10 and the input signal 1 is stored in the row address 0, when the Write Mode A becomes H level, the read control unit of the input buffer sets the row address to 0.
Reads out the area where the column address is 0 and 1 and processes the write request to the single port memory 6 and outputs the pointer output A
Returns to the L level.

No. 2 is the arbitrator 1 when the register 94 is set to "10" or less and the register 95 is set to "11".
02 output. In this case, the Write Mode B of the single port memory 6 always goes to the H level regardless of other write requests, read requests, and register settings. Since the arbiter 102 is configured to process the request for the pointer output B as the highest priority, the user sets the priority of the pointer output A to “10” in the register 94 to change the priority. This is because the priority is increased by setting the priority of the pointer output B to "11" in the register 95. Hereinafter, No. In the case of 3 to 12,
Processing is performed based on a similar rule.

(Embodiment 2) Next, as Embodiment 2, a method of outputting an input signal with a simple delay using an input buffer and an output buffer will be described.

FIG. 20 shows a memory cell array 121 of the input buffer unit 1 and a write bus to the single port memory 6, and a memory cell array 122 of the output buffer unit 2.
2 shows a configuration of a bus for reading from the single port memory 6. 20, reference numerals 20 to 27 and 104 to 111 denote memory cells in which two 1-bit cells are paired.
Reference numeral 121 denotes a memory cell array representing the entire memory cell of the input buffer unit 1. Reference numeral 122 denotes a memory cell array representing the entire memory cell of the output buffer unit 2. 28-3
Reference numerals 6, 112 to 120 denote two wired ORs. In the present embodiment, it is assumed that one word of the single port memory 6 is 4 bits.

The memory cell array 12 of the input buffer unit 1
When 1 is satisfied, it is normally output to the single port memory 6 through WiredORs 28-36. Since the write bit line and the read bit line of the memory bus are connected, the same means can be used to write data directly from the memory cell array 121 of the input buffer unit 1 to the memory cell array 122 of the output buffer unit 2. Is possible. For example, data of the memory cell 20 is wired OR
If the wired OR 112 is turned ON at the same time when reading through the memory, the data can be written to the memory cell 104.

With the above configuration, the input signal can be simply delayed and output using the input buffer and the output buffer. In the above example, the input signal is output with a delay of 4 to 8 clocks.

Note that the number of bits and the number of words in the buffer are not limited to the present embodiment.

[0092]

According to the first aspect of the present invention, while transferring a signal stored in a specific input area among a plurality of input areas of an input buffer to a single port memory, a signal other than the specific input area is transferred. While the input signal is stored in the input area of the output buffer and the signal stored in the specific output area among the plurality of output areas of the output buffer is output as the output signal, the signal stored in the single port memory is output to the specific output area. Transferred to an output area other than the area. This makes it possible to output a signal read from the single port memory as an output signal in real time while writing the input signal to the single port memory. Furthermore, by increasing the number of input areas of the input buffer and the number of output areas of the output buffer, the minimum unit of the amount of data transferred at one time can be reduced. As a result, fine address control can be performed.

According to the second aspect of the present invention, the output bus width of the input buffer is converted into the input bus width of the single port memory, and the output bus width of the single port memory is converted into the input bus width of the output buffer. A bus width conversion circuit is provided. This makes it possible to realize a system that does not depend on the bus width of the single-port memory.

According to the third aspect of the present invention, the input buffer is divided into a plurality of input areas corresponding to the bit direction and the word direction of the input buffer. And a plurality of output areas corresponding to the word direction. By making the division in the bit direction programmable, it is possible to access the intended address of the single port memory for each area regardless of the bit width of the input signal. As a result, the single port memory can be used effectively. Further, it is possible to input and output a plurality of signals of different synchronization systems.

According to the fourth aspect of the present invention, the arbitration circuit for prioritizing the access request signals according to a predetermined standard is provided. Accordingly, when a plurality of signals of different synchronization systems are input / output, access to the single-port memory can be preferentially permitted for a signal having a high signal rate. As a result, real-time control can be performed without failure.

According to the fifth aspect of the present invention, there is provided a circuit for directly writing a signal output from an input buffer to an output buffer. As a result, the input signal can be simply delayed using the input buffer and the output buffer and output.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a memory interface device according to a first embodiment.

FIG. 2 is a diagram illustrating a configuration of an input buffer 1a.

FIG. 3 is a time chart showing a timing of writing data to a single port memory 6;

FIG. 4 is a diagram showing a configuration of an output buffer 2a.

FIG. 5 is a time chart showing a timing of reading data from a single port memory 6;

FIG. 6 is a time chart showing timing when data is read from and written to the single port memory 6 in real time.

FIG. 7 is a diagram showing an example of a memory map of a single port memory 6;

FIG. 8 is a diagram illustrating a configuration of an input buffer unit 1;

FIG. 9 is a diagram showing a configuration of an output buffer unit 2;

FIG. 10 is a diagram showing a configuration of a memory cell array 10;

FIG. 11 is a diagram illustrating a configuration of a write control unit 9;

FIG. 12 is a time chart showing the operation timing of the write control unit 9;

FIG. 13 is a diagram illustrating a configuration of an input data read control unit 11;

FIG. 14 is a diagram showing a configuration of a control unit 3.

15A is a diagram showing a configuration of a timing signal generator 81, and FIG. 15B is a diagram showing a configuration of an address generator 82. FIG.

FIGS. 16A and 16B are diagrams showing an example of a memory map of a single port memory 6. FIG.

17 (a) to (d) show a single port memory 6;
FIG. 3 is a diagram showing an example of a memory map of FIG.

FIG. 18 is a diagram illustrating a configuration of an arbitration circuit.

FIG. 19 is a diagram showing an output of the arbitrator 102.

FIG. 20 is a diagram showing a configuration of a memory array of an input buffer unit 1 and an output buffer unit 2;

FIG. 21 is a diagram illustrating another configuration of the input signal Write control unit 9;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input buffer part 2 Output buffer part 3 Control part 4 Buffer control part 5 Memory control part 6 Single port memory 9 Input signal Write control part 10 Memory cell array 11 Input data Read control part 12 Output signal Read control part 13 Output data Write control part 47 memory cell 50 differentiating circuit 80 timing generator 81 address generator 82 timing generator 83 address generator 102 arbitrator

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kazuki Ninomiya 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. Within Sangyo Co., Ltd. (72) Inventor Kenta Samukawa 1006 Kazuma Kadoma, Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. Instrument Co., Ltd. 2355 Murakihara (56) References JP-A-10-326342 (JP, A) JP-A-3-29179 (JP, A) (58) Fields investigated (Int. Cl. ⁷⁾ H04N 5/76-5/956 H04N 7/01 H04N 9/79-9/898 G06F 5/06 G11C 7/00 G11C 11/40-11/4197

Claims (5)

(57) [Claims] 1. A and input <br/> force buffer for a given signal having a plurality of input regions, and output <br/> force buffer for a given signal having a plurality of output regions, the input buffer and the output buffer And a control unit for controlling a predetermined single port memory, wherein each input area of the input buffer is logically divided.
Therefore, each output area of the output buffer is logically divided.
The control unit may include a plurality of areas of the input buffer.
While transferring the input signal accumulated in a specific input region to the single port memory, and controls the input buffer and the single port memory to store the input signal in the input area other than the specific input region The control unit outputs the signal stored in the single-port memory to the specific output while outputting a signal stored in a specific output area of the plurality of output areas of the output buffer as an output signal. A memory interface device that controls the output buffer and the single-port memory so as to transfer the data to an output area other than the area; 2. An input buffer having a plurality of input areas.
An output buffer having a plurality of output areas;
Buffer and the output buffer and a predetermined single port
And a control unit for controlling the memory and the plurality of input areas of the input buffer
The signal stored in a specific input area of the
During the transfer to the port memory,
The input buffer so as to store the input signal in an external input area.
And the single port memory, wherein the control unit controls the plurality of output areas of the output buffer.
The signal accumulated in a specific output area of the
Output to the single port memory.
Transferred to the output area other than the specific output area.
The output buffer and the single port
A bus width conversion circuit for controlling a memory, converting an output bus width of the input buffer into an input bus width of the single port memory, and converting an output bus width of the single port memory into an input bus width of the output buffer; A memory interface device, further comprising: 3. An input buffer having a plurality of input areas.
An output buffer having a plurality of output areas;
Buffer and the output buffer and a predetermined single port
And a control unit for controlling the memory and the plurality of input areas of the input buffer
The signal stored in a specific input area of the
During the transfer to the port memory,
The input buffer so as to store the input signal in an external input area.
And the single port memory, wherein the control unit controls the plurality of output areas of the output buffer.
The signal accumulated in a specific output area of the
Output to the single port memory.
Transferred to the output area other than the specific output area.
The output buffer and the single port
Controlling the memory, the input buffer is divided into a plurality of input areas corresponding to the bit direction and the word direction of the input buffer, and the output buffer is arranged in the bit direction and the word direction of the output buffer. A memory interface device correspondingly divided into a plurality of output areas. 4. The input buffer and the output buffer each output an access request signal for the single port memory to the control unit, and the control unit prioritizes the access request signal according to a predetermined criterion. The arbitration circuit is provided.
3. The memory interface device according to claim 1. 5. An input buffer having a plurality of input areas.
An output buffer having a plurality of output areas;
Buffer and the output buffer and a predetermined single port
And a control unit for controlling the memory and the plurality of input areas of the input buffer
The signal stored in a specific input area of the
During the transfer to the port memory,
The input buffer so as to store the input signal in an external input area.
And the single port memory, wherein the control unit controls the plurality of output areas of the output buffer.
The signal accumulated in a specific output area of the
During the to output, it is stored in the single port memory
Transferred to the output area other than the specific output area.
The output buffer and the single port
An interface device, further comprising a circuit that controls a memory and directly writes a signal output from the input buffer to the output buffer.