JPS60136541U

JPS60136541U - level detection circuit

Info

Publication number: JPS60136541U
Application number: JP449985U
Authority: JP
Inventors: 芳昭佐野; 花沢　敏夫; 平松　良
Original assignee: 富士通株式会社
Priority date: 1985-01-17
Filing date: 1985-01-17
Publication date: 1985-09-10

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図はヒステリシス特性を有する従来のレベル検出回
路の一例を示す回路図、第２図はその入出力特性図、第
３図は本考案の実施例を示す回路図、第４図のａ、　ｂ
はベース電流をグランドへ落す例を示す要部回路図、第
５図はｈＦｅ対策の例を示す回路図である。図中、Ｑ２はラテラル、ｐｎｐトランジスタ、Ｑ工はダ
イオード、ｑはｐｎｐ）ランジスタ、Ｉ−１は負荷回路
、（４，Ｑ４は一対のｎｐｎ　）ランジスタ、Ｊｌは定
電流源、ＩＮは入力信号：　ＤＩＦは差動対、Ｑ６はｐ
ｎｐトランジスタ、Ｑ５はｎｐｎトランジスタ、Ｒ１は
抵抗、Ｑ７はダイオード、ＯＵＴは出力端、ＲＴはラッ
チ回路である。FIG. 1 is a circuit diagram showing an example of a conventional level detection circuit having hysteresis characteristics, FIG. 2 is its input/output characteristic diagram, FIG. 3 is a circuit diagram showing an embodiment of the present invention, and FIG. b
5 is a main circuit diagram showing an example of dropping the base current to ground, and FIG. 5 is a circuit diagram showing an example of measures against hFe. In the figure, Q2 is a lateral pnp transistor, Q is a diode, q is a pnp) transistor, I-1 is a load circuit, (4, Q4 is a pair of npn) transistors, Jl is a constant current source, and IN is an input signal: DIF is a differential pair, Q6 is p
Q5 is an npn transistor, R1 is a resistor, Q7 is a diode, OUT is an output terminal, and RT is a latch circuit.

Claims

[Claims for Utility Model Registration] A lateral pnp t' transistor, a diode connected between the base and emitter of the transistor, and a pnp l' transistor in which the emitter is connected to the base of the transistor and the base is connected to the collector. a differential pair having a pair of nPn transistors and a constant current source, receiving an input signal at the bases of the pair of transistors, and having their collectors connected to the collectors of both transistors of the load circuit, and a pnp)' a transistor, an npn transistor whose collector is connected to the base of the transistor, a resistor connected in series to the emitter of the npn transistor, and the other end of the resistor connected to the npn transistor;
a diode connected between the base of the pnp transistor and the emitter and base of the pnp transistor connected to the collectors of both transistors of the differential pair;
A level detection circuit comprising a latch circuit whose output terminal is the other end of the resistor.