JPS6012874B2 - digital phase shifter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital phase shifter, and more particularly to four-type and simplified phase shifters for controlling the voltage of static inverters and the like.

In general, the output of a static isoverter is obtained by multiplexing the outputs of multiple unit inverters via a transformer to obtain a predetermined output voltage. - Only the same quantity is required, which increases the number of parts used and complicates the circuit.

Furthermore, it is extremely difficult to exactly match the characteristics of each phase shifter under any conditions, and the difference in output voltage of each unit inverter due to variations in phase shift characteristics causes the output voltage of a static inverter to Imbalance is inevitable. The present invention was made to solve this problem, and it is possible to drive a large number of unit inverters with one phase shifter regardless of the number of unit inverters, and to create a stable and highly accurate digital phase shifter. This is what we intend to provide.

Hereinafter, the present invention will be described in detail with reference to the drawings, taking as an example a circuit that generates three phase-shifted signals for each characteristic phase difference of x/6.

FIG. 1 is a circuit diagram showing a basic embodiment of the present invention, and FIG. 2 is a timing chart illustrating the operation of FIG.

Figures 2 through 2 respectively show the operating states and contents of the same reference numerals shown in Figure 1. The configuration diagram of FIG. 1 will be explained using the operation timing chart of FIG. 2. As shown in the solid line waveform in FIG. 2A, the reference counter 2 in FIG.
The operation is repeated at a frequency twice the output frequency of the inverter. The flip-flop 4 (waveform at the beginning of FIG. 2) performs an inverting operation every time the reference counter 2, which is an N-ary counter, determines the output frequency of the inverter and serves as a reference signal for each phase shift signal. Like the reference counter 2, the up/down counter 3 in FIG. 1 normally counts up the pulses from the oscillator 1 as clock pulses, and sequentially outputs the count contents to the D/A converter 5. The D/A converter 5 converts the digital value of the up/down counter 3 into an analog value, and the comparator 6 compares the converted analog value with the voltage control signal, and the output of the D/A converter 5 is used for voltage control. When the signal level is reached, the comparator S generates a pulse signal as shown in FIG. A pulse train consisting of this pulse signal is applied as a down-count Z signal to the up-down counter 3, and the contents of the up-down counter 3 are instantaneously counted down by N (dotted line waveform in Figure 2 A).
At the same time, it is applied as a shift pulse to a shift register 7 for distributing a signal having a predetermined phase difference from the pulse train. The predetermined signal of the output of Z register 7 (second
The flip-flop 8 is triggered at the point in time (t2 in FIG. 2) when the output voltage changes (t2 in FIG. 2), and the output state of the flip-flop 4 is transmitted to the output of the flip-flop 8. Further, at the same time, the up/down counter 3 is preset so that the output state 2 of the up/down counter 3 becomes the output state of the reference counter 2. Therefore, the value preset in the up/down counter 3 changes depending on the voltage control signal level, and the phase of each output of the shift register 7 with respect to the output signal 2 of the flip-flop 4 is determined by the amount of phase shift according to the voltage control signal. The phase will be shifted by an amount equal to the phase difference of . As explained above, according to the present invention, a large number of phase-shifted signals can be obtained with one phase shifter, and all the phase-shifted signals are phase-shifted by the same amount with respect to the voltage control signal. An ideal digital phase shifter is realized.

Here, in the embodiment of the present invention described above, N=6×N
, that is, a circuit that generates 3 to 6 phase-shifted signals during a half cycle of the output frequency has been described, but N=n×N,
Of course, by setting (n>1), n phase-shifted signals can be obtained for each characteristic phase difference of m/n.

Further, in the embodiment of the present invention, the normal operation of the reference counter 2 and the up/down counter 43 has been explained as an up counter, but this is replaced with a down counter and the output pulse of the comparator 6 controls the up/down counter 3 by a predetermined number (this embodiment Then, by counting up N,), the first
It goes without saying that the digital phase shifter has a phase shift characteristic in the opposite direction to that of the digital phase shifter explained in FIGS. Although the digital phase shifter having an evenly spaced characteristic phase difference has been described in FIG. 1 and FIG. A digital phase shifter that shifts the phase of each phase signal by the same amount will be described with reference to FIG. 3 showing its circuit configuration and FIG. 4 showing its operating state.

Figures 4 to 4 respectively show the operating states and contents of the same reference numerals shown in Figure 3. As shown in the configuration diagram of FIG. 3, in addition to the configuration diagram of FIG. 1, a down count amount setter 9 is provided. A down-count amount corresponding to a desired characteristic phase difference is repeatedly set with respect to the reference phase which is the output of the flip-flop 4 shown in the opening of FIG. Each time is applied, the down count amount set in the down count amount setter 9 is sequentially counted down.

That is, N=N. By setting 10N20...10Nn-10Nn, any characteristic phase difference N.・Tei/N, (NI+
N2), Shimano N,. ,,...(NI ten N2 ten... ten Nn-
・), 怀ノN, (NI ten N2 ten... ten Nn-・ten Nn)
- n phase shift signals are obtained by adding a phase shift amount of 8 corresponding to m/N' voltage control signal.

As explained above, if the voltage control by the digital phase shifter of the present invention is used for voltage control of an inverter, etc., excellent characteristics will be exhibited and its industrial value will be extremely large.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of an embodiment showing the basic configuration of the present invention. FIG. 2 is a timing chart explaining the operation of FIG. 1. In FIG. The operating status and contents of FIG. 3 is a circuit configuration diagram showing another embodiment according to the present invention, and FIG. 4 is a timing chart explaining the operation shown in FIG.
Figures 1 to 3 show the operating states of the same reference numerals in Figure 3. 1... Oscillator, 2... Reference counter, 3... Up/down counter, 4, 8...
...Flip-flop, 5...D/A converter, 6
...Comparator, 7...Shift register, 9.
...Down count amount setting device. Younger brother's illustration of his life, figure 3, younger brother, figure 4

Claims (1)

[Claims] 1 A predetermined number of clock pulses with a predetermined frequency (
A reference counter that counts up (or down) and operates repeatedly, and goes up (or down) with the clock pulse.
The D/A converter comprises an up-down counter for counting, a D/A converter for converting the count contents of the up-down counter into an analog quantity, and a comparator for comparing the output of the D/A converter with a control command. The up-down counter is counted down (or up) by a predetermined amount using a pulse train generated every time the comparator detects that the output has reached the control command level, and when a predetermined pulse of the pulse train is generated, the up-down counter is counted down (or up) by a predetermined amount. A digital phase shifter characterized in that an up-down counter reads the contents of the reference counter.