SU951588A1 - Digital phase-shifting device - Google Patents

Description

one

The invention relates to electrical engineering and industrial electronics and can be used in thyristor converters.

Digital phase shifters are known, the phase of which is controlled by changing the frequency ft and the code t21.

The disadvantage of these phase shifters is the dependence of the phase being formed on the frequency of the synchronizing voltage.

Closest to the present invention is a digital phase shifting device comprising a clock generator, a pulse counter and a synchronizer with two outputs. In this device, the invariance of the formed phase with respect to frequency is achieved due to the presence of a double conversion — syachal of a part of the synchronization voltage period into a code, and then received. code in the time interval (phase) D3

2

The disadvantages of this device are the inability to control the phase with a digital code from a control computer or a control digital device and the complexity of the device. The phase generated by the device is proportional to the frequency ratio of the oscillators of a constant frequency and voltage controlled frequency generator, which makes the accuracy of the generated phase low and the more complex circuit design of the generators providing the required accuracy complicates and reduces the complexity of the generators due to their instability. the phase shifting device becomes more expensive.

The use of the ability to control the phase by means of a digital-to-analog converter code at the input of a voltage-controlled generator leads to a considerable complication and cost of the phase-shifting device.

39

The purpose of the invention is to simplify the phase shifter and increase its accuracy.

This goal is achieved by the fact that in a digital phase shifter containing a clock generator, a pulse counter and a synchronizer with two outputs, the pulse counter is reversible, two frequency dividers are inserted at the output of the clock generator, the first of which is output through the introduced two-input element-NOT connected to the summing input of the counter, and the output of the second through the entered three-input logic element AND NOT connected to the subtractive input of the counter, the first and second outputs Synchronizers are connected respectively to the inputs of the two-input and three-input logic elements of the NAND, the counter reverse transfer output is connected to the S-input of the entered SR flip-flop, the second synchronizer output is connected to the R-input of the SR flip-flop, and the output of the trigger is connected to the input of the three-input logic element .nta AND-NOT.

The division ratio of the second frequency divider is controlled by code.

Fig. 1 shows a diagram of a digital phase-shifting device consisting of a generator of such voltage pulses 1, a frequency divider with a constant division factor of 2, a frequency divider with a division factor of control code 3, two-input logic element 4, three-input logic element 5, reversing counter 6, synchronizer 7 and SR flip-flop 8.

Figure 2 shows the time diagrams of the voltage on the elements of the circuit of Figure 1: the a axis shows the synchronization voltage and (-; on the axis 6 and c is the voltage respectively on the first and second outputs of the synchronizer 1 on the a axis - the number in counter 6; d axis - voltage at the output of the reverse transfer of the counter; 6; for OSM S and - for example, for direct and second, respectively, the trigger output 8

A digital phase shifter operates as follows.

The sinusoidal voltage 1 coming to the synchronizer 7 input (Fig. 2a) is npi-formed in a rectangular one at the outputs 1 and 2 (Fig. 2b, c)

15884

and is fed to the inputs of the NAND and S- elements. The frequency of the clock generator 1 FQ is divided by divisor 2 by the number N, has output 2 the value 5 f / I% / M and is fed to the input of the element L. For a time equal to half the voltage period sync

1s.

when a whitefish arrives

from exit 1 syn. chronizer 7, the pulses from output 2 are fed to the summing input of the reversing estimator 6. The number of pulses that will be recorded in counter 6 is equal to the number of pulses with a period of 1 / fL in the interval

Vo.

(t) aNi

. at time T / 2, the signal at output 1 of synchronizer 7 is changed to logical O, and at output 2 to logical 1. At the same time, the flow of impulses from element 4 to the input of counter 6 stops, and through element 5 from divider 3 to the subtracting input of counter 6, pulses start to arrive at a frequency f fp / N, where the number corresponding to the control code, 1 N, N. Time 1 (for which the number in the counter 6 changes from N to zero, is equal to

S

N,

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at the moment t, when the number of the counter reaches 6, the zero value at the output

reverse transfer 6 is formed by the pulse of FIG. 25 throwing the SR flip-flop 8. This will remove the logical 1 signal from input 5 coming from the direct SR-tri1 output

Claims (3)

Hera 8 of Fig. 2e and the arrival of pulses from 3 to subtractive input 6 is stopped, preventing the number from decreasing below zero. This state continues until the synchronization voltage transition time T is zero, after which the trigger 8 is thrown by the signal from the output 2 of the synchronizer 7, the input of the element from the first output of the synchronizer 7 receives a logical 1 signal, the pulses from the divider 2 are fed to the totalizer input 6 and the process described is repeated. The leading edge of the inverse trigger output 8. (.Fig.2) {or the trailing edge of the non-inverted output) is informative. The phase to be f is equal to, N, .N cV - T- follows from (3) the generated phase does not depend on the frequency of the network and has a linear dependence on the control code LH,. The frequency of the clock pulse generator 1 fp is also absent in the conversion function (2), which makes it invariant with respect to frequency instability fp. The latter circumstance is an additional advantage of the phase shifter, increasing its accuracy. The proposed frequency-independent phase-shifting device can work in the same mode as the prototype, in which the synchronizer signal for filling the counter is shorter than half of the period T (90 electr.) And there is a pause of 30 electr. between fill and subtract modes. This mode is completely determined by the outputs of the outputs 1 and 2 of the synchronizer 7, for the counter 6 in the absence of pulses on one of its inputs stores the number recorded in it. The advantage of the proposed digital phase-shifting device is the invariance of the formed phase relative to the synchronization voltage frequency, clock frequency, simplicity of its implementation and greater accuracy, the value of which can be predetermined by the discreteness error AND, ultimately, the number of bits of the counter, divider and code. A digital phase shifter comprising a clock pulse generator, a pulse counter and a synchronizer with two outputs, characterized in that, in order to simplify and improve accuracy, the pulse counter is reversible, two input frequency dividers, the first output, are connected to the clock pulse generator output. of which through the input two-input logic element AND-NOT connected to the summing input of the counter, and the output Btoporo through the input three-input I logic element AND-NOT connected to the calculator to the input of the counter, the first and second outputs of the synchronizer are connected respectively to the inputs of the two-input and three-input logic elements AND-NOT, the output of the reverse transfer of the counter is connected to the S-input of the entered ZI-flip-flop, the second output of the synchronizer is connected to the R-BXO SR-trigger. and the output of the SR flip-flop is connected to the input of a three-input logic element. Sources of information taken into account in the examination 1.Patent of Germany No. 1538135, cl. H 02 M 1/08, 1972. 2. USSR author's certificate number 629621 ,. cl. H 02 R 13/16, 1977. 3.E1ektrotechIsche Zeltschrift, Bd E, 1973, H 1, p. 31-3.