GB1582400A

GB1582400A - Control systems for pulse with control type inverter

Info

Publication number: GB1582400A
Application number: GB53651/77A
Authority: GB
Original assignee: Tokyo Shibaura Electric Co Ltd
Current assignee: Toshiba Corp
Priority date: 1976-12-23
Filing date: 1977-12-23
Publication date: 1981-01-07
Also published as: AU510671B2; CA1097737A; DE2757053C3; DE2757053A1; DE2757053B2; AU3192477A

Description

(54) CONTROL SYSTEMS FOR PULSE WIDTH CONTROL TYPE INVERTER (71) We, TOKYO SHIBAURA DENKI KABUSHIKI KAISHA, a Japanese Company, of 72, Horikawa-Cho, Saiwai-Ku, Kawasaki-Shi, Kanagawa-Ken, Japan, do hereby declare the invention, for which we pray that a patent may be granted to us,- and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to a control system of a pulse width control type inverter.

One example of the application of the pulse width control type inverter involves a non-interruption or always available source of electric supply. Since such source is connected with such load as computers, electric communication apparatus or the like it is desired to have a fast transient response for such external disturbance as the variations in DC voltage and load.

As diagrammatically shown in Figure 1, a conventional pulse width control type inverter comprises four semi-conductor switching elements 1 through 4, such as power transistors and thyristors, which are ON-OFF controlled in a predetermined sequence for converting the power of a DC source E into alternating current which is applied to an AC load 5. In order to maintain the voltage across load 5 at a constant value irrespective of variations in the DC voltage E, usually the conduction periodes of the switching elements 1 - 4 are controlled in accordance with the magnitude of the DC voltage or the conduction periods of switching elements 2 and 4 alone are controlled while the conduction periods of the switching elements 1 and 3 are maintained fixed.

Figure 2 shows one example of a control system which controls the conduction periods of the switching elements 1 - 4 and comprises a reference pulse generator 11 generating a pulse having a frequency of an integer multiple (in this example, twice) of the output frequency of the inverter for determining the frequency thereof a sawtooth wave generator for generating a signal synchronously with the generation of the reference pulse, a constant voltage control circuit 13 for producing an analogue signal having a level corresponding to the DC voltage for the purpose of obtaining a desired output voltage, an analogue comparator 14 which compares the output of the sawtooth wave generator with the output of the constant voltage control circuit 13, a ring counter 15 which in response to the output of the comparator 14 forms a pulse signal adapted to ON-OFF control the switching elements 1 - 4 shown in Figure 1 in a predetermined sequence, and a pulse amplifier 16 which amplifies the output of the ring counter 15 to a level that can directly ON-OFF control the switching elements 1 to 4.

Figure 3A shows waveforms useful to explain the operation of the control system shown in Figure 2 in which A, B and C show the waveforms at corresponding portions of the system shown in Figure 2. The dotted line level of curve B corresponds to the output of the constant voltage control circuit 13. While this level is higher than that of the output of the sawtooth wave generator 12 the output C of the analogue computer 14 becomes "1" whereas while the output level of the sawtooth wave generator 12 is higher than the former, the output C becomes "0". During an interval in which the output C of the analogue comparator 14 is "1'* a control signal is applied to the inverter through ring counter 15 and pulse amplifier 26 for rendering ON the switching elements 1 - 4 in a predetermined sequence thus producing an alternating currents output as shown by curve D. In this manner, the conduction period 6 of the switching elements 1 to 4 vary dependent upon the output level of the constant voltage control circuit 13. Accordingly, the output voltage shown by curve D is controlled such that the product EXO of the DC voltage E and the conduction period 0 would be always constant. Then, it is possible to always obtain a constant output voltage regardless of the variation in the DC voltage E.

The control system described above, however, can not provide an efficient control by following up the output of the constant voltage control circuit where the DC voltage varies rapidly. which occurs when switching is made between a commercial source and a battery source. Figure 3B shows enlarged views of portions of curves B and D shown in Figure 3A and useful to explain the operation of the control system when the DC voltage varies rapidly. In Figure 3B, lines a, b and c of curve B show the output of the constant voltage control circuit 13. Since lines a, b and c intersect the output of the sawtooth wave generator 12 at the same level, the conduction periods 0 are the same. Even when the constant voltage control circuit 13 has no internal delay and is provided with DC voltage detecting means for the purpose of improving its control ability, where the DC voltage varies as shown by curve D-b, Figure 3B, the output of the constant voltage control circuit 13 varies as shown by curve B-b, Figure 3B, whereas when the DC voltage varies as shown by curve D-c. the output of the constant voltage control circuit varies as shown by curve B-c. In each case, however, the conduction period n is equal to that when the DC voltage is constant as shown by curve D-a. Accordingly, where the DC voltage is constant, product EXO is also constant, but when the DC voltage varies as shown by curve D-b, a deficiency shown by hatched portion 1 and having an area of AElxO 2 appears as an error, whereas when the DC voltage varies as shown by curve D-c. a surplus shown by hatched portion 2 and having an area of AE2xO 2 also appears as an error. Thus, with the control system described above where the rate of variation of the output of the constant voltage control circuit is large, it is difficulty to obtain high response speed. While the foregoing description was made with respect to the variation of the DC voltage, the same difficult also arises when the output voltage varies due to rapid variation of the load.

Where the control system is constructed by using analogue technique, the sawtooth wave generator 12 is usually constituted by an integrator in the form of an operational amplifier, and it is necessary to use considerably complicated circuit for the purpose of compensating for the errors of the characteristics of electronic circuit components such as diodes and transistors, and the off-set voltage of the operational amplifier as well as temperature drift.

Moreover, it is not easy to adjust the inclination and linealrity of the sawtooth wave. Also, the analogue comparator 14 is generally constructed by an operational amplifier but this circuit is also difficult to adjust due to error of the characteristics of the circuit components.

Furthermore, the operation of the comparator is affected by a noise signal superposed upon the input signal. Accordingly, it is necessary to use a complicated circuit for overcoming these defects.

According to one embodiment of this invention there is provided a control system for a pulse width control type inverter made up of a plurality of switching elements, comprising a digital signal producing means for producing a digital signal indicative of a certain level, a reference pulse generator which generates reference pulses that determine the output frequency of the inverter, a clock pulse generator which generates clock pulses in synchronism with the reference pulses and having a frequency of an integer multiple of that of the reference pulses, a binary clock-pulse counter having a predetermined number of steps and connected to be cleared by the reference pulses and count up the clock pulses generated by the clock pulse generator, a digital comparator for comparing the output of the binary clock-pulse counter with the output of said means, an m step (m represents an integer) carry-pulse counter for counting the leading edges of the outputs of the digital comparator, means responsive to the leading edges of the outputs of the digital comparator and the output of said carry pulse counter for clearing the binary clock-pulse counter and repeating m times the counting up and clearing operations of the binary clock-pulse counter until the carry-pulse counter produces a carry pulse so as to use the interval between the generation of a reference signal and the generation of the carry pulse as a signal for determining the conduction period of the switching elements.

According to another embodiment of this invention the control system comprises a digital signal producing means for producing a digital signal indicative of a certain level, a reference pulse generator which generates reference pulses that determine the output frequency of the inverter, a clock pulse generator which generates clock pulses having a frequency of an integral multiple of that of said reference pulses in synchronism therewith; a presettable up down counter in which the output of said means is set as an initial value at the time of generating of said reference pulse and said clock pulses are counted up starting from said initial value, means responsive to a carry pulse generated by said up down counter for presetting again the output of said producing means in said up down counter as another initial value and for causing said up down counter to count up starting from said another initial value thereby repeating m (an integer) times said counting up operations, means for switching the operation of said up down counter to down counting operation after said m counting operations have been repeated until a shift down pulse is generated by said up down counter, means responsive to said shift down pulse for presetting again the output of said producing means in said up down counter for causing said up down counter to repeat (e-m > (t is an integer) times of counting down operation unitl a (f-m)th shift down pulse is generated, means for determining the conduction period of said switching elements to be equal to an interval between the m th carry pulse and the(f-m) th shift down pulse, and means responsive to the output of said up down counter for controlling said conduction period such that e=3m thereby keeping the phase of the output voltage of said inverter constant.

According to a further embodiment of the invention, the control system comprises digital signal producing means for producing a digital signal indicative of a certain level; a reference pulse generator which generates reference pulses that determine the output frequency of said inverter: a clock pulse generator which generates clock pulses in synchronism with said reference pulses and having a frequency of an integral multiple of that of said reference pulse, a presettable down counter responsive to the generation of the reference pulse for presetting the output of the means as an initial value and then counting down the same in response to the clock pulses generated by the clock pulse generator until a shift down pulse is produced, an m step (m represents an integer) carry-pulse counter connected to count the number of said shift down pulses, and means responsive to the output of the down counter and the output of said carry-pulse counter for clearing the down counter when it generates the shift down pulse to preset again the output of the producing means and repeating m times the counting down and the clearing operations of the down counter until the carry-pulse counter produces a carry pulse so as to use an interval between the generation of a reference pulse and the generation of the carry pulse as a signal for determining the conduction period of the switching elements.

Examples of the invention will now be described with reference to the accompanying drawings, in which: Figure I shows a basic construction of a pulse width control type inverter; Figure 2 is a block diagram showing one example of a prior art control system for an inverter of the pulse width control type; Figure 3A are waveforms useful to explain the operation of the control system shown in Figure 2; Figure 3B shows enlarged views of portions of the waveforms shown in Figure 3A for explaining the operation of the control system shown in Figure 2 when the DC voltage varies; Figure 4 is a block diagram showing one embodiment of the control system of a pulse width control type inverter embodying the invention; Figure 5A shows waveforms useful to explain the operation of the control system shown in Figure 4; Figure 5B shows enlarged views of certain portions of the waveforms shown in Figure 5; Figure 6 is a block diagram showing a modified embodiment of this invention; Figure 7A shows waveforms helpful to explain the operation of the modified embodiment shown in Figure 6; Figure 7B shows enlarged views of certain portions of the waveforms shown Figure 7A; Figure 8 is a block diagram showing another modification of this invention; Figure 9 show waveforms useful to explain the operation of the modification shown in Figure 8; and Figure 10 is a block diagram showing still further embodiment of this invention.

In a preferred embodiment of this invention shown in Figure 4, circuit elements corresponding to those shown in Figure 2 are designated by the same reference charactors.

In addition to those shown in Figure 2 there are provided a clock pulse generator 21 which generates a clock pulse having a frequency of an integer multiple of the frequency of the pulse generated by the reference pulse generator 11 in synchronism therewith, a n (an integer) bit binary up-counter which counts the number of the clock pulses generated by the clock pulse generator 21 for producing n bit binary code outputs, an A-D converter 23 which converts an analogue output signal of the constant voltage control circuit 13 into a digital signal in the form of a n bit binary code, a digital comparator 24 which compares the output of the up-counter 22 with the digital output of the A-D converter 23 for producing an output "1" or "0" in accordance with the relative magnitude of the inputs, a m (integer) step up-counter 25 which counts the change of the output of the digital comparator 24 from "0" to "1"j that is the building up edge of the output and a R.S. flip-flop circuit 26.

In Figure 5A, curves A through F show waveforms at points A through F shown in Figure 4 As above described the prior art control system comprises a sawtooth wave generator and an analogue comparator, whereas the control system of this invention is constituted by an A-D converter which converts the analogue output of the constant voltage control circuit into a n bit digital signal, a n bit binary up-counter, a digital comparator and a m step upwcounter. The A-D converter 23 which produces n bit outputs can represent 2n type states and it is constructed to produce (2n -1) codes of the digital output when the output of the constant voltage control circuit 13 is at a maximum where n and m are integers. At this time, the clock frequency of the clock pulse generator 13 is selected to be 2"xm times of the frequency of the reference pulse. The binary up-counter 22 is cleared by the output of an OR gate circuit 50 when a reference pulse is generated and then starts to count the number of clock pulses. The output of the up-counter 22 and the output of the A-D converter 23 which produces 2" types of digital signals are compared with each other by digital comparator 24 Where the output of the up-counter is larger than the output of the A-D converter the digital comparator 24 produces an "1" output, whereas where the output of the up-counter is smaller than the output of the A-D converter, the comparator produces a "0" output, and the output of the comparator 24 changes from "0' to "1" when the output of the counter 22 becomes larger than the output of the A-D converter 23 so that the OR gate circuit 50 is enabled to clear again the up-counter 22. As the same time, the building up edge which occurs when the output of comparator 24 changes from "0" to "1" is counted by m step up-counter 25. At the same time, when counter 22 is cleared the ouput of digital comparator 24 returns to "0" from "1" as shown by curve D in Figure 5 whereby the counter 22 begins to count up in a manner as above described. When the m step up-counter 25 counts m building up edges of the output of the digital comparator 24, the carry output of the counter 25 becomes "1" as shown by curve E. When the R.S. flip-flop circuit 26 which has been set by the output of the reference pulse generator 11 is reset by the carry output, the conduction period 6 is determined by the Q output of the flip-flop circuit as shown by curve F whereby an alternating current shown by curve G is produced. At this time, the counter 25 is cleared simultaneously with the reversal or reset of the flip-flop circuit so that the counter will not count until next reference pulse is applied. Denoting the number of outputs of the A-D converter 23 by P, the conduction period 6 would correspond to PXm clock pulses and the output voltage E shown by curve G would be controlled such that EXO is constant in the same manner as in the prior art.

By constructing the control system of the pulse width control type inverter with digital technique it is possible to improve the transient response of the control system for such external disturbance as variations in the DC voltage and load.

Figure SB is an enlarged view of certain portions of curves C and G shown in Figure 5A where the DC voltage varies rapidly in the embodiment shown in Figure 4. In Figure SB when the DC voltage varies according to curve G in a manner as has been already described in connection with Figure 3B, the output of the A-D converter 23 which converts the analogue output of the constant voltage control circuit 13 into a digital signal varies as shown by dotted lines of curve C and in response to this variation the control system produces a conduction period of 0 = + + 62 + - + om- Accordingly., the error in this case corresponds to the error caused by the deficient portion of the inclined portion of curve G 2 (AE1 X 431) +2(EE2 x 02) ±- -+(Em X (3m) However, the error is far smaller than the error shown by D-1 of Figure 3B .of the conventional control system, and can be reduced to a negligible value by increasing m. In other words, the control system of this invention can respond at a high speed to a rapid variation in the output of the -constadt voltage control circuit 13.

Since the control system of this invention utilizing digital technique is required to merely budge -';0" or "1 state of the signal it is not necessary to consider such factors as the offset voltage of the operational amplifier, and the errors of such electronic circuit -components as diodes and transistors which caused troubles in -the prior art control system utilizing an analogue circuit. Moreover, since the inclination angle of the curve passing through respective counts of the binary zrp-counter -is determined by the frequency of the clock pulse it is not necessary to adjust the inclination angle and linearity of the sawtooth wav.e shown in Figure 3A and also the digital comparator does not require any level adjustment as in .an analogue comparator. Since the accuracy of the linearity of the counts of the binary up-counter is determined to be 1/2"cm) by the ratio of the clock pulse frequency ,to the reference pulse frequency, it is possible to improve the accuracy by increasing the bit number n of the binary up-counter and the A-D converter or the step number m of the up-counter. Accordingly, it is possible to obtain sufficiently high accuracies by selecting 2"xm to be about several hundreds. With recent development of data transmission technique, the cost of the A-D converter has been greatly decreased and it becomes possible to fabricate a binary up-counter, a digital comparator and a multi-step up counter with one or two integrated circuits without using resistors, capacitors and diodes, thus obtaining an inexpensive control system having a simple construction yet extremely reliable.

Figure 6 shows a modified embodiment of this invention in which elements corresponding to those shown in Figure 4 are designated by the same reference characters. In this modification, there is provided a 2n step presettable down counter 31 in which the output of the A-D converter 23 is preset by the output of OR gate circuit 50 having inputs connected to receive the output of the reference pulse generator 11 and the shift down signal produced by the counter 31 and the initial value thus preset is counted down by the clock pulse generated by clock pulse generator 21. The operation of this modification can be understood from Figure 7A in which curve C shows the progress of counting of the down counter 31, the dotted lines thereof showing the output of the A-D converter 23. In this modification, the n bit binary up-counter and the digital comparator shown in Figure 4 were substituted by the 2n step presettable down counter 31. More particularly, at the same time when the R.S. flip-flop circuit 26 is set by the reference pulse A, the output of the A-D converter 23 is preset in the down counter 31 by the reference pulse and the initial value thus set is counted down by the clock pulse generated by the clock pulse generator as shown by curve C. Denoting the output of the A-D converter 23 by P, the initial value is sequencially counted down as P, P-1, P-2 ..., and when the count reaches zero, a shift down pulse is generated as shown by curve D which is counted by m step up-counter 25. In response to this shift down pulse and the reference pulse A, the OR gate circuit 50 applies a preset instruction to the down counter 31 thus causing it to preset again the output of the A-D converter 23 and then count down. Above described cycle of operation is repeated m times until m shift down pulses produced by the down counter 31 has been counted at which time a carry signal produced by the up-counter 25 becomes "1" as shown by curve E. This carry signal resets flip-flop circuit 26 so that the conduction period 6 becomes equal to (Pxm) clock pulses. In this modification too high transient response can be obtained for such external disturbances as the variations in the DC voltage and the load. Figure 7B is an enlarged view of certain portions of curves C and G shown in Figure 7A. The error in this case is the error caused by surplus portions -( < EI x 01)±21(AE2 x (32) +,.. +21(AErn X om) As has already been described with reference to Figure 5B this error can be decreased by increasing m.

With the construction shown in Figure 6, the down counter 31 too can be fabricated with only one or two down counters thus simplifying the circuit construction and increasing the reliability of the control system.

Although the foregoing description refers to a pulse width control type inverter as shown in Figure 1, the inverter may be of single phase or poly phase type and the invention is applicable to any type of inverter that can produce an AC output having a waveform close to a sinusoidal wave.

It should be understood that the combination of the constant voltage control circuit and the A-D converter can be substituted by such operation device as a micro-computer that produces digital signals.

In a modified embodiment shown in Figure 8, there are provided a reference pulse generator 121 which produces a reference pulse AS having a frequency of an integer multiple (in this embodiment twices) of the output frequency of the inverter, a clock pulse generator 122 which generates a clock pulse DS having a frequency of an integer multiple of the frequency of the reference pulse AS in synchronism therewith, R.S. flip-flop circuits 123 and 124, an OR gate circuit 125, a constant voltage control circuit 126 which generates an analogue signal having a level corresponding to the DC voltage, an A-D converter 127 which converts this analogue signal into a digital signal comprising a ,n (an integer) bit binary code, and a binary presettable up down counter 128 in which the output of the A-D converter 127 is preset by a preset signal produced by the OR gate circuit 125. The Q output ,of the flip-flop circuit 123 is applied to the up down counter 128 to cause it to count up or down the clock pulse DS generated by the clock pulse generator 122 starting from said preset initial value. The up down counter produces a carry signal during its counting up operation and a shift down signal during its counting down operation. Counter 129 counts up the output FS of the up down counter 128 to produce decimal code outputs 1, 2, ...m... 1 An at AND gate circuit 130 is provided having its inputs connected to receive the Q output of flip-flop circuit 123 and the Q output of flip-flop circuit 124. The output GS of AND gate circuit 130 is applied to a ring counter 131 which produces a pulse signal adapted to ON-OFF control the switching elements of the inverter according to a predetermined sequence. The output of the ring counter is applied to the inverter through an amplifier 132.

An overcurrent detector 33 is provided to detect the overcurrent condition on the output side of the inverter caused by a short circuit, for example, for supplying an instruction signal HS to the constant voltage control circuit 126 so as to rapidly decrease the output level thereof.

The operation of the control system shown in Figure 8 will now be described with reference to Figure 9 which shows various waveforms, in which curves AS through HS correspond to those shown in Figure 8. In curve ES, Ec shows the count of the up down counter 125 while dotted lines the levels of the digital outputs of the A-D comverter 127.

The n bit output of this converter can represent 2n types of the states. When the output of the constant voltage control circuit 126 is at a maximum, the digital output thereof has a code of (2"-1) and the frequency of the clock pulse DS is selected to be 2n x(f-m) times of the frequency of the reference pulse AS. The outputs of the counter 129 are applied to flip-flop circuits 123 and 124 to act as reset pulses at counts m and f respectively, where f = 3m. The up down counter 128 switches between counting up and counting down operations in response to the Q output of flip-flop circuit 123 and performs its counting operation only when the output of counter 129 and the Q output of flip-flop circuit 24 are "1" and is creared when these outputs are "0".

In response to the reference pulse AS (Figure 9A) produced by the reference pulse generator 121, both flip-flop circuits 123 and 124 are set. At the same time, the reference pulse AS is applied as a preset instruction to the up down counter 128 through the OR gate circuit 125 for presetting outputs E" E2 .... of the A-D converter 127 as initial values which are counted up by the clock pulse DS as shown in curve E, Figure 9. It is now assumed that the output of the A-D converter 127 is E1, then the clock pulse is counted up as E" (eel+ 1), (E,+2) .... .. . When the count reaches 2n a carry pulse FS is produced as shown by curve F.

The carry pulse FS is counted by counter 129 while at the same time is applied to the up down counter 128 via OR gate circuit 125 to act as a preset instruction. In this manner, the output of the A-D converter 127 is preset again in the counter 128 to begin the counting up operation. When this operation is repeated m times so that the counter 129 counts m carry signals FS produced by the up down counter 128 the counter 129 applies a reset pulse to the flip-flop circuit 123. At this time, the up down counter 128 is again preset with the output of the A-D converter A-D by being applied with a carry signal FS as a preset instruction. At this time, however, since the output of slip-flop circuit 123 is reversed to "0" from "1" as shown by curve B, whereby the up down counter begins to count down from the preset count as E,, (E, -1) E1 -2)... until the count is reduced to zero 2T3 = T1 + T2 = 2n+l m + E1 (t - 3m) Since it is selected that e = 3m 2T3 = T1 + T2. = 2n+l m which is constant independently of the output El, of the A-D converter 127. In other words, since at the end of TX, mth shift down pulse is generated and since this instant is always constant independently of the output of the A-D converter 127, the phase is maintained always at a constant value even when the conduction period H varies in response to the output of the A-D converter 127.

When the output current of the inverter becomes excessive due to short circuiting or the like, the over-current detector 133 rapidly lowers the output level of the constant voltage control circuit 126 thus rapidly decreasing the output of the A-D converter 127 to level E4 as shown by curve E, Figure 9 with the result that the period of producing the shift down pulse by the up down counter 128 which has been counting in accordance with output El of the A-D converter 127 is decreased greatly as shown by curve F. Accordingly, the conduction period 8 is greatly reduced as shown by curve J thus greatly decreasing the output voltage, and the output current which has been increasing is quickly limited below overload capacity K1 of the inverter as shown by curve K. The time at which the up down counter 128 produces m th carry pulse FS for determining the leading edge of the output as shown in Figure 9E varies in a range equal to the first half (in this example 900) of the period of the reference pulse AS in response to the output of the A-D converter 127, whereas the time at which the counter 129 produces (t - m)th shift down pulse for the purpose of determining the trailing edge of the output pulse GS can be freely varied within the period (in this example 1800) of the reference pulse AS so that it is possible to quickly limit the overcurrent. The error in the conduction period can be made negligibly small as in the preceeding embodiments.

In the circuit shown in Figure 8, although the output of the overcurrent detector 133 is applied to the constant voltage control circuit 126, this output is also applicable to a cleavable buffer circuit, not shown, provided on the digital output side of the A-D converter for decreasing the digital output or to an A-D cpmverter which can be cleared by the output of the overcurrent detector for decreasing the digital output level of such A-D converter.

In a modified circuit shown in Figure 10 instead of applying the output of the overcurrent detector 133 to A-D converter 127, the output is applied to the clock terminal of counter 129 via OR gate circuit 142. It is also possible to apply the output of the over-current detector to clearable buffer circ it not shown, to act as a clear signal to lower the level of the digital output or to use an A-D converter capable of clearing its digital output or to the A-D converter as a clear signal for lowering the level of its digital output.

WHAT WE CLAIM IS: 1. A control system for a pulse width control type inverter made up of a plurality of switching elements, comprising digital signal producing means for producing a digital signal indicative of a certain level; a reference pulse generator which generates reference pulses that determine the output frequency of said inverter; a clock pulse generator which generates clock pulses in synchronism with said reference pulses and having a frequency of an integral multiple of that of said reference pulses; a binary clock-pulse counter having a predetermined number of steps and connected to be cleared by said reference pulses and count up the clock pulses generated by said clock pulse generator; a digital comparator for comparing the output of said binary clock-pulse counter with the output of said means an m step (m represents an integer) carry-pulse counter for counting the leading edges of the outputs of said digital comparator, means responsive to the leading edges of the outputs of -said digital comparator and the output of said carry pulse counter for clearing said binary clock-pulse counter and repeating m times the counting up and clearing operations of said binary clock-pulse counter until said carry-pulse counter produces a carry pulse so as to use the interval between the generation of a said reference pulse and the generation of said carry pulse as a signal for determining the conduction period of said switching elements.

2. A control system for 'a pulse width control type inverter made up of a plurality of switching elements, comprising digital signal producing means for producing a digital signal indicative of a certain level; a reference pulse generator which generates reference pulses that determine the output frequency of said inverter: a clock pulse generator which generates clock pulses in synchronism with said reference pulses and having a frequency of an integral multiple of that of said reference pulses; a presettable down counter responsive to the generation of said reference pulse for presetting the output of said means as an initial value and then counting down the same in response to the clock pulses generated by said clock pulse generator until a shift down pulse is produced; an m step (m represents an

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **.

2T3 = T1 + T2 = 2n+l m + E1 (t - 3m) Since it is selected that e = 3m 2T3 = T1 + T2. = 2n+l m which is constant independently of the output El, of the A-D converter 127. In other words, since at the end of TX, mth shift down pulse is generated and since this instant is always constant independently of the output of the A-D converter 127, the phase is maintained always at a constant value even when the conduction period H varies in response to the output of the A-D converter 127.

When the output current of the inverter becomes excessive due to short circuiting or the like, the over-current detector 133 rapidly lowers the output level of the constant voltage control circuit 126 thus rapidly decreasing the output of the A-D converter 127 to level E4 as shown by curve E, Figure 9 with the result that the period of producing the shift down pulse by the up down counter 128 which has been counting in accordance with output El of the A-D converter 127 is decreased greatly as shown by curve F. Accordingly, the conduction period 8 is greatly reduced as shown by curve J thus greatly decreasing the output voltage, and the output current which has been increasing is quickly limited below overload capacity K1 of the inverter as shown by curve K. The time at which the up down counter 128 produces m th carry pulse FS for determining the leading edge of the output as shown in Figure 9E varies in a range equal to the first half (in this example 900) of the period of the reference pulse AS in response to the output of the A-D converter 127, whereas the time at which the counter 129 produces (t - m)th shift down pulse for the purpose of determining the trailing edge of the output pulse GS can be freely varied within the period (in this example 1800) of the reference pulse AS so that it is possible to quickly limit the overcurrent. The error in the conduction period can be made negligibly small as in the preceeding embodiments.

In the circuit shown in Figure 8, although the output of the overcurrent detector 133 is applied to the constant voltage control circuit 126, this output is also applicable to a cleavable buffer circuit, not shown, provided on the digital output side of the A-D converter for decreasing the digital output or to an A-D cpmverter which can be cleared by the output of the overcurrent detector for decreasing the digital output level of such A-D converter.

In a modified circuit shown in Figure 10 instead of applying the output of the overcurrent detector 133 to A-D converter 127, the output is applied to the clock terminal of counter

129 via OR gate circuit 142. It is also possible to apply the output of the over-current detector to clearable buffer circ it not shown, to act as a clear signal to lower the level of the digital output or to use an A-D converter capable of clearing its digital output or to the A-D converter as a clear signal for lowering the level of its digital output.

WHAT WE CLAIM IS: 1. A control system for a pulse width control type inverter made up of a plurality of switching elements, comprising digital signal producing means for producing a digital signal indicative of a certain level; a reference pulse generator which generates reference pulses that determine the output frequency of said inverter; a clock pulse generator which generates clock pulses in synchronism with said reference pulses and having a frequency of an integral multiple of that of said reference pulses; a binary clock-pulse counter having a predetermined number of steps and connected to be cleared by said reference pulses and count up the clock pulses generated by said clock pulse generator; a digital comparator for comparing the output of said binary clock-pulse counter with the output of said means an m step (m represents an integer) carry-pulse counter for counting the leading edges of the outputs of said digital comparator, means responsive to the leading edges of the outputs of -said digital comparator and the output of said carry pulse counter for clearing said binary clock-pulse counter and repeating m times the counting up and clearing operations of said binary clock-pulse counter until said carry-pulse counter produces a carry pulse so as to use the interval between the generation of a said reference pulse and the generation of said carry pulse as a signal for determining the conduction period of said switching elements.
2. A control system for 'a pulse width control type inverter made up of a plurality of switching elements, comprising digital signal producing means for producing a digital signal indicative of a certain level; a reference pulse generator which generates reference pulses that determine the output frequency of said inverter: a clock pulse generator which generates clock pulses in synchronism with said reference pulses and having a frequency of an integral multiple of that of said reference pulses; a presettable down counter responsive to the generation of said reference pulse for presetting the output of said means as an initial value and then counting down the same in response to the clock pulses generated by said clock pulse generator until a shift down pulse is produced; an m step (m represents an

integer) carry-pulse counter connected to count the number of said shift down pulses; and means responsive to the output of said down counter and the output of said carry-pulse counter for clearing said down counter when it generates said shift down pulse to preset again the output of said producing means and repeating m times the counting down and the clearing operations of said down counter until said carry-pulse counter produces a carry pulse so as to use the interval between the generation of a said reference pulse and the generation of said carry pulse as a signal for determining the conduction period of said switching elements.
3. The control system according to claim 1 wherein said last mentioned means comprises a flip-flop circuit which is connected to be set by said reference pulse and reset by the output of said clock-pulse counter, means for applying one output of said flip-flop circuit to ON-OFF control said switching elements, means for applying the other output of said flip-flop circuit to said clock-pulse counter for clearing the same, and an OR gate circuit having inputs connected to receive said reference pulse and the output of said digital comparator, and an output connected to said carry-pulse counter for clearing the same.
4. The control system according to claim 2 wherein said last mentioned means comprises a flip-flop circuit connected to be set by said reference pulse and reset by the output of said carry-pulse counter, means for applying one output of said flip-flop circuit to ON-OFF control said switching means, means for applying the other output of said flip-flop circuit to said carry-pulse counter for clearing the same, and an OR gate circuit connected to receive said reference pulse and a shift down pulse generated by said counter for presetting the output of said producing means in said down counter.
5. A control system of a pulse width control type inverter made up of a plurality of switching elements, comprising digital signal producing means for producing a digital signal indicative of a certain level; a reference pulse generator for generating reference pulses which determine the output frequency of said inverter; a clock pulse generator for generating clock pulses having a frequency of an integral multiple of that of said reference pulses in synchronism therewith; a presettable up down counter in which the output of said means is set as an initial value at the time of generating of said reference pulse and said clock pulses are counted up starting from said initial value, means responsive to a carry pulse generated by said up down counter for presetting again the output of said producing means in said up down counter as another initial value and for causing said up down counter to count up starting from said another initial value thereby repeating m (an integer) times said counting up operations, means for switching the operation of said up down counter to down counting operation after said m counting operations have been repeated until a shift down pulse is generated by said up down counter, means responsive to said shift down pulse for presetting again the output of said producing means in said up down counter for causing said up down counter to repeat (f-m) (e is an integer) times of counting down operation until a (e-m) th shift down pulse is generated, means for determining the conduction period of said switching elements to be equal to an interval between the m th carry pulse and the (e-m) th shift down pulse, and means responsive to the output of said up down counter for controlling said conduction period such that e = 3m thereby keeping the phase of the output voltage of said inverter constant.
6. The control system according to claim 5 which further comprises an overcurrent detector which detects an overcurrent of said inverter, and means responsive to the output of said overcurrent detector for decreasing the period of generating said shift down pulse of said up down counter thus shortening said conduction period.
7. The control system according to claim 6 wherein said last mentioned means comprises means for applying the output of said overcurrent detector to said constant voltage generating circuit for decreasing its output level.
8. The control system according to claim 6 wherein said last mentioned means comprises means for applying the output of said overcurrent detector to said producing means for decreasing the level of the output thereof.
9. The control system according to claim 5 which further comprises a counter connected to count the carry and shift down pulses produced by said up down counter for supplying reset signals to first and second flip-flop circuits at different counts, one output of one flip-flop circuit being applied to said up down counter for switching its operation between counting up and counting down operations.
10. The control system according to claim 9 wherein said means for determining the conduction period of said switching elements comprises an AND gate circuit having its inputs respectively connected to receive the outputs of said first and second flip-flop circuits.
11. The control system according to any one of the preceding claims wherein said digital signal producing means comprises a constant voltage control circuit for producing an analogue output and an A-D converter for converting said analogue output into a digital signal.
12. The control system according to any one claims 1 to 10 wherein said digital signal producing means comprises a microprocessor.
13. A control system substantially as herein described with reference to and as illustrated in Figures 4 and 5, Figures 6 and 7, Figures 8 and 9 or Figure 10 of the accompanying drawings.