JPS61284455A - Printing apparatus - Google Patents

Abstract

PURPOSE:To enable the use of the same character generator in the printing characters having different pitches and to reduce a printing position error, by generating printing timing signals at different pitches. CONSTITUTION:In the movement of a carriage, printing timing signal is outputted from an encoder at a fixed interval and used as a reference signal. a programmable frequency dividing circuit 50 divides the frequency of an encoder signal 7 to 1/N on the basis of the frequency dividing value signal 52 from a microprocessor for performing the main control of a printer. In the same way, a programmable frequency dividing circuit 51 divides the frequency of the output signal 56 of a voltage control type variable frequency oscillator 55 to 1/M on the basis of the frequency dividing value signal 52. The phase difference between frequency divided output signals 57, 58 is outputted as a pulse width signal 59 by a phase difference detector 53. A filter circuit 54 for converting the pulse width signal to an analogue voltage signal 60 is a low band-pass filter. The analogue voltage proportional to said phase difference is applied to the voltage control type variable frequency oscillator 55 and sent to a microprocessor for main control as a printing timing signal 56.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a serial dot printer device. [Prior Art] In recent years, with the increase in the number of dots constituting characters, it has become possible to obtain printing quality close to that of thick printing. Along with this, there is an increasing demand for printers with a wide variety of 7 onts and multi-ring character pitch, similar to thick printing printers.Generally, the printing pitch of serial dot printers is 10 characters/inch, but there is a need to improve printing quality. Accordingly, 12 characters/inch, which is used in thick print printers, and 15 characters/inch are required. A simple method is to have a number of character generators corresponding to the printing pitch, but this is expensive as it requires a large amount of memory for the character generators.

In addition, in order to change the printing pitch of conventional dots,
There are methods to obtain a print signal of a predetermined print pitch by setting the encoder pitch finely by comparing it with the actual print pitch and dividing the output print timing, and a method of setting a timer between several pulses of the print timing signal. The method used is to use and divide the data. However, these methods have disadvantages such as requiring an expensive high-resolution encoder, accumulating errors, and increasing the error in the printing pitch at the end of the divided section.◇ [Problems to be solved by the invention] ] The present invention overcomes these conventional drawbacks, and by generating printing timing signals at different pitches, the same character generator can be used to print characters with different pitches, and furthermore, printing position errors can be reduced. The purpose is to provide printing devices.

[Means for Solving the Problems] In order to overcome the above-mentioned drawbacks, the printing apparatus of the present invention employs a print timing generation circuit using a 7A locked loop. In general, a rotary encoder or a linear encoder is used to generate print timing. has been done. These encoders output print timing at fixed intervals when the carriage moves.The printing apparatus of the present invention uses the timing signal as a reference signal and at least first and twentieth frequency dividing means, phase difference detecting means, filter means,
The signal from the tJ & quasi-encoder is frequency-divided by the first frequency dividing means and inputted to the phase difference detecting means, and the output signal of the variable frequency oscillating means is divided by the second frequency dividing means. is frequency-divided and input to the phase difference detection means, and the phase difference signal of the output signals of the first and second frequency division means by the phase difference detection means is transmitted to the variable frequency oscillation means via the filter means. The apparatus includes a print timing control section that receives the input signal and uses the output signal of the variable frequency oscillation means as a print timing signal.

Furthermore, in order to improve the printing position accuracy, a 30th frequency dividing means for dividing the output signal of the variable frequency oscillator, a position counting means, and a position comparison means for comparing the reference value and the position counting means are provided. Microprocessor (MP)
Based on the detailed printing position data calculated in U), a reference value is set at an arbitrary position within the run-up section of the carriage of the printing device and where the output signal of the variable frequency oscillator is controlled in synchronization with the encoder signal. After passing through this reference value, set the frequency division ratio of the third frequency division means to the value calculated by the MPU for one frequency division interval, and then set the frequency division ratio to the value calculated by the MPU.
It is equipped with a print timing control section that is set to match the print pitch and uses this signal as a print timing signal.

Such a printing apparatus is particularly effective in a serial dot printing apparatus equipped with a carriage drive system whose speed is stably controlled.

An example of a printing device whose speed can be stably controlled is a seven-way speed droop type speed control system that uses a DC motor in the carriage drive system of the printing device and adds a frequency modulation type feedback loop of a reference oscillator consisting of a low-pass filter and a differential circuit. There is a printing device that includes a carriage control section that includes a control circuit and a mode selection circuit that switches the voltage applied to the DC motor, and in which the speed of the carriage drive system is controlled. Use and explain.

In the present invention, we devised a print timing generation circuit using a 7-Aze locked loop.The present invention will be explained using Fig. The encoder signal 7 is frequency-divided by - based on the frequency division value signal 52 from the processor. Similarly, the programmable frequency divider circuit 51 receives a frequency division value signal 52.
The output signal 56 of the voltage controlled variable frequency oscillator 55 is frequency-divided into i based on . Divided output signal゛57゜58
A phase difference detector 53 outputs the phase difference as a pulse width signal 59. 54 is a filter circuit for converting the pulse width signal into an analog voltage signal 60, and is a low-pass type filter. An analog voltage proportional to this phase difference is applied to a voltage controlled variable frequency oscillator 55 and sent to the main control microprocessor as a print timing signal 56.

The encoder signal 7 is output as the printer carriage moves, and the print timing signal is locked to the frequency i of the encoder signal frequency (M, N are integers) and follows the frequency change of the encoder signal. For example, when the print pitch of the encoder is set to 10 characters/inch, the value of i is set to 1 for 12 characters/inch and 1 for 15 characters/inch. Further, the bandwidth of the filter circuit 54 is set to be sufficiently larger than the response frequency of the carriage drive system, and is determined in consideration of the stability and tracking accuracy of the print timing circuit.

In general, the moving speed characteristics of the printer's carriage are expressed as shown in Figure 2 A. Here, 110 represents the frequency of the incremental reference encoder or the speed of the paper carriage, which is output in accordance with the carriage displacement. . The line 115 in the figure is the starting point of actual printing, and the carriage drive control system is designed so that the carriage speed falls within a predetermined error at this point. Here, the step input response characteristics of the print timing control circuit shown in Fig. 1 are expressed as
If the design is as shown in FIG. B111, the response to the carriage speed 110 will be as shown in FIG. 2 B115. In addition, the step input response characteristics of the print timing control circuit are shown in Figure 2B11.
12, the response to the carriage speed 110 is shown in FIG. 2E.

It will look like 114. Therefore, in order to obtain an accurate print timing signal at the print start position 115, it is necessary to make the response of the print timing circuit higher than the response of the carriage drive control system.
5 and later), the stability is lost and accurate printing timing signals cannot be obtained.

The response characteristics of the print timing circuit are determined based on the response characteristics of the carriage drive control system, the required print timing accuracy,
Is it not possible to make a general decision based on stability, etc.?In order to achieve print timing accuracy (pitch accuracy ±5%) when using the carriage drive control system described later,
It needs to be at least three times higher. The responsiveness of the print timing signal is determined by the frequency division numbers N and M, the voltage control station variable frequency oscillator range, and the time constant of the filter circuit.

For example, the print timing generation circuit can generate 12 characters/inch (
Taking M/N: 615) as an example, there are five types of phase lock states as shown in FIG. In FIG. 3, all signals are shown as edge differential signals for explanation. Assume that the reference encoder signal is A in the same figure. Figures B to F show five types of lock states. First, in state B, the reference encoder signal and print timing signal match at carriage position #P, and after 5 pulses of the reference encoder signal, 6 pulses of the print timing signal. The two pulses match again at the P+5 position of the pulse. A print timing signal is generated by sequentially repeating this process. In state C, they match at position P+1, match again at position P+6, and repeat this process. Further, in the D state, the positions P-1-2 and P+7 match, in the E state, the matches match at the P-1-3 and P+8 positions, and in the F state, P+4. A print timing signal is generated so as to coincide with the position P+9. Since the phase lock states B and IF are determined by the initial and transient states of the frequency divider circuits 50 and 51, it is not possible to arbitrarily specify which phase relationship between B and F. Therefore, although the printing timing signal can be divided accurately, an error of at most one standard encoder pulse occurs in the absolute position. In Fig. 3, it is assumed that the phase difference in the phase lock state, that is, the output signal 59 of the phase difference detector, is zero, but this is a value determined by the order of the filter circuit and the loop gain of the entire print timing generation circuit, and is actually is not necessarily zero.

In the present invention, the lock states of B and F can be specified arbitrarily, and a third frequency dividing means is added in order to obtain a more accurate print timing signal.

Next, this method will be explained using figures. FIG. 4 is an example of a timing diagram of this method, in which the division pitch of the print timing generation circuit is set as follows: the reference encoder signal is 10 characters/inch, the print timing signal is 12 characters/inch, or the frequency division number is M:6. This is an example when N:5 is set. FIG. 4A represents the reference encoder signal. By locking the phase difference between the print timing signal shown in Figure B and A to an arbitrary value in Figure 6B-7, a timing signal can be obtained at an accurate print position. By changing the frequency division number of the frequency circuit 51 from M to MXN, a print timing signal that is N times the reference encoder signal (N = 5 in this case) can be obtained as shown in Fig. 4G, and this G signal It is possible to consider a method in which the print control MPU distinguishes both the signals A and A, and extracts only the necessary print timing signals from the G signals.However, with this method, N times as many print timing signals Since the information is input to the control MPU, the processing becomes complicated and the processing throughput is significantly reduced.

Therefore, in the present invention, the third frequency divider is used to divide the print timing signal G, and by changing this frequency division number, the fourth
We devised a method to obtain the printing timing shown in Figure B and arbitrarily set the phase relationship between parentheses.

Next, the method will be described. FIG. 5 is a basic block diagram of this system. The part (■) in FIG. 5 has the same configuration and operation as in FIG. The output 120 of the controlled oscillator 55 is passed through a programmable frequency divider 121 to 1
/x is divided into 0. The frequency division ratio at this time is data line 12.
At this time, two values 1 /A and 1 /M are input to the frequency division data 1/x through the data bus 52 of the MPH.

As the value of 1/x, select either 1/A or 17M. To switch the selection value, use the output 1 of 7 lip 70 knob 123.
This method is performed by inputting the set signal 124 of the flip-flop at an arbitrary reference encoder position, so that the 7 lip and 70 knob are set.
The frequency division ratio is set to 1/A. After this, when the output pulse G of the variable voltage control oscillator 55 in FIG. Switching, frequency dividing circuit 121
The 0 frequency division ratio is switched from 1/A to 1/H, and from then on, the print timing signal 56 is output every N pulses of the 4th G. FIG. 4H shows the output of the print timing signal 56 and the output 120 of the variable voltage controlled oscillator 55 at this time. In this example, N=5, M=6, and A=4, indicating that this circuit is operated from the reference encoder position P-1-2. Although the explanation has been made so far, the value of H does not necessarily have to be this value, and by setting it to an integral multiple of H, it is possible to more finely correct the position of the print timing signal.

Next, a method of calculating the value of the frequency division value 1/A will be described. The print start position is calculated based on the count value P of the reference encoder signal. 'Generally, the pitch of the reference encoder is 10
Determine the minimum spacing between dots in character/inch printing. Here, the explanation will be given assuming that the pitch of the reference encoder signal is determined as described above. First, determine the values of M and H to obtain the predetermined printing pitch.Next, convert the printing start position to the predetermined printing pitch, and set this value as R.This value is used as the count value of the reference encoder. Convert ◎ P=RX-; Here, P is the print start position with the reference encoder as a reference.

Since the value of P calculated in the above equation is not necessarily an integer value, the printing position cannot be determined accurately.

P' = nt(Rx); nt1(,) means cutting off the decimal part of the calculation in parentheses.

Execute the calculation in the above equation to find the integer part of the value of P.

As is clear from FIG. 4, in the locked state, the value of the print timing signal before frequency division is M times the output of the reference encoder signal. Therefore, in order to convert to this signal, the value of the decimal part P'p' = (RX-) - F' of the above calculation is multiplied by M and converted into an integer. This value becomes the frequency division number A (0A-1(RX-)-F')XM To simplify the calculation procedure a little more, first, the value of R is multiplied by N. Next, this value is divided by M, but at this time, integer division is performed and the result is P', and the remainder is the value of the person. When the value of the reference encoder becomes P', the programmable frequency divider 121
By setting the frequency division number to 1/A and then switching to 1/H by the first output of the print timing signal 56, print timing can be obtained at a predetermined position. The above calculation is a calculation method when the reference encoder prints in the increasing direction, but in bidirectional printing, when the reference encoder counts are printed in the decreasing direction, 1 is added to the value of P' mentioned above. The value of O or A to be P' can be realized by setting the above-mentioned remainder A as A'=M-A and setting 1/A' at the position of P' in the same way as above. Also, at this time, P′, P”, A,
By adding an appropriate offset amount to the value of A', it is possible to correct printing deviation in bidirectional printing.

Next, this circuit will be explained in more detail.

Figure 6 shows all the elements of the print timing circuit of the present invention.
A direction determining circuit 219 determines whether the phase of the reference encoder signal (B phase) differs by 90 degrees from that of the reference encoder signal (human face) 7 is advanced or delayed, and the position counter 221 performs addition or subtraction. This value becomes the value of P ◇The counted value 222 of this counter is sent to the position comparator 223 and compared with the reference value 224 sent from the MPU, the reference value latch 2
Reference numeral 25 temporarily stores data sent from the MPU through the data bus 52.
' is stored and output as a reference value 224. on the other hand,
The positional force controller 226 temporarily stores the counted value 222 of the position counter 221 at the request of the MPH and outputs it to the data bus 522, thereby enabling the MPU to read the carriage position of the printer.

The data latch 200 temporarily stores the frequency division value (N) from the MPU and outputs it to the frequency divider 50 as a frequency division value signal 200. Further, the data latch 202 temporarily stores the frequency division value (v, X x *) from the MPU, and outputs this value to the frequency divider 51 as a frequency division value signal 206 . The data controller Sochi 216 temporarily stores the frequency division value (A or A' and N) from the MPU, outputs it as a frequency division value signal 215 to the frequency division value selection circuit 122, and in the frequency division value selection circuit, A Alternatively, the value of A' and the value of N are switched and output as a frequency division value 125 to the frequency division circuit 121.

The address decoder 209 uses the MPU address signal 210
and R/W signal 211, select signal 204 for each latch
~208 is output, and numerical values are exchanged between the MPU and each data latch.

On the other hand, the signal of the position comparator 223 is the position count value 222 (P
A coincidence signal (p=u) 124, a mismatch signal (P>R) 227, and a mismatch signal (P<R) 228 are output between the position reference value 224 (assumed as R) and the position reference value 224 (assumed as R). These three signals and the carriage movement direction signal (R/L signal) are selected by the gate circuit 214, and the print timing signal 212 is selected after the position reference value among the print timing signals 56 generated.
output to the MPU as At this time, the gate signal is
Then, a print timing output signal 211 is outputted as shown in FIG.

The operations of other elements are the same as those described above, so their description will be omitted.

Note that the filter circuit 54 may be a high-order filter.

Integrating circuits are also a type of low-pass filter.

Furthermore, in FIG. 6, the two input signals 57 of the phase comparator 56
．． The dividing ratios of the divider 50 and 51 connected to the divider 58 are respectively 1/N and 1/(NxM), but this value is the common value 1
I have /N. Therefore, it is possible to erase the value of 1/H from both peaks, but the frequency division ratios when erased are 1 and 17N, respectively. A frequency division ratio of 1 means that the frequency is not divided, so the frequency divider 50 can be omitted. This block diagram is shown in FIG. The operations, components, etc. are the same as those in FIG. 7, so their description will be omitted.

Further, in the embodiment, the voltage-controlled control circuit 55 is used, but the circuit 55. It is also possible to make the filter circuit 54 and the phase difference detector 53 numerically controlled, and to perform all phase difference detection etc. by digital numerical control.

Next, we will discuss the carriage drive control system. In the print timing generation circuit of the present invention, if the carriage running system does not operate stably without fluctuation, the specified design accuracy cannot be obtained.Therefore, a DC motor is used in the carriage drive system of serial dot printing. Phase control is achieved using a low-cost, high-performance, high-precision carriage control device and fixed-interval print timing signals generated as the carriage moves.
A locked loop control system generates printing timing at arbitrary intervals, making it possible to print arbitrary character pitches using the same character generator. It is best to configure a serial dot printer consisting of a print timing generation circuit.10 Therefore, for the carriage and carriage drive system using a DC motor, this carriage control device can be improved by adding a simple circuit without reducing the loop gain. Figure 9 is a professional diagram of this system, which employs a system that improves stability and suppresses oscillation.

The phase difference signal 8 detected by the phase comparator 2 is converted into an analog speed signal 11 via a low-pass filter 9, and further converted into a pseudo acceleration signal 12 by a differentiating circuit 10. This signal 12 frequency-modulates the output signal of the reference oscillator 1. This control system achieves the same effect as adding an acceleration feedback loop to a speed control device composed of analog circuits, and is a 7-speed locked loop. It has the effect of improving stability without compromising the quick response and high precision of the control system. FIG. 10(a) shows the response 16 of the 7-axis lock droop control device shown in FIG. 8, and FIG. 10(6) shows the response 17 of the control device of the type shown in FIG. 18 in the figure indicates a set speed, and shows a state where a signal of set speed 18 is applied from a stopped state at time 0.

In the carriage control of a serial printer, the actual printing speed can be improved by skipping non-printing sections at high speed or moving at high speed to the next printing start position after printing one line.

In view of the above points, the present invention provides a method for improving responsiveness when reducing the set speed using a simple circuit without adding a special mechanical brake device.
This embodiment will be explained using the block diagram shown in FIG. 1st
Figure 1 shows the system shown in Figure 9 with a mode selection circuit 19 added. 24 is a reference oscillator 10. The set speed is changed by a manual signal that changes the frequency. When a certain set speed signal 24 is input, the output frequency of the oscillator 1 is changed. 6 changes. At this time,
When the input set speed is larger than the set speed before changing, the phase detector 20 phase advance signal 8 (when the phase of the oscillator output signal is ahead compared to the encoder output signal 7) is output. It is applied to the motor 4 via the mode selection circuit 19 and the driver circuit 3 to increase the speed.

The control method is the same as that shown in FIG. On the other hand, when the input set speed signal 24 is smaller than the previous set speed, a speed reduction signal 25 is applied to the brake flip-flop 23 at the same time as the set speed signal 24 changes.
Set 0 knob 23. The mode selection circuit 19 switches the control signal to the phase delayed signal 22 (when the phase of the oscillator output signal is delayed compared to the encoder output signal 7) by the output signal 21 of the flip 70 knob 23, and further changes the current direction. Outputs to driver 3 and applies the brakes.

When the motor speed decreases below the set speed, the phase lead signal 8 is output, so the brake flip 70 knob 2'
5 is reset and the mode selection circuit 19 is switched to return to the control operation before braking. This control circuit applies reverse energization to the brakes during deceleration, providing the same level of responsiveness as during acceleration.

FIG. 12 shows an example of the response when the set speed is changed. When the set speed 24 is changed from 0 to the value shown in 28 at time 0 31, the speed of this control device changes from 0 to 30 as shown in 26.
When the set speed 24 is further increased to a value of 27 at time 32, the speed 26 increases to a value of 29. Conversely, when the set speed 24 is decreased to the original value of 28 at time 33, the speed 26 is decelerated to the value of 60.The broken line shown at 034 shows the speed characteristics when this circuit is not added.

FIG. 16 shows a specific diagram of the embodiment shown in the 11th FA. ◇101 is an integrated circuit capable of frequency modulation with the acceleration signal 12, and its output signal 68 is programmably divided into a frequency according to the speed setting signal 24. A phase difference detector 2 detects the phase of the output signal 6 and the encoder signal 7. 39 is a circuit called a charge/discharge pump, and a low-pass filter 9 composed of this and an operational amplifier 40,
The phase difference signal is converted into an analog speed signal 11, and further converted into an acceleration signal 12 by a differentiating circuit 10. The portion within the dotted line 47 is built into a commercially available integrated circuit for controlling the 7A locked loop. On the other hand 65
The signal 13 in FIG. 11 determines the advancing direction of the carriage. This signal and the output signal 21 of the brake 7-lip prop 23 cause a circuit that switches between the phase lead signal 8 and the phase lag signal 22 to select the mode. The output 20 of the 0 mode selection circuit 19, which is the selection circuit 19, changes the direction and time of energization of the motor 4 by the switching type driver 3 made up of four transistors. 36 is a current limiting circuit for controlling the large current that flows when the motor is reversely energized and when starting up, and is useful when a DC motor is used in equipment that frequently starts, stops, and reverses, such as the carriage drive system of a serial printer. Prevent significant reduction in service life.

The bandwidth of the low-pass filter 9 is determined by the resistor 44 and the :2 capacitor 43, but this value is sufficiently lower than the frequency of the encoder signal corresponding to the set speed, and is equal to the natural frequency of the control system obtained by actual measurement or calculation. The resistor 42 and resistor 44 are selected to have a sufficiently small value compared to the resistor 42 and resistor 44, which perform high-frequency correction of the low-pass filter (02), which is set to a bandwidth that allows sufficient passage. Further, the ratio between the resistor 41 and the resistor 44 becomes an adjustment parameter for the damping ratio of this control system. Further, a time constant is determined by the product of the resistor 45 and capacitor 46 of the differentiating circuit 10, and this value is set to a value that has a differential effect on the natural frequency of the control system.

Note that in the present invention, "printing" refers to characters.

It is a broad concept that includes numbers, figures, etc. You can use RAM instead of a character generator to dump and print characters and graphic patterns in RAM. The 0 head may be one bin or multiple bins such as 9, 24, 32, etc. The bins may be aligned in a direction that intersects the printing direction.In addition to wire tod type printing devices, printing devices such as thermal type, thermal transfer type, or inkjet type such as on-demand type may be used. It's okay. In this case, the above-mentioned "bottle" may be replaced with "electrode".

Also, the head may have multiple bins or 1! in the direction crossing the printing direction. When poles are mounted, by changing the inclination of the head in the perpendicular direction to the recording paper, it is possible to change the pitch of the dots that make up the character in the printing direction and at the same time change the height of the character. This can also be done by changing the angle between the direction in which the head's bins (or electrodes) are aligned and the printing direction, but in this case, pay attention to the timing of printing the dots and adjust the printing timing to match each dot row. You need to speed it up or slow it down.

〔Effect of the invention〕

In this manner, the printing apparatus of the present invention generates printing timing at different pitches, thereby making it possible to use character patterns stored in the same character generator for characters with different pitches, and further, The printing position error is also small.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a PLL type print timing generation circuit. FIG. 2 is a diagram showing the response of the carriage drive system and the PLL print timing generation/main circuit. FIG. 3 is an explanatory diagram showing the phase relationship between the encoder signal and the print timing signal. FIG. 4 is a timing diagram showing the relationship between the output signal of the print timing circuit including the third frequency divider and the carriage position. FIG. 5 is an explanatory block diagram of a print timing circuit including a third frequency divider. FIG. 6 is a block diagram explaining FIG. 5 in more detail, and FIG. 7 is a block diagram of a type in which one frequency divider is omitted. Figure 8 is a block diagram of a conventional 7A locked loop control device, in which 13 is the printer carriage, 14 is the belt boot IJ, and 15 is the printing paper.0 Figure 9 is the acceleration feedback to the 7A locked loop control device. Figure 10 is a block diagram of the control device when a loop is added. Figure 10 shows response example 16 of the conventional 7-speed locked loop control device shown in Figure 8, and a control device with an acceleration feedback loop added as shown in Figure 9. FIG. 12 is a diagram comparing response example 17. FIG. 11 shows a block diagram of the carriage control device of the present invention. FIG. 12 shows an example of the response of the carriage control device of the present invention and the state of each signal at this time. FIG. 13 is a circuit diagram embodiment of the carriage control device of the printer device of the present invention shown in FIG. Figure 1 Figure 2 Figure 2

Claims (1)

[Claims] 1. Consisting of at least first and second frequency dividing means, a phase difference detecting means, a filter means, and a variable frequency oscillating means, the signal of the reference encoder is frequency-divided by the first frequency dividing means and sent to the phase difference detecting means. The output signal of the variable frequency oscillation means is frequency-divided by the second frequency division means and inputted to the phase difference detection means, and the output signal of the first and second frequency division means is frequency-divided by the second frequency division means and inputted to the phase difference detection means. a print timing control section for inputting a phase difference signal of the output signal to the variable frequency oscillation means via the filter means and for making the output signal of the variable frequency oscillation means a print timing signal; and a third frequency dividing means. and a position counting means, a position comparison means for comparing a reference value and the position counting means, and the output signal of the variable frequency oscillation means is divided by the second frequency dividing means and the third frequency dividing means. constituting a surrounding means,
A printing apparatus characterized in that the printing apparatus is further equipped with a function of switching the frequency division ratio to an arbitrary value using an output signal from the position comparison means.