JPH0773927B2 - Print timing signal generator for serial printer - Google Patents

Description

The present invention relates to print timing generation for a serial printer.

(Prior Art) With a serial dot printer that forms and prints characters using a dot matrix, due to advances in high-density printing head technology, it is now possible to obtain print quality close to that of mother-size printing.
Along with that, printing with a variety of fonts and a variety of character pitches, which is the same as the mother-printing type printer, is required. For example,
Generally, the printing pitch of a serial dot printer is 10 characters /
Although the inch type is used, the 12 character / inch type and the 15 character / inch type used in the mother-size printing type printer are required.

As a method for realizing this, there is a method having a number of character generators corresponding to the print pitch, but the memory for the character generators has a large capacity and becomes expensive. Therefore, it is considered to use the same character generator for characters with different pitches by generating print timings with different pitches. As the method, a timing signal generated in synchronization with the movement of the carriage is generated by a rotary encoder and the print timing is obtained by dividing the output timing signal, or the timing signals are divided using a timer. Then, a method for obtaining a print timing signal is adopted.

However, since the former method requires an expensive high-resolution encoder and frequency division, the print timing signal can only be generated at intervals that are an integral multiple of the encoder signal interval, and the latter method must also be divided equally. If the interval of the last divided section is incorrect, the print timing signal can be generated only at an interval that is an integer fraction of the encoder signal interval, and as a result, the printable character size is limited, and the same character generator can be used. I couldn't print it in any size.

(Problems to be Solved by the Invention) The present invention has been made in view of such problems,
The purpose is to generate a print timing at an arbitrary equal pitch from a timing signal output along with the movement of a predetermined distance of a carriage, and use the same character generator to print a serial printer capable of printing in any size. To provide a print timing signal generator.

(Means for Solving the Problems) A print timing signal generation device for a serial printer according to the present invention is a timing signal output when a carriage equipped with a print head is moved in a print digit direction and the carriage moves a predetermined distance. In a print timing signal generation device for a serial printer that generates a print timing signal based on the above, a first frequency dividing circuit that divides the timing pulse and a pulse signal from the first frequency dividing circuit are input to one side. A phase difference detection circuit that detects the phase difference between the two pulse signals, a filter circuit that removes high frequency components from the output of the phase difference detection circuit, and an oscillation frequency is modulated by the output from the filter circuit, and the print An oscillation circuit for generating a timing signal and a second frequency divider for dividing the print timing signal
And the pulse signal from the second frequency dividing circuit is input to the other of the phase difference detecting circuits.

(Embodiment) A serial dot printer equipped with a print timing signal generator of the present invention uses a DC motor as a drive system for a carriage. In order to perform high-quality printing, the running property of the carriage affects, so this drive system will be described.

FIG. 1 shows a basic block diagram of a conventional carriage drive system. It shows a reference speed pulse 6 oscillated by a reference oscillator 1 and a pulse train signal corresponding to a speed generated from an encoder 5 attached to a motor 4. The phase difference is detected by the phase comparator 2, and the pulse signal 8 whose duty changes according to the phase difference is transmitted through the switching circuit 3 to the motor 4
To control the speed. The characteristic of this control system is that the accuracy of the speed is determined by the reference oscillator 1, so that extremely high accuracy is obtained, and the heat of the switching circuit 3 and the motor 4 is small. Since it is high and cannot be changed easily, it has a drawback that it easily causes oscillation and its stability is poor.
Particularly, in the carriage control of a serial printer that requires a high-speed response, the frictional load and the inertial load are both designed to be smaller than the output of the motor 4, so that this drawback becomes conspicuous.

Therefore, the applicant disclosed in Japanese Patent Laid-Open No. 58-59876 a carriage control which improves stability and suppresses oscillation by adding a simple circuit without lowering loop gain. FIG. 2 is a block diagram of this system. The phase difference signal 8 detected by the phase comparator 2 is converted into an analog signal through the low pass filter 9, and further converted into a pseudo acceleration signal 12 by the differentiating circuit 10. The pseudo acceleration signal 12 frequency-modulates the output signal of the reference oscillator 1. This control system achieves the same effect as adding an acceleration feedback loop to the speed control device composed of analog circuits, and does not reduce the responsiveness and high accuracy of the phase locked loop type control device. Has the effect of improving stability. Third
The figure shows this effect. The response 16 of the conventional phase-locked loop controller shown in FIG.
The response 17 of the control device of the system shown in FIG. 2 is shown in FIG.

By the way, in the carriage control of the serial printer, the throughput can be improved by skipping the non-printing section at high speed or moving to the next print start position at high speed after the completion of printing one line. FIG. 4 is a block diagram of a carriage control system aiming at improving the above-mentioned throughput, in which a mode selection circuit 19 is added to the control system of FIG. Reference numeral 24 is an input signal for changing the frequency of the reference oscillator 1. When the set speed signal 24 is input, the output frequency 6 of the oscillator 1 changes, and the set speed is changed. At this time, if the input set speed is faster than the set speed before the change,
Phase lead signal 8 of phase detector 2 (encoder output signal 7
Is output when the phase of the oscillator output signal is advanced), and this signal is applied to the motor 4 via the mode selection circuit 19 and the driver circuit 3 to increase the speed. On the other hand, when the input set speed signal 24 is slower than the previous set speed, the brake flip-flop 23 is set by the speed decrease signal 25 at the same time when the set speed signal 24 changes. The output signal 21 of the flip-flop 23 switches the input of the mode selection circuit 19 to the phase delay signal 22 (when the phase of the oscillator output signal is delayed as compared with the encoder output signal 7), and further changes the energizing direction to change the driver 3 Output to brake. When the speed of the motor 4 falls below the set speed, the phase advance signal 8 is output, so the brake flip-flop 23 is reset and the input of the mode selection circuit 19 is switched to the phase advance signal 8 to return to the control operation before braking. . In this control circuit, the brake of reverse energization is added during deceleration,
The same responsiveness as when accelerating is obtained. FIG. 5 shows an example of the response when the set speed is changed. When the set speed signal 24 is changed from the value 0 to the value 28 shown at time 31, the speed of this control device becomes 0 as shown in 26. To 30 to increase the set speed signal 24 to a value of 27 at time 32, the speed 26 increases to a value of 29. Conversely, when the set speed signal 24 is decreased to the original value of 28 at the time 33, the speed 26 is decelerated to the value of 30. The wavy line indicated by 34 in the figure shows the speed characteristic when this circuit is not added.

FIG. 6 is a diagram showing a specific circuit configuration of the block diagram shown in FIG. 4. Reference numeral 101 is an IC capable of frequency modulation with the acceleration signal 12, and its output signal 38 is output in accordance with the speed setting signal 24. The frequency is divided by the programmable frequency divider 37, and the phases of the output signal 6 and the encoder signal 7 are detected by the phase difference detector 2. Reference numeral 39 is a circuit called a charge / discharge pump, which converts a phase difference signal into an analog speed signal 11 by a low-pass filter 9 composed of this and an operational amplifier 40, and further converts it into a pseudo acceleration signal 12 by a differentiating circuit 10. . The code
The inside of the wavy line of 47 is the part built in the commercially available IC for phase-locked loop control. A signal 35 is a signal that determines the traveling direction of the carriage 13, and a mode selection circuit 19 is a circuit that switches between the phase advance signal 8 and the phase delay signal 22 by this signal 35 and the output signal 21 of the brake flip-flop 23. By the output 20 of the mode selection circuit 19,
The direction and time for energizing the motor 4 are changed by the switching driver 3 composed of four transistors. Reference numeral 36 is a current limiting circuit for controlling a large current flowing when the motor 4 is reversely energized and started. When the DC motor is used in a device such as a carry drive system of a serial printer, in which start, stop and reverse rotation are frequently repeated. , Prevents a significant decrease in motor life.

The bandwidth of the low-pass filter 9 is the resistance 44 and the capacitor.
43, this value is sufficiently lower than the frequency of the encoder signal 7 corresponding to the set speed, and the natural frequency of the control system obtained by actual measurement or calculation is set to a value that allows sufficient passage. A resistor for high-frequency correction of the low-pass filter 9.
The value of 42 is selected to be sufficiently smaller than that of the resistor 44. Also, the resistor 41
The ratio of the resistor 44 and the resistor 44 is the adjustment parameter for the damping ratio of this control system. Also, the resistor 45 and the capacitor 46 of the differentiating circuit 10
The time constant is determined by the product of, and this value is set to have a differential effect on the natural frequency of the control system.

By configuring the carriage drive system as described above, it is possible to drive the carriage with less vibration and high speed stability and quick response.

The print timing signal generating device of the present invention mounted on a serial printer which is a carriage drive system having such high speed stability and quick response will be described below. FIG. 7 is a block diagram of a circuit for generating the print timing signal of the present invention. In the figure, reference numeral 50 is a programmable frequency dividing circuit, and data (N) for dividing the encoder signal 7 into 1 / N is inputted from a microcomputer controlling the main control of the printer via a data bus 52. Similarly, data (M) for dividing a signal 56 from a voltage control type variable frequency converter 55, which will be described later, into 1 / M is input to the programmable frequency dividing circuit 51 via a data bus 52. The signals 57 and 58 from the program frequency dividing circuits 50 and 51 are input to the phase difference detector 53, and the phase difference detector 53 outputs a pulse width signal 59 having a width corresponding to the phase difference.
Is output.

Reference numeral 54 is a low-pass filter circuit for converting the pulse width signal 59 into the analog voltage signal 60, which outputs the analog voltage signal 60 proportional to the phase difference between the signals 57 and 58, and receives the analog voltage signal 60 to control the voltage. The oscillation frequency of the frequency oscillator 55 is modulated and sent as a print timing signal 56 to a print controller (not shown).

In the print timing signal generation circuit shown in FIG. 7, feedback control is applied so that the frequencies of the signal 57 and the signal 58 are equal. Therefore, in the locked state, the frequency of the encoder signal 7 is ENC and the frequency of the print timing signal 56 is PTS. Then, it locks in the frequency state shown by the relational expression of ENC / N = PTS / M.

That is, since the frequency PTS of the print timing signal 56 follows the frequency ENC of the encoder signal 7 by M / N times (M and N are integers), the values of N and M to be written in the program frequency dividers 51 and 52 can be appropriately selected. For example, the print timing signal 56 can be generated at any pitch. The M / N value is set to 6/5 for printing 12 characters / inch and 3 for printing 15 characters / inch, for example, when the carriage movement amount per encoder cycle is set to 10 characters / inch. You can set it to / 2. The bandwidth of the low-pass filter 54 is at least twice as high as the response frequency of the carriage drive system, and is determined in consideration of the stability and tracking of the circuit.

In the embodiment, the case where the carriage drive system is driven by the DC motor is shown, but the present invention can be used regardless of the configuration of the carriage drive system.

(Effects of the Invention) As described above, according to the present invention, by setting the frequency division ratio (N, M) of the two program frequency dividers from the microcomputer, it is generated in synchronization with the predetermined distance movement of the carriage. A print timing signal having a frequency M / N times that of the timing pulse can be obtained, and the print timing signal can be generated with arbitrary resolution by appropriately selecting the values of M and N. Therefore, the same character generator can be used to print characters of various sizes.

[Brief description of drawings]

FIG. 1 is a block diagram showing a conventional carriage drive control device using a phase locked loop, in which 13 is a carriage, 14 is a belt pulley, and 15 is a printing paper. FIG. 2 is a block diagram showing a carriage drive control device in which an acceleration feedback loop is added to the phase locked loop of FIG. 3 (a) is a diagram showing the response of the phase-locked loop of FIG. 1, and FIG. 3 (b) is a diagram showing the response of the phase-locked loop of FIG. FIG. 4 is a block diagram of a carriage drive device obtained by further improving the carriage control device shown in FIG. FIG. 5 is a diagram showing the responsiveness of the carriage drive device shown in FIG. 4 and the signal states at this time. FIG. 6 is a detailed circuit diagram of the carriage driving device shown in FIG. FIG. 7 is a block diagram of a print timing signal generator for a serial printer according to the present invention.

Claims (1)

[Claims] 1. A print timing signal generator for a serial printer, which moves a carriage equipped with a print head in a print digit direction, and generates a print timing signal based on a timing signal output when the carriage moves a predetermined distance. In the device, a first frequency dividing circuit that divides the timing pulse, and a phase difference detection circuit that detects the phase difference between the two pulse signals with one input of the pulse signal from the first frequency dividing circuit. A filter circuit that removes high frequency components from the output of the phase difference detection circuit; an oscillator circuit that modulates an oscillation frequency with the output from the filter circuit to generate the print timing signal; and a frequency divider that divides the print timing signal. Second frequency divider circuit and serial printer printing in which the pulse signal from the second frequency divider circuit is input to the other of the phase difference detection circuits Timing signal generating device.