JPS6223763A - Printer - Google Patents

Abstract

PURPOSE:To reduce the error of printing positions as well as enable the same character generators to be used for letter printing of different pitches by generating print timing signals with different pitches. CONSTITUTION:A programmable dividing circuit 50 divides encoder signals 7 into 1/N on the basis of dividing value signals from a microprocessor. A programmable dividing circuit 51 divides output signals 56 from a voltage control type variable frequency generator 55 into 1/M on the basis of the signal 52. A phase difference between divided output signals 57 and 58 is output as a pulse width signal 59 by a phase difference detector 53. An analog voltage proportional to the phase difference is applied to the generator 55 and sent out as a print timing signal 56 to the main control microprocessor. In this way, letter patterns stored in the same character generators can be used for letters of different pitches.

Description

[Detailed description of the invention] 〔Technical field〕 The present invention relates to a serial dot printer device.

[Prior art]

In recent years, with the increase in the number of dots that make up characters, it has become possible to obtain print quality close to that of matrix printing, and along with this, there has been an increasing demand for printers with a variety of fonts and character pitches similar to matrix printing printers.

Generally, the printing pitch of serial dot printers is 10 characters/inch, but as printing quality has improved, the printing pitch has changed to 12 characters/inch, which is used in matrix type printers, and 15 characters/inch. something is required. A simple method is to have a number of character generators corresponding to the printing pitch, but this is expensive as it requires a large amount of memory for the character generators.

In addition, in order to change the printing pitch of conventional dots,
There are methods to obtain a print signal of a predetermined print pitch by setting the encoder pitch finely by comparing it with the actual print pitch and dividing the output print timing, and a method of setting a timer between several pulses of the print timing signal. The method used is to use and divide the data. However, these methods require an expensive high-resolution encoder, accumulate errors, and have the disadvantage that the error in the printing pitch at the end of the divided section becomes large.

[Problem that the invention seeks to solve]

The present invention overcomes such drawbacks of the conventional art, and by generating printing timing signals at different pitches, the same character generator can be used to print characters with different pitches, and furthermore, printing position errors can be reduced. The purpose is to provide equipment.

[Means for solving problems]

In order to overcome the above drawbacks, the printing apparatus of the present invention employs a print timing generation circuit based on a 7A locked loop.

Generally, a rotary encoder or a linear encoder is used to generate print timing. These encoders output print timing at fixed intervals when the carriage moves. The printing apparatus of the present invention uses such a timing signal as a reference signal. and at least first and second frequency dividing means, phase difference detection means, filter means,
It consists of variable frequency oscillation means, and is inputted to the first frequency dividing means (1 + e sleeve, l - 1 - 7 y + small n nagishi ζ Hatta to the handle 1 unit, and the above-mentioned first frequency dividing means). The output signal of the variable frequency oscillation means is frequency-divided by the second frequency division means and input to the phase difference detection means, and the output signal of the first and second frequency division means is divided by the phase difference detection means. The apparatus further includes a print timing control section for inputting a phase difference signal to the variable frequency oscillation means via the filter means and using an output signal of the variable frequency oscillation means as a print timing signal.

Furthermore, in order to improve printing position accuracy, a third frequency dividing means for dividing the output signal of the variable frequency oscillator, a position counting means, and a position comparison means for comparing a reference value with the position counting means are provided, and the printing control microprocessor (MP
Based on the detailed printing position data calculated by U, a reference value is set at an arbitrary position within the run-up section of the carriage of the printing device and where the output signal of the variable frequency oscillator is controlled in synchronization with the encoder signal. After passing this reference value, the frequency division ratio of the fifth frequency dividing means is set to the value calculated by the MPU for a one minute period, and the subsequent frequency division ratio is
It is equipped with a print timing control section that is set to match the print pitch and uses this signal as a print timing signal.

Such a printing apparatus is particularly effective in a serial dot printing apparatus equipped with a carriage drive system whose speed is stably controlled.

An example of a printing device whose speed can be controlled stably is a seven-speed locked-loop speed system that uses a DC motor in the carriage drive system of the printing device and adds a frequency-modulated feedback loop of a reference oscillator consisting of a low-pass filter and a differential circuit. There is a printing apparatus that includes a carriage control section that includes a control circuit and a mode selection circuit that switches the voltage applied to the DC motor, and that controls the speed of a carriage drive system.

〔Example〕

The printing apparatus of the present invention will be explained using an example.

In the present invention, a print timing generation circuit using a phase-locked loop has been devised. The present invention will be explained using FIG. 50 is a programmable frequency divider circuit which divides the encoder signal 7 into 1 based on a frequency division value signal 52 from a microprocessor which performs main control of the printer. Similarly, the programmable frequency divider circuit 51 receives a frequency division value signal 52.
The output signal 56 of the voltage-controlled variable frequency frequency oscillator 55 is divided into 1 based on . The phase difference between the frequency-divided output signals 57° and 58 is output as a pulse width signal 59 by the phase difference detector 53. 54 converts the pulse width signal into an analog voltage signal 6
This is a filter circuit for converting to 0, and is a low-pass type filter. An analog voltage proportional to this phase difference is applied to a voltage controlled variable frequency oscillator 55 and sent to the main control microprocessor as a print timing signal 56.

The encoder signal 7 is output as the printer carriage moves, and the print timing signal is locked to the frequency of the encoder signal (M and N are integers) and follows the frequency change of the encoder signal. For example, if the print pitch of the encoder is set to 10 characters/inch, the value of ■ is 12 characters/inch! ! -1S character/I''
In Nochi, set it to soil. Further, the bandwidth of the filter circuit 54 is set to be sufficiently larger than the response frequency of the carriage drive system, and is determined in consideration of the stability and tracking accuracy of the print timing circuit.

Generally, the moving speed characteristics of the printer's carriage are expressed as shown in FIG. 2A. Here, 110 represents the frequency or carriage speed of an incremental reference encoder that is output in accordance with the carriage displacement. The line 115 in the figure is the starting point of actual printing, and the carriage drive control system is designed so that the carriage speed falls within a predetermined error at this point. Here, the step input response characteristics of the print timing control circuit shown in Fig. 1 are expressed as
If the design is as shown in FIG. B111, the response to the carriage speed 110 will be as shown in FIG. 2 B113. In addition, the step input response characteristics of the print timing control circuit are shown in Figure 2B11.
2, the response to the carriage speed 110 is shown in FIG. 2E.

It will look like 114. Therefore, in order to obtain an accurate print timing signal at the print start position 115, it is necessary to make the response of the print timing circuit higher than the response of the carriage drive control system.
5 and later), the stability is lost and accurate printing timing signals cannot be obtained. The response characteristics of the print timing circuit cannot be determined unconditionally depending on the response characteristics of the carriage drive control system, the required print timing accuracy, stability, etc., but when using the carriage drive control system described below, In order to achieve printing timing accuracy (pitch accuracy ±5%), it is necessary to increase the printing timing by at least five times. The responsiveness of the print timing signal is determined by the frequency division numbers N and M, the voltage control station variable frequency oscillator range, and the time constant of the filter circuit.

For example, the print timing generation circuit can generate 12 characters/inch (
Taking for example M/N=615), there are five types of phase lock states as shown in FIG. In FIG. 3, all signals are shown as edge differential signals for explanation. Assume that the reference encoder signal is A in the same figure. Figures B to F show five types of lock states. First, in state B, the reference encoder signal and print timing signal match at carriage position P, and after 5 pulses of the reference encoder signal, 6 pulses of the print timing signal. The two pulses coincide again at the P+5 position of the eye. A print timing signal is generated by sequentially repeating this process. In state O, it matches at position P+1,
They match again at position P+6 and repeat this process. Also, in the D state, there is a match at the position P+2 and P+7, in the E state, there is a match at the P+5 and 'P+8 positions, and in the 7 state, there is a match at the P+4 position.
．． Print timing signals are generated so as to coincide at the position T'+9. This phase opening state B-7 is the frequency divider circuit 5
B-1 because it is determined by the initial and transient conditions of 0.51
1' cannot be arbitrarily specified.

Therefore, although the printing timing signal can be divided accurately, an error of at most one standard encoder pulse occurs in the absolute position. In addition, in FIG. 5, it is assumed that the phase difference in the phase lock state, that is, the output signal 59 of the phase difference detector, is zero.
This value is determined by the order of the filter circuit and the loop gain of the entire print timing generation circuit, and is not necessarily zero in reality.

In the present invention, the above-mentioned B-1 state is arbitrarily designated,
In order to obtain a more accurate print timing signal, a third frequency dividing means is added.

Next, this method will be explained using figures. FIG. 4 is an example of a timing diagram of this method, in which the division pitch of the print timing generation circuit is set to 10 characters/inch for the reference encoder signal and 12 characters/inch for the print timing signal, that is, the frequency division number is M=6. This is an example when N=5. FIG. 4A represents the reference encoder signal. By locking the phase difference between the print timing signal shown in Figure B and A to an arbitrary value in Figure 3B-1, a timing signal can be obtained at an accurate print position. By changing the frequency division number of the frequency circuit 51 from M to MXN, a print timing signal that is N times the reference encoder signal A (N=5 in this case) can be obtained as shown in FIG. A method can be considered in which both the signals A and A are discriminated by the print control MPU, and only the necessary print timing signal is extracted from the G signal. However, in this method, N times as many print timing signals are input to the print control MPH, which complicates the process and significantly reduces the throughput of the process. Therefore, in the present invention, by dividing the print timing signal G using a third frequency divider and changing the frequency division number, the print timing shown in FIG. 4B can be obtained, and this phase relationship can be set arbitrarily. I devised a method to do so. Next, the method will be described. FIG. 5 is a basic block diagram of this system. The part (■) in FIG. 5 has the same configuration and operation as in FIG. Set to . The output 120 of the variable voltage controlled oscillator 55 is divided by 1/X through a programmable frequency divider 121. The frequency division ratio at this time is input to the frequency divider 121 through the data line 125, but the frequency division data at this time is divided into two values 1/A and 1/M.
is input through the data bus 52 of the MPH, and the data selection circuit 122 selects 1 / A e 1 /
Select either value of M. The selection value is switched by the output 126 of the flip 70 knob 123, but in this method, by inputting the set signal 124 of the flip 70 knob at an arbitrary reference encoder position, the 7 lip flop becomes set, and the division ratio is changed. is set to 1/A. After that, when the output pulse G of FIG. 4 of the variable voltage control oscillator 55 is output as A pulse, the print timing signal 5
6 is output, and this signal causes the flip 70 knob 125
enters the reset state, the output of the data selection circuit 122 changes, and the frequency division ratio of the frequency divider circuit 121 changes from 1/A to 1.
/N, and thereafter the print timing signal 56 is outputted every N pulses of the cylinder 41]G. FIG. 4H shows the output of the print timing signal 56 and the output 120 of the variable voltage controlled oscillator 55 at this time. In this example, N=5,
Assuming M=6 and A=4, it is shown that this circuit is operated from the reference encoder position [P+2. In the explanation so far, we have added an explanation assuming that the frequency division ratio of the third frequency divider is 1/N, but the value of N does not necessarily have to be this value, and can be made more finely by making it an integer multiple of N. It is possible to correct the position of the print timing signal.

Next, a method of calculating the frequency division value 17A will be described. The print start position is calculated based on the count value P of the reference encoder signal. Generally, the pitch of the reference encoder is determined to be the minimum interval between dots in 10 characters/inch printing. Here, the explanation will be given assuming that the pitch of the reference encoder signal is determined as described above. First, the values of M and H are determined so that a predetermined printing pitch can be obtained. Next, calculate the printing start position by converting it into a predetermined printing pitch, and calculate this value by R.
shall be. This value is converted into the count value of the reference encoder.

P=RX-: Here, P is the print start position with the reference encoder as a reference.

Since the value of P calculated in the above equation is not necessarily an integer value, the printing position cannot be determined accurately.

p'== nt(Rx-); nt() means cutting off the decimal part of the calculation in parentheses.

Execute the calculation in the above equation to find the integer part of the value of P. As is clear from FIG. 4, in the locked state, the value of the print timing signal before frequency division is M times the output of the reference encoder signal. Therefore, in order to convert to this signal, the value of the decimal part p // P"=(RX-)-P' of the above calculation is multiplied by M and converted into an integer. This value becomes the frequency division number A.

A-1 (RX sprout) -P' IXM To simplify the calculation procedure a little more, first, the value of R is multiplied by N. Next, this value is divided by M, but at this time, integer division is performed, the result is p/, and the remainder is the value of A. When the value of the reference encoder reaches P', the frequency division number of the programmable frequency divider 121 is set to 1/A, and then the print timing signal 56 is set.
By switching to 1/N based on the first output of , printing timing can be obtained at a predetermined position. Note that this calculation is a calculation method when the reference encoder prints in the increasing direction, but in bidirectional printing, when the reference encoder counts are printed in the decreasing direction, 1 is added to the value of P' mentioned above.
'. Also, the value of A can be realized by setting the above-mentioned residual A as A=M-A and setting 1/A' at the position of P'' in the same way as above. Also, in this case, P'.P'' ,A,
By adding an appropriate offset to the value of A', it is possible to correct printing deviation in bidirectional printing.

Next, this circuit will be explained in more detail.

FIG. 6 shows all the elements of the print timing circuit of the present invention.

The direction determination step @219 determines whether the phase of the reference encoder signal (B phase) differs from that of the reference encoder signal (human face) 7 by 90′, and the position counter 221 performs addition or subtraction. This value becomes the value of P. The counted value 222 of this counter is sent to the position comparator 223 and compared with the reference value 224 sent from the MPU, the reference value latch 2.
Reference numeral 25 temporarily stores data sent from the MPU through the data bus 52.
J++-fu+#+7-1-ψhatl t1mukertLh-
--1- is output. On the other hand, position counter latch 226
By temporarily storing the counted value 222 of the position counter 221 at the request of the MPH and outputting it to the data bus 522, it is possible for the MPU to read the carriage position of the printer.

The data latch 200 temporarily stores the frequency division value (N) from the MPU, and outputs it to the frequency divider 50 as a frequency division value signal 200. Further, the data latch 202 temporarily stores the frequency division value (MXN) from MI'U, and outputs this value to the frequency divider 51 as a frequency division value signal 203. data latch 21
6 temporarily stores the value of the frequency division value (A or A' and N) from the MPU and outputs it as a frequency division value signal 215 to the frequency division value selection circuit 122. and the value of N to the frequency divider circuit 121, and the frequency divider value 125
Output as .

The address decoder 209 uses the MPU address signal 210
and the R/W signal 211, the selection signal 204~ of each latch
Output 20B, MPU and charge number H of each day 4-y float song
On the other hand, position comparator 22
The signals of No. 3 are a coincidence signal (P=R) 124 and a mismatch signal (P)R) 227 . Mismatch signal (P(R)2
2B is output. A gate circuit 214 selects a signal based on these three signals and a carriage movement direction signal (R/L signal), and outputs the position reference value and subsequent portions of the generated print timing signal 56 to the MPU as a print timing signal 212. At this time, the gate signal is outputted as shown in FIG. 4J, and the print timing output signal 211 is outputted as shown in FIG.

The operations of other elements are the same as those described above, so their description will be omitted.

Note that the filter circuit 54 is a high-order filter.

The integrating circuit is also a type of low-pass filter.

Further, in the h embodiment, the voltage control type control circuit 55 is used, but the circuit 55. It is also possible to make the filter circuit 54 and the phase difference detector 53 numerically controlled, and to perform all phase difference detection etc. by digital numerical control.

Next, we will discuss the carriage drive control system. The print timing generation circuit of the present invention cannot achieve a predetermined design accuracy if the carriage running system does not operate stably without fluctuations. Therefore, we developed a low-cost, high-performance, high-precision carriage control device that uses a DC motor in the carriage drive system of a serial dot printer, and a phase-locked loop control system that uses fixed-interval print timing signals generated as the carriage moves. To generate printing timing at arbitrary intervals and to print arbitrary character pitches using the same character generator. It is preferable to configure a serial dot printer including a print timing generation circuit.

Therefore, for the carriage drive system using a DC motor, we adopted a method that improves the stability of this carriage control device and suppresses oscillation by adding a simple circuit without reducing the loop gain. FIG. 8 is a block diagram of this system. The phase difference signal 8 detected by the phase comparator 2 is converted into an analog speed signal 11 via a low-pass filter 9, and further converted into a pseudo-acceleration signal 1 by a differentiating circuit 10.
Convert to 2. This signal 12 frequency-modulates the output signal of the reference oscillator 1. This control system achieves the same effect as adding acceleration feedback looseness to a speed control device configured with an analog circuit, without reducing the quick response and high accuracy of a phase-locked loop control device. It has the effect of improving stability. Figure 9 (
α) shows the response 16 of the phase-locked loop control device shown in FIG. 7, and FIG. 7(b) shows the response 17 of the control device of the type shown in FIG. Reference numeral 18 in the figure indicates the set speed, and shows a state in which a signal for the set speed of 1 day is added from a stopped state at time 0.

In the carriage control of a serial printer, the present invention can substantially improve the printing speed by skipping the non-printing section at high speed and moving to the next printing start position after printing one line at high speed. In view of the above points, this method provides a method for improving the responsiveness when reducing the set speed using a simple circuit without adding any special mechanical brake device, and uses the block diagram shown in Figure 10. An embodiment of the lever will be explained. FIG. 10 shows the method shown in FIG. 8 with a mode selection circuit 19 added, and 24 is an input signal that changes the frequency of the reference oscillator 1 to change the set speed.
When a certain set speed signal 24 is input, the output frequency 6 of the oscillator 1 changes. At this time, if the input set speed is greater than the set speed before changing, the phase advance signal 8 of the phase detector 2 (when the phase of the oscillator output signal is ahead compared to the encoder output signal 7) is output. This signal is applied to the motor 4 via the mode selection circuit 19 and the driver circuit 5 to increase the speed. The control method is the same as that in FIG. On the other hand, when the input set speed signal 24 is smaller than the previous set speed, a speed reduction signal 25 is applied to the brake flip-flop 25 at the same time as the set speed signal 24 changes, and this 7-lip-flop 25 is set.

Using the output signal 21 of the flip 70 knob 25, the mode selection circuit 19 switches the control signal to a phase delayed signal 22 (in which the phase of the oscillator output signal is delayed compared to the encoder output signal 7), and further changes the current direction. The signal is output to the driver 3 to apply the brake. When the motor speed decreases below the set speed, the phase lead signal 8 is output, so the brake flip-flop 25 is reset and the mode selection circuit 19 is switched to perform the control operation before braking. Return to

This control circuit applies reverse energization to the brakes during deceleration, providing the same level of responsiveness as during acceleration. FIG. 11 shows an example of the response when the set speed is changed. When the set speed 24 is changed from 0 to the value shown at 28 at time 31, the speed of this control device increases from 0 to 30 as shown at 26, and when the set speed 24 is further increased to the value 27 at time 32. Velocity 26 increases to a value of 29. Conversely, when the set speed 24 is decreased to the original value of 28 at time 63, the speed becomes 26.
is decelerated to a value of 30. The broken line shown at 34 shows the speed characteristics when this circuit is not added.

FIG. 12 shows a concrete diagram of the embodiment shown in FIG. 10. 101 is an integrated circuit capable of frequency modulation with the acceleration signal 12, and its output signal 58 is divided by a programmable frequency divider 67 to a frequency corresponding to the speed setting signal 24, and the output signal 6 is
The phase difference detector 2 detects the phase of the encoder signal 7 and the encoder signal 7. Reference numeral 39 denotes a circuit called a charge/discharge pump, which converts the phase difference signal into an analog speed signal 11 by a low-pass filter 9 composed of this and an operational amplifier 40, and further converts it into an acceleration signal 12 by a differentiating circuit 10. The portion within the dotted line 47 is built into a commercially available integrated circuit for controlling the 7A locked loop. On the other hand, the signal 35 is a signal that determines the advancing direction of the carriage shown in 13 in FIG. , a mode selection circuit 19. The output 20 of the mode selection circuit 19 changes the direction and time in which the motor 4 is energized by the switching type driver 3 made up of four transistors. 36 is a current limiting circuit for controlling the large current that flows when the motor is reversely energized and when starting up, and is useful when a DC motor is used in equipment that frequently starts, stops, and reverses, such as the carriage drive system of a serial printer. Prevent a significant drop in waiting life.

This value is determined by the band IfQiNt resistor 44 and capacitor 45 of the low-pass filter 9, but this value is sufficiently lower than the frequency of the encoder signal corresponding to the set speed and is sufficient to pass the natural frequency of the control system obtained by actual measurement or calculation. bandwidth. The value of the resistor 42 that performs high frequency correction of this low-pass filter is selected to be sufficiently smaller than that of the resistor 44. Further, the ratio between the resistor 41 and the resistor 44 becomes an adjustment parameter for the damping ratio of this control system. Also, the differential circuit 1
The time constant is determined by the product of the zero resistance 45 and the capacitor 46, and this value is set to a value that has a differential effect on the natural frequency of the control system.

Note that in the present invention, "printing" refers to characters.

′! l! It is a broad outline, including six figures. A RAM may be used instead of a character generator, and characters, graphic patterns, etc. in the RAM may be dump printed. The head may have one pin or a plurality of bins such as 9, 24, 32, etc., and the plurality of bins may be arranged in a direction perpendicular to the printing direction. Further, in addition to the wire tod type printing device, a thermal type, a thermal transfer type, an on-demand type, or other inkjet type printing device may be used. In this case, the above-mentioned "bottle" may be replaced with "electrode".

Additionally, if the head is equipped with multiple bins or electrodes in a direction that intersects the printing direction, by changing the inclination of the head perpendicular to the recording paper, the pitch of the dots that make up the character in the printing direction can be adjusted. You can also change the height of the letters at the same time. This is the head bin (
Alternatively, it is possible to do this by changing the angle between the direction in which the dots (electrodes) are aligned and the printing direction, but in this case, pay attention to the timing of printing the dots, and advance or delay the printing timing according to each row. [Effects of the Invention] As described above, the printing device of the present invention generates the printing timing at different pitches, thereby converting character patterns stored in the same character generator into characters with different pitches. Furthermore, the printing position error is small.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the PLI and shape printing timing generation circuit. FIG. 2 is a diagram showing the responses of the carriage drive system and the PLL print timing generation circuit. FIG. 4 is an explanatory diagram showing the phase relationship between the encoder signal and the print timing signal. FIG. 4 is a timing diagram showing the relationship between the output signal of the print timing circuit including the third frequency divider and the carriage position. FIG. 5 is an explanatory block diagram of a print timing circuit including a fifth frequency divider. FIG. 6 is a block diagram illustrating FIG. 5 in more detail. FIG. 7 is a block diagram of a conventional phase-locked loop control device, in which 13 indicates a printer carriage, 14 a belt pulley, and 15 a printing paper. FIG. 8 is a block diagram of a control device when an acceleration feedback loop is added to a seven-speed locked loop control device. FIG. 9 is a diagram comparing response example 16 of the conventional 7-wheel locked loop control device shown in FIG. 7 and response example 17 of the control device with an added acceleration feedback loop shown in FIG. FIG. 10 shows a schematic diagram of the carriage control device of the present invention. FIG. 11 shows an example of the response of the carriage control device of the present invention and the state of each signal at this time. FIG. 12 is a circuit diagram embodiment of the carriage control device of the printer apparatus of the present invention shown in FIG. 10. that's all

Claims (1)

[Scope of Claims] 1. Consisting of at least first and second frequency dividing means, phase difference detection means, filter means, and variable frequency oscillation means, the reference encoder signal is frequency-divided by the first frequency dividing means. The output signal of the variable frequency oscillation means is input to the phase difference detection means, and the output signal of the variable frequency oscillation means is frequency-divided by the second frequency division means and input to the phase difference detection means. 2, the phase difference signal of the output signal of the frequency dividing means is inputted to the variable frequency oscillation means through the filter means, and the print timing control section is configured to use the output signal of the variable frequency oscillation means as a print timing signal. A printing device featuring: 2. The printing device is equipped with a third frequency dividing means, a position counting means, and a position comparing means for comparing a reference value with the position counting means, and the output signal of the variable frequency oscillation means is used as the output signal of the third frequency dividing means.
2. The printing apparatus according to claim 1, further comprising a function of dividing the frequency by the frequency dividing means and switching the frequency dividing ratio at this time to an arbitrary value by an output signal of the position comparing means. 3. The printing apparatus according to claims 1 and 2, wherein the printing apparatus is a serial dot printing apparatus equipped with a carriage system whose speed is stably controlled. 4. Using a DC motor in the carriage drive system of the printing device,
The carriage is driven by a phase-locked loop type speed control circuit to which a frequency modulation feedback loop of a reference oscillator consisting of a low-pass filter and a differentiation circuit is added, and a mode selection circuit to switch the voltage applied to the DC motor. 4. A printing device according to claim 3, wherein the system is speed controlled. 5. The printing apparatus according to claim 1, wherein the phase difference detection means, the filter means, and the variable frequency oscillation means are of an analog type. 6. The printing apparatus according to claim 1, wherein the phase difference detection means, the filter means, and the variable frequency oscillation means are numerically controlled. 7. The printing apparatus according to claims 1 and 2, wherein characters recorded on the same character generator are printed at different pitches. 8. The printing apparatus according to claim 7, wherein the angle of the head relative to the recording paper differs when printing the same character pattern at different pitches.