JPH07121594B2 - Print timing signal generator for serial printer - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a serial dot printer.

[Prior art]

In recent years, due to the increase in the number of dots forming characters, it has become possible to obtain printing quality close to that of master printing, and at the same time, there is an increasing demand for printers of various fonts and character pitches similar to those of master printing printers.

Generally, the printing pitch of a serial dot printer is 10 characters /
The inch type is used, but with the improvement of the printing quality, the 12 character / inch type and the 15 character / inch type that are used in the mother-size printing type printer are required. As a simple method, there is a method in which the number of character generators corresponding to the print pitch is provided, but it is expensive because it requires a large amount of memory for the character generators.

Also, in order to change the printing pitch of conventional dots,
Set the encoder pitch finely compared to the actual print pitch and divide the output print timing to obtain a print signal with a specified print pitch, or use a timer between several pulses of the print timing signal. The method of splitting is used. However, these methods have drawbacks in that an expensive high-resolution encoder is required and errors are accumulated, resulting in a large error in the print pitch at the end of the divided section.

[Problems to be solved by the invention]

The present invention overcomes the above-mentioned drawbacks of the prior art, and enables the same character generator to be used for character printing of different pitches by generating the print timing signals at different pitches, and further, the printing position error can be reduced. The purpose is to provide a device.

[Means for solving problems]

A print timing signal generation device for a serial printer according to the present invention moves a carriage having a print head in the row direction, generates a frequency signal M times as high as a pulse signal output when the carriage moves a predetermined distance, In a print timing signal generation device for a serial printer, which outputs a M times frequency signal as a print timing signal via a frequency dividing means, the frequency dividing means capable of switching a frequency dividing value and the frequency dividing means in response to a print start position signal. A frequency division value is set to A, the frequency division means is activated, and frequency division value selection means for switching the frequency division value to N is provided in response to the first print timing signal output from the frequency division means. Characterize. (However,
M, A, N are integers greater than 1. Such a print timing signal generation device for a serial printer can exert its effect particularly in a serial printer having a carriage drive system whose speed is stably controlled. It is most suitable to use the carriage drive system disclosed in Japanese Patent Laid-Open No. 58-59876 disclosed by the applicant.

〔Example〕

A printing apparatus of the present invention will be described with reference to an embodiment. The present invention has devised a print timing generation circuit using a phase locked loop. The present invention will be described with reference to FIG.
FIG. 50 is a programmable frequency dividing circuit, which divides the encoder signal 7 into 1 / N based on the frequency dividing value signal 52 from the microprocessor which performs the main control of the printer. Similarly, the programmable frequency dividing circuit 51 divides the output signal 56 of the voltage controlled variable frequency oscillator 55 into 1 / M based on the frequency division value signal 52. The phase difference detector 5 detects the phase difference between the divided output signals 57 and 58.
The pulse width signal 59 is output according to 3. Reference numeral 54 is a filter circuit for converting a pulse width signal into an analog voltage signal 60, which is a low-pass filter. An analog voltage proportional to this phase difference is added to the voltage-controlled variable frequency oscillator 55, and a print timing signal is sent to the main control microprocessor.
Sent as 56.

The encoder signal 7 is output in accordance with the movement of the carriage of the printer, and the print timing signal is locked at the M / N frequency (M and N are integers) of the encoder signal frequency, and follows the frequency change of the encoder signal. For example, when the encoder printing pitch is set to 10 characters / inch, the M / N value is set to 6/5 for printing 12 characters / inch and set to 3/2 for 15 characters / inch. The bandwidth of the filter circuit 54 is set sufficiently larger than the response frequency of the carriage drive system, and is determined in consideration of the stability and tracking accuracy of the print timing circuit.

In general, the moving speed characteristic of the printer carriage is represented as shown in FIG. 2A. Here, 110 represents the frequency of the incremental reference encoder or the carriage speed that is output with the displacement of the carriage. The line in FIG. 115 is the starting point of actual printing, and the carriage drive control system is designed so that the carriage speed is within a predetermined error at this point. Here, the step input response characteristic of the print timing control circuit shown in FIG. 1 is shown in FIG.
When designed as shown in FIG. 11, the response to the carriage speed 110 is as shown in D113 in FIG. When the step input response characteristic of the print timing control circuit is designed as shown in FIGS. 2C and 112, the response to the carriage speed 110 is as shown in FIGS. 2E and 114. Therefore, in order to obtain an accurate print timing signal at the print start position 115, it is necessary to make the response of the print timing circuit higher than the response of the carriage drive control system, but if it is made too high, the steady state (115 After that), the stability is not obtained and an accurate print timing signal cannot be obtained. The response characteristics of the print timing circuit cannot be determined unconditionally depending on the response characteristics of the carriage drive control system, the required printing timing accuracy, stability, etc., but when using the carriage drive control system described later, In order to realize the printing timing accuracy (pitch accuracy ± 5%), it is necessary to increase it at least about three times. The response of the print timing signal is determined by the frequency division number N, M, the oscillation range of the voltage controlled variable frequency oscillator, and the time constant of the filter circuit.

The print timing generation circuit is, for example, 12 characters / inch (M /
Taking N = 6/5) as an example, there are five types of phase lock states as shown in FIG. For the sake of explanation, FIG. 3 shows all signals as edge differential signals. Assume that the reference encoder signal is A in FIG. FIGS. 3B to 3F show five types of lock states. First, in the state of B, the reference encoder signal and the print timing signal match at the carriage position P, and after the reference encoder signal has 5 pulses, the print timing signal has 6 pulses. The two pulses coincide again at the position P + 5 of the eye. A print timing signal is generated by repeating this sequence. In the state of C, it coincides at the position of P + 1 and coincides again at the position of P + 6, and this is repeated. In the state of D, P
+2, P + 7 match, E = P + 3, P +
The print timing signal is generated so that the position 8 coincides, and in the state F, the positions P + 4 and P + 9 coincide. Since the phase locked states B to F are determined by the initial and transient states of the frequency dividing circuits 50 and 51, it is not possible to arbitrarily specify which phase relation of B to F. Therefore, although the division of the print timing signal can be accurately executed, a maximum error of one reference encoder pulse occurs at the absolute position. In Fig. 3, the phase difference in the phase locked state, that is, the output signal 59 of the phase difference detector is assumed to be zero, but this is a value determined by the order of the filter circuit and the loop gain of the entire print timing generation circuit. Is not necessarily zero.

In the present invention, the lock states of B to F are arbitrarily designated,
A third frequency dividing means is added to obtain a more accurate print timing signal.

Next, this method will be described with reference to the drawings. FIG. 4 is an example of a timing diagram of this system, in which the division pitch of the print timing generation circuit is set to 10 characters / inch for the reference encoder signal,
This is an example when the print timing signal is 12 characters / inch, that is, the frequency division number is M = 6, N = 5. FIG. 4A represents the reference encoder signal. By locking the phase difference between the print timing signal shown in FIG. 3B and A to an arbitrary value in FIGS. 3B to 3F, a timing signal can be obtained at an accurate print position. By changing the frequency division number of the frequency circuit 51 from M to M × N, a print timing signal M times (M = 5 in this case) of the reference encoder signal A is obtained as shown in FIG. 4G. A method of discriminating both the signal of A and the signal of A by the print control MPU and extracting only the necessary print timing signal from the signal of G can be considered. However, in this method, since the M times print timing signal is input to the print control MPU, the process becomes complicated and the throughput of the process is significantly reduced. Therefore, in the present invention, the print timing signal G is divided by using the third frequency divider, and the print timing of FIG. 4B is obtained by changing the frequency division number, and the phase relationship is arbitrarily set. I devised a method to do it. Next, the method will be described. FIG. 5 is a basic block diagram of this system. The part of FIG. 5 has the same configuration as that of FIG. 1 and operates in the same manner, but the frequency division number of the programmable frequency dividing circuit 51 is 1 / m through the data bus 52 of the MPU.
Set to (M × N). Variable voltage controlled oscillator 55 output 12
0 is divided into 1 / X through the programmable divider 121. The division ratio at this time is the divider 1 through the data line 125.
It is input to 21, but the divided data at this time is two values 1 / A,
The value of 1 / N is input through the data bus 52 of the MPU, and the data selection circuit 122 selects either 1 / A or 1 / N. The selection value is switched by the output 126 of the flip-flop 123.
According to this method, by inputting the set signal 124 of the flip-flop at an arbitrary reference encoder position, the flip-flop is set and the frequency division ratio is set to 1 / A. After this, the variable voltage controlled oscillator 55
When the output pulse of FIG. 4G of FIG. 4A is output as the A pulse, the print timing signal 56 is output, the flip-flop 123 is reset by this signal, the output of the data selection circuit 122 is switched, and the frequency of the frequency divider circuit 121 is changed. From 1 / A to 1 /
After switching to N, the print timing signal 56 is output every N pulses in FIG. 4G. FIG. 4H shows the output of the print timing signal 56 and the variable voltage control oscillator 55 at this time.
The output 120 of is shown. In this example, N = 5, M = 6, A = 4 is set, and this circuit is operated from the reference encoder position P + 2. In the above description, the frequency division ratio M has been described as M = 6, but the value of M does not necessarily have to be this value, and the position of the print timing signal is corrected more finely by making it an integral multiple. It is possible.

Next, the method of calculating the frequency division value 1 / A will be described. The print start position is calculated with reference to the count value P of the reference encoder signal. Generally, the standard encoder pitch is 10 characters /
Determine so that it is the minimum dot spacing for inch printing. Here, description will be made assuming that the pitch of the reference encoder signal is determined as described above. First, the values of M and N are determined so that a predetermined print pitch can be obtained. Next, the print start position is converted into a predetermined print pitch and obtained, and this value is set as R. This value is converted into the count value of the reference encoder.

Here, P is the print start position with the reference encoder as the reference.

Since the value of P in the above equation is not necessarily an integer value, the print position cannot be accurately determined.

Int () means to cut off the decimal point of the operation in ().

The operation of the above equation is executed to find the integer part of the value of P. As is clear from FIG. 4, in the locked state, the value of the print timing signal before frequency division is M times that of the reference encoder signal. Therefore, in order to convert to this signal, the part P ″ below the decimal point of the above calculation The value of is multiplied by M to be an integer. This value becomes the frequency division number A.

To simplify the calculation procedure a little more, first, the value of R is multiplied by N. Next, this value is divided by M. At this time, the result of integer division is P ', and the remainder is the value of A. When the value of the reference encoder becomes P ', the frequency division number of the programmable frequency divider 121 is set to 1 / A, and then it is switched to 1 / N by the first output of the print timing signal 56, and printing is performed at a predetermined position. Get the timing. This calculation is a calculation method when the reference encoder prints in the increasing direction. However, when the reference encoder count is printed in the decreasing direction in bidirectional printing, 1 is added to the value of P ′ and P is added. And Further, the value of A can be realized by setting the above-mentioned residual A to A '= MA and setting 1 / A' at the position of P similarly to the above. Further, by adding an appropriate offset amount to the values of P ', P, A, A'at this time, it becomes possible to correct the print misalignment in bidirectional printing.

Next, this circuit will be described in more detail.

FIG. 6 shows all the elements of the print timing circuit of the present invention.
The direction discriminating circuit 219 discriminates whether the reference encoder signal (A phase) 7 is 90 degrees out of phase with the reference encoder signal (B phase) 217, and the position discriminating circuit 219 performs addition or subtraction. This value becomes the value of P. The count value 222 of this counter is sent to the position comparator 223, and is compared with the reference value 224 indicating the print start position sent from the MPU. The reference value memory 225 stores the data sent from the MPU through the data bus 52. This is temporarily stored, and the value of P ′ or P described above is stored and output as a reference value 224. On the other hand, the position counter memory 226 uses the count value 222 of the position counter 221 as the MPU.
By temporarily storing the data and outputting the data to the data bus 52, the MPU can read the carriage position of the printer.

The data memory 200 temporarily stores the frequency division value (N) from the MPU, and outputs it as the frequency division value signal 201 to the frequency divider 50. The data memory 202 temporarily stores the frequency division value (M × N) from the MPU, and this value is used as the frequency division value signal 203 by the frequency divider 51.
Output to. The data memory 216 temporarily stores the value of the frequency division value (A or A ′ and N) from the MPU, and outputs the frequency division value signal 215.
To the frequency division value selection circuit 122, and the frequency division value selection circuit switches the value of A or A ′ and the value of N to the frequency division circuit 12
Output to 1 as the division value 125.

Address decoder 209 is MPU address signal 210 and R / W signal
The selection signals 204 to 208 of each latch are output from 211, and the numerical values are transferred between the MPU and each data latch.

On the other hand, the signal of the position comparator 223 is a coincidence signal (P = P) between the position count value 222 (P) and the position reference value 224 (R).
R) 124 and disagreement signal (P> R) 227, disagreement signal (P <
R) 228 is output. The gate circuit 2 by these three signals and the carriage movement direction signal (R / control signal 213)
The print timing signal 56 selected and output after the position reference value is output to the MPU as the print timing signal 212. At this time, the gate signal is output in FIG. 4J and the print timing output signal 211 is output in FIG. 4K.

The operation of the other elements is the same as that described above, and therefore will be omitted.

The low-pass filter 54 may be a high-order filter. The integrating circuit is also a kind of low-pass filter.

Further, although the voltage control type variable frequency oscillator 55 is used in the embodiment, the circuit 55, the low-pass filter 54 and the phase difference detector 53 may be of a numerical control type, and phase difference detection and the like may be all performed by digital numerical control. Is.

Next, the carriage drive control system will be described. The print timing generation circuit of the present invention cannot obtain a predetermined design accuracy unless the carriage traveling system is operating stably without fluctuation. Therefore, in this embodiment, a method is adopted in which a DC motor is used in the carriage drive system and a simple circuit is added without lowering the loop gain to improve the stability of the carriage control device and suppress oscillation. FIG. 8 is a block diagram of this system. The phase difference signal 8 detected by the phase comparator 2 is converted into an analog speed signal 11 via a low pass filter 9, and further, a pseudo acceleration signal 12 is obtained by a differentiating circuit 10.
Convert to. The signal 12 frequency-modulates the output signal of the reference oscillator 1. This control system has the same effect as adding the acceleration feedback loop to the speed control device composed of analog circuits, and does not reduce the responsiveness and high accuracy of the phase locked loop type control device. Has the effect of improving stability. Fig. 9 (a)
FIG. 7 shows a response 16 of the phase locked loop controller shown in FIG. 7 and response 17 of the controller of the system shown in FIG. Reference numeral 18 in the drawing indicates a set speed, which is a state where a signal of the set speed 18 is applied from the stopped state at time 0.

In the carriage control of the serial printer, the non-printing section can be skipped at high speed, or after the printing of one line is completed, the printing speed can be moved to the next printing start position at a high speed, thereby substantially improving the printing speed.

In consideration of the above points, the present embodiment adopts a method of improving the responsiveness when reducing the set speed with a simple circuit without adding a special mechanical braking device or the like.
This embodiment will be described with reference to the block diagram of FIG. 10th
The figure shows the mode selection circuit 19 added to the system shown in FIG.
24 is an input signal that changes the frequency of the reference oscillator 1 to change the set speed. When a certain set speed signal 24 is input,
The output frequency 6 of the oscillator 1 changes. At this time, when the input set speed is higher than the set speed before the change, the phase lead signal 8 of the phase detector 2 (when the phase of the oscillator output signal leads the encoder output signal 7) is output. This signal is applied to the motor 4 via the mode selection circuit 19 and the driver circuit 3 to increase the speed. The control method is the same as that in FIG. On the other hand, if the set speed signal 24 input is smaller than the previous set speed, the set speed signal 24
Simultaneously with the change of 24, the speed decrease signal 25 is added to the brake flip-flop 23, and the flip-flop 23 is set. The mode selection circuit 19 switches the control signal to the phase delay signal 22 (when the phase of the oscillator output signal is delayed compared to the encoder output signal 7) by the output signal 21 of the flip-flop 23, and further changes the energizing direction to drive the driver. Output to 3 and apply the brake. When the motor speed falls below the set speed, the phase lead signal 8 is output, so the brake flip-flop 23 is reset and the mode selection circuit
Switch 19 to return to the control operation before braking. Since this control circuit applies a reversely energized brake during deceleration, it is possible to obtain the same responsiveness as during acceleration. FIG. 11 shows an example of response when the set speed is changed. Set speed 24 to 0 at time 31
From 28 to 28, the speed of this controller is 26
As shown in, when the set speed 24 is increased to a value of 27 at time 32 and the set speed 24 is further increased to a value of 27, the speed 26 is increased to a value of 29. Conversely, when the set speed 24 is reduced to the original value of 28 at time 33, the speed 26 is decelerated to the value of 30. The broken line shown in 34 shows the speed characteristics when this circuit is not added.

FIG. 12 shows a concrete view of the embodiment shown in FIG. Ten
Reference numeral 1 is an integrated circuit capable of frequency modulation with the acceleration signal 12, and the output signal 38 is frequency-divided by the programmable frequency divider 37 into a frequency corresponding to the speed setting signal 24. The phase difference between the output signal 6 and the encoder signal 7 is obtained. It is detected by the detector 2. Reference numeral 39 denotes a circuit called a charge / discharge pump, which converts a phase difference signal into an analog speed signal 11 by a low-pass filter 9 composed of this and an operational amplifier 40, and further converts it into an acceleration signal 12 by a differentiating circuit 10. The part within the dotted line of 47 is the part built in an integrated circuit which is commercially available for phase locked loop control. On the other hand, the signal 35 is a signal for determining the direction of advance of the carriage shown in 13 of FIG. 10, and a circuit for switching the phase advance signal 8 and the phase delay signal 22 is provided by this signal and the output signal 21 of the brake flip-flop 23. , Mode selection circuit 19. The output 20 of the mode selection circuit 19 causes the switching type driver 3 composed of four transistors.
Changes the direction and time for energizing the motor 4. 36
Is a current limiting circuit for controlling a large current that flows when the motor is reversely energized and started. The life when the DC motor is used in a device such as the carriage drive system of a serial printer, where start, stop, and reverse rotation are frequently repeated. To prevent a significant decrease.

The bandwidth of the low-pass filter 9 is a resistor 44 and a capacitor 43.
However, this value is sufficiently lower than the frequency of the encoder signal corresponding to the set speed, and the natural frequency of the control system obtained by actual measurement or calculation is set to a bandwidth that allows sufficient passage. The resistor 42 for high-frequency correction of this low-pass filter is selected to have a sufficiently small value as compared with the resistor 44. Further, the ratio of the resistor 41 and the resistor 44 becomes the damping parameter of the damping ratio of this control system. Also, the resistor 45 and the capacitor of the differentiating circuit 10
The time constant is determined by the product of 46, and this value is set to a value that has a differential effect on the natural frequency of the control system.

In the present invention, "printing" is a broad concept including characters, numbers, figures and the like. RAM may be used instead of the character generator to dump print the characters and graphic patterns in the RAM. The head has 1 pin, 9, 24, 32
A plurality of pins, or the plurality of pins may be aligned in a direction intersecting the printing direction. In addition to the wire dot type printing device, thermal type,
A printing device such as a thermal transfer type or an on-demand type inkjet type may be used. In this case, the “pin” may be replaced with the “electrode”.

When the head is equipped with multiple pins and electrodes in a direction that intersects the printing direction, the pitch of the dots that make up the characters in the printing direction can be changed by changing the angle of the head in the vertical direction with respect to the recording paper. The height of the letters can be changed at the same time as the change. This can also be done by changing the angle between the direction in which the pins (or electrodes) of the head are aligned and the printing direction. In this case, pay attention to the dot print timing and adjust the print timing according to each dot row. You need to speed up or slow down.

〔The invention's effect〕

As described above, according to the present invention, the print timing signal having a frequency M / N times that of the timing pulse generated in synchronization with the predetermined distance movement of the carriage only by setting the frequency division ratio (N, M). The print timing signal can be generated by arbitrary decomposition by appropriately selecting the frequency division ratio (N, M). for that reason,
Characters of various sizes can be printed using the same character generator. Further, since it is possible to finely control the position where the leading print timing signal is generated, it is possible to prevent uneven printing start positions and bidirectional printing misalignment.

[Brief description of drawings]

FIG. 1 is a block diagram of a PLL type print timing generation circuit. FIG. 2 is a diagram showing the response of the carriage drive system and the PLL print timing generation circuit. FIG. 3 is an explanatory diagram showing the phase relationship between the encoder signal and the print timing signal. FIG. 4 is a timing chart showing the relationship between the output signal of the print timing circuit including the third frequency divider and the carriage position. FIG. 5 is an explanatory block diagram of a print timing circuit to which a third frequency divider is added. FIG. 6 is a block diagram explaining FIG. 5 in more detail. FIG. 7 is a block diagram of a conventional phase locked loop type control device, in which 13 is a carriage of a printer, 14 is a belt pulley, and 15 is a printing paper. FIG. 8 is a block diagram of the phase locked loop controller when the acceleration feedback loop is added to the controller. FIG. 9 is a diagram comparing the response example 16 of the conventional phase locked loop controller shown in FIG. 7 with the response example 17 of the controller shown in FIG. 8 to which the acceleration feedback loop is added. FIG. 10 shows a block diagram of the carriage control device of the present invention. FIG. 11 shows a response example of the carriage control device of the present invention and the state of each signal at this time. FIG. 12 is a circuit diagram embodiment of the carriage control device of the printer device of the present invention shown in FIG.

Claims (3)

[Claims] 1. A carriage carrying a print head is moved in a row direction to generate a frequency signal M times as high as a pulse signal output in accordance with a predetermined distance movement of the carriage, and the frequency signal M is divided. In a print timing signal generator for a serial printer that outputs a print timing signal via a means, the frequency dividing means can switch the frequency dividing value, and the frequency dividing value is set to A in response to a print start position signal. Print timing of a serial printer, comprising means for activating the means and responding to the first print timing signal output from the frequency dividing means, for switching the frequency dividing value to N Signal generator. (However, M, A, N are integers greater than 1) 2. The print timing signal generating device for a serial printer according to claim 1, wherein the M-fold frequency signal is generated by a phase locked loop. 3. The print timing signal generating device for a serial printer according to claim 1, wherein the frequency division value A differs depending on the printing direction.