JPS60128615A - Electrolyte plating method for semiconductor wafer - Google Patents
Electrolyte plating method for semiconductor waferInfo
- Publication number
- JPS60128615A JPS60128615A JP23691483A JP23691483A JPS60128615A JP S60128615 A JPS60128615 A JP S60128615A JP 23691483 A JP23691483 A JP 23691483A JP 23691483 A JP23691483 A JP 23691483A JP S60128615 A JPS60128615 A JP S60128615A
- Authority
- JP
- Japan
- Prior art keywords
- electrolyte
- metal plate
- contact
- type region
- wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 239000003792 electrolyte Substances 0.000 title claims abstract description 13
- 238000007747 plating Methods 0.000 title claims description 5
- 238000000034 method Methods 0.000 title claims description 4
- 235000012431 wafers Nutrition 0.000 claims abstract description 26
- 238000009713 electroplating Methods 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 239000002184 metal Substances 0.000 abstract description 15
- 229910052751 metal Inorganic materials 0.000 abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 12
- 229910052710 silicon Inorganic materials 0.000 abstract description 12
- 239000010703 silicon Substances 0.000 abstract description 12
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract 1
- 229910052737 gold Inorganic materials 0.000 abstract 1
- 239000010931 gold Substances 0.000 abstract 1
- 229910052738 indium Inorganic materials 0.000 abstract 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 abstract 1
- 239000011248 coating agent Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000000463 material Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000008151 electrolyte solution Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
- H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Electroplating Methods And Accessories (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、半導体ウェハの電解メッキ方法に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for electrolytic plating of semiconductor wafers.
n型半導体ウェハ上のp型頭域にpn接合を通して電流
を流すことにより電解メッキを行なう場合、n型半導体
ウェハの裏面を直接電解液に接触させないようにする必
要がある。これは、pn接合に拡散電位が存在するため
、裏面のn型部分に比較してp型部分に電流が流れにく
くなるためである。n型半導体ウェハ上のn型領域に電
解メッキを行なう場合も同様に、p型半導体ウニへの裏
面を直接電解液に接触させないようにする必要がある。When performing electrolytic plating by passing a current through a pn junction to the p-type head region on an n-type semiconductor wafer, it is necessary to prevent the back surface of the n-type semiconductor wafer from coming into direct contact with the electrolyte. This is because the existence of a diffusion potential in the pn junction makes it difficult for current to flow through the p-type portion compared to the n-type portion on the back surface. Similarly, when performing electrolytic plating on an n-type region on an n-type semiconductor wafer, it is necessary to prevent the back surface of the p-type semiconductor wafer from coming into direct contact with the electrolyte.
従来、第1図に示すように、半導体ウェハSの裏面を絶
縁性の被膜Mで覆っていたが、裏面をくまなく覆うには
多量の被膜形成材が必要でコストが高くなるだけでなく
、被膜にピンホールが形成されて被膜の効果が失われ易
いという問題があった゛。Conventionally, as shown in FIG. 1, the back surface of a semiconductor wafer S has been covered with an insulating film M, but in order to cover the entire back surface, a large amount of film forming material is required, which not only increases cost. There was a problem in that pinholes were formed in the coating and the effectiveness of the coating was likely to be lost.
本発明は上記従来の問題に鑑みてなされたものであり、
その目的は、低コストで歩留りのよい半導体ウェハの電
解メッキ方法を提供することにある。The present invention has been made in view of the above-mentioned conventional problems,
The purpose is to provide a method for electrolytic plating of semiconductor wafers that is low cost and has a high yield.
上記目的を達成する本発明は、2枚の半導体ウェハの裏
面を、金属板を挾んで相互に密着することにより電解液
との接触を妨げると共にこの金属板に電圧を供給するよ
うに構成されている。To achieve the above object, the present invention is configured such that the back surfaces of two semiconductor wafers are brought into close contact with each other by sandwiching a metal plate to prevent contact with an electrolyte and to supply voltage to the metal plates. There is.
以下1本発明の更に詳細を実施例によって説明する。The present invention will now be explained in more detail by way of examples.
第2図は9本発明の一実施例を説明するための断面図で
ある。Sはn型シリコンウェハであり。FIG. 2 is a sectional view for explaining one embodiment of the present invention. S is an n-type silicon wafer.
その表面には二酸化シリコン等の絶縁膜Iで分離された
複数のp壁領域が形成されている。Cは金属板、Aは電
極2Mは被膜である。A plurality of p-wall regions separated by insulating films I made of silicon dioxide or the like are formed on the surface thereof. C is a metal plate, A is an electrode 2M is a coating.
−2枚のn型シリコンウェハSの裏面は金属板Cを介し
て密着されることにより、電解液との接触が妨げられて
いる。側面におけるシリコンウェハSと電解液との接触
を防止するため、小量の被膜Mが付加される。金属板C
には電圧が供給され。- The back surfaces of the two n-type silicon wafers S are brought into close contact with each other via the metal plate C, thereby preventing contact with the electrolyte. A small amount of coating M is added to prevent contact between the silicon wafer S and the electrolyte on the side surfaces. metal plate C
is supplied with voltage.
ここからシリコンウェハSのn型領域2表面直下のpn
接合2表面のp型W4域及び電解液を介して電極Aに至
る電流路が形成され1表面のp壁領域に電解メッキ層が
形成される。From here, pn immediately below the surface of n-type region 2 of silicon wafer S
A current path is formed through the p-type W4 region on the surface of the junction 2 and the electrolytic solution to the electrode A, and an electrolytic plating layer is formed on the p-wall region on the surface 1.
金属板Cとしては、シリコンウェハSとの電気的接触を
良くするため、インジュムや金環伸展性の高い軟金属が
好適である。また、被膜Mとしては、メッキ液への耐性
が高くかつシリコンウェハSと金属板Cとの密着強度を
高めるうえで粘着性の高いワックス等が好適である。こ
の被膜Mは。As the metal plate C, in order to improve the electrical contact with the silicon wafer S, Injum or a soft metal with high ring extensibility is suitable. Further, as the film M, a wax or the like having high resistance to the plating solution and high adhesiveness in order to increase the adhesion strength between the silicon wafer S and the metal plate C is suitable. This film M is.
電解メッキの終了後、加熱により又は溶剤の使用により
除去される。After electrolytic plating is completed, it is removed by heating or by using a solvent.
また、必要に応じてメッキむらをなくすためシリコンウ
ェハS又は電極Aを回転させればよい。Further, the silicon wafer S or the electrode A may be rotated to eliminate uneven plating as necessary.
以上説明したように9本発明によれば半導体ウェハの裏
面の被覆が不要になるので、被覆材の使用量が少なく低
コストになるという利点がある。As explained above, according to the present invention, there is no need to coat the back surface of the semiconductor wafer, so there is an advantage that the amount of coating material used is small and the cost is low.
また、ウェハ側面の小面積部分だけを被覆すればよいか
ら、ピンホールが形成され難り2歩留りが向上するとい
う利点がある。Furthermore, since only a small area on the side surface of the wafer needs to be coated, pinholes are less likely to be formed and the yield is improved.
さらに9本発明は、2枚の半導体ウエノ\を一度に電解
メッキすることが出来るので1作業時間を短縮できると
云う利点もある。Furthermore, the present invention has the advantage that two semiconductor sheets can be electrolytically plated at the same time, so that one working time can be shortened.
第1図は従来方法を説明するための断面図、第2図は本
発明の一実施例を説明するための断面図である。
S・・シリコンウェハ、C・・金属板1M・・被1J、
!・・二酸化シリコン、A・・電極。FIG. 1 is a sectional view for explaining a conventional method, and FIG. 2 is a sectional view for explaining an embodiment of the present invention. S...Silicon wafer, C...Metal plate 1M...1J covered,
! ...Silicon dioxide, A...Electrode.
Claims (1)
及び該メ・7キ層形成中に電圧が供給されかつ電解液か
ら遮蔽される第2の面を有する半導体ウェハの電解メッ
キ方法において。 2枚の前記半導体ウェハの前記第2の面を、全方法。[Scope of Claims] A first surface that is contacted with an electrolyte to form a plating layer, and a second surface that is supplied with a voltage and shielded from the electrolyte during the formation of the plating layer. In an electrolytic plating method for semiconductor wafers. The second side of the two semiconductor wafers is completely processed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23691483A JPS60128615A (en) | 1983-12-15 | 1983-12-15 | Electrolyte plating method for semiconductor wafer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23691483A JPS60128615A (en) | 1983-12-15 | 1983-12-15 | Electrolyte plating method for semiconductor wafer |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60128615A true JPS60128615A (en) | 1985-07-09 |
Family
ID=17007620
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP23691483A Pending JPS60128615A (en) | 1983-12-15 | 1983-12-15 | Electrolyte plating method for semiconductor wafer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60128615A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02223924A (en) * | 1989-02-27 | 1990-09-06 | Hitachi Ltd | Production of display panel |
WO2000007229A1 (en) * | 1998-07-24 | 2000-02-10 | Interuniversitair Micro-Elektronica Centrum | A system and a method for plating of a conductive pattern |
US6758958B1 (en) | 1998-07-24 | 2004-07-06 | Interuniversitair Micro-Elektronica Centrum | System and a method for plating of a conductive pattern |
EP2500927A3 (en) * | 2011-03-17 | 2014-07-30 | SEMIKRON Elektronik GmbH & Co. KG | Method for depositing a metal coating on a semiconductor element and semiconductor element |
DE102014105066B3 (en) * | 2014-04-09 | 2015-03-05 | Semikron Elektronik Gmbh & Co. Kg | Method and apparatus for depositing a metal layer on a semiconductor device |
-
1983
- 1983-12-15 JP JP23691483A patent/JPS60128615A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02223924A (en) * | 1989-02-27 | 1990-09-06 | Hitachi Ltd | Production of display panel |
WO2000007229A1 (en) * | 1998-07-24 | 2000-02-10 | Interuniversitair Micro-Elektronica Centrum | A system and a method for plating of a conductive pattern |
US6758958B1 (en) | 1998-07-24 | 2004-07-06 | Interuniversitair Micro-Elektronica Centrum | System and a method for plating of a conductive pattern |
EP2500927A3 (en) * | 2011-03-17 | 2014-07-30 | SEMIKRON Elektronik GmbH & Co. KG | Method for depositing a metal coating on a semiconductor element and semiconductor element |
DE102014105066B3 (en) * | 2014-04-09 | 2015-03-05 | Semikron Elektronik Gmbh & Co. Kg | Method and apparatus for depositing a metal layer on a semiconductor device |
US10577707B2 (en) | 2014-04-09 | 2020-03-03 | Semikron Elektronik Gmbh & Co., Kg | Methods and apparatus for depositing a metal layer on a semiconductor device |
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