JPS60127763A - Field effect transistor - Google Patents

Abstract

PURPOSE:To obtain an FET which has less backgate effect by forming a conductive layer different from an active layer on one main surface of opposite side to the main surface formed with the active layer of an fet of a semi-insulating substrate, and applying a potential to the conductive layer. CONSTITUTION:An active layer 4 is formed on one main surface of a semi- insulating substrate 1, a conductive type layer 10 different from the layer 4 is formed on the other main surface, an ohmic electrode 11 is formed on the layer 10, and a voltage is applied to the substrate 1. For example, in case of a GaAs MESFET in which a semi-insulating GaAs substrate 1 is formed with an n<+> type source region 2, an n<+> type drain region 3, an n type active layer 4, a p type layer 10 and an ohmic electrode 11, the electrode 11 and a drain electrode 6 are shortcircuited and a positive potential is applied to a source electrode 5. Then, holes presented in the layer 10 are implanted to a negative charge layer presented in the boundary 9, the charge layer is neutralized to reduce the thickness of a depletion layer. Thus, an FET having less backgate effect can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to field effect transistors (FETs).

The structure of the conventional example and its problems will be explained below by taking the aAs MESFET as an example. Fig. 1 shows a structural diagram of the conventional GaAs MESFET. 1 is a semi-insulating GaAs substrate. 2.3.4 are a type 1 source region, a square drain region, and an n-type active layer formed by selective ion implantation, respectively.5 and 6. are a source electrode, a drain electrode, and a gate electrode, respectively. 8 is the depletion layer directly under the gate,
Reference numeral 9 indicates the interface between the semi-insulating (SI type) GaAs substrate 1 and the active layer 4. In this way, in the conventional MESFKT structure,
Due to the deep traps existing in the substrate 1 and the difference in Fermi level between the active layer 4 and the substrate 1, a depletion layer similar to a Pn junction is formed near the interface 9, and as shown in FIG. Charge layer: A negative charge layer is formed on the substrate 1 side.

Therefore, the thickness of the active layer 4 decreases by this amount, and when the potential of the semi-insulating GaAs substrate 1 becomes more negative than the potential of the source 5, the thickness of this charge layer increases, and the drain current decreases. An effect (backgate effect) appears, and in particular, since a negative potential is used in a circuit constituted by a depletion type FET, this effect has a large influence and deteriorates the characteristics of the FET.

OBJECTS OF THE INVENTION In view of the above problems, the present invention provides an FET with less backgate effect.

Structure of the Invention The present invention involves forming a conductive layer different from the active layer on one main surface of a semi-insulating substrate opposite to the main surface forming the active layer of the FET, and applying a potential to the conductive layer. This reduces the thickness of the depletion layer existing in the semi-insulating substrate and the active layer of the FET, thereby obtaining an FET with less back gate effect.

DESCRIPTION OF EMBODIMENTS FIG. 2 shows a structural diagram of ymT according to an embodiment of the present invention. In the figure, 1 to 9 are the same as in Figure 1, and 1
0 indicates a P-type layer, and 11 indicates an ohmic electrode. In the figure, when the electrode 11 and the drain electrode 6 are short-circuited and a positive potential is applied to the source electrode 6, the holes existing in the P-type layer 10 are transferred to the negative charge layer (mainly positive) existing at the interface 9. (by hole traps), this charge layer is neutralized and the thickness of the depletion layer is reduced. Therefore, an FET with less backgate effect can be obtained.

FIG. 3 compares the back gate effect of a conventional FET having the same active layer with a gate length of 1 μm and a gate width of 50 μm and the FET of the present invention. The back gate electrode is an n+ region ohmic electrode formed 30 μm away from the FET. In the figure, the vertical axis is the drain current normalized to the drain saturation current when the back gate voltage is Ov, and the horizontal axis is the back gate voltage. It is voltage. As is clear from FIG. 3, the FET 1d of the present invention indicated by a solid line,
It can be seen that the back gate effect is much smaller than that of the conventional FET shown in B. The above explanation is for the case where the active layer is n-type, but in the case of p-type, the active layer of the substrate Needless to say, it is sufficient to provide an n-type conductive layer on the main surface opposite to 0. Effects of the Invention As is clear from the above, the present invention realizes an FET with extremely low back gate effect. It is.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view of the structure of a conventional GaAs MKSFET.
FIG. 2 shows a GaAs MESF according to an embodiment of the present invention.
FIG. 3, which is a cross-sectional view of the structure of ET, is a characteristic diagram showing a comparison of the back gate effect of the FET of the present invention and a conventional FET. 1... Semi-insulating GaAs substrate or semi-insulating GaA
s layer, 2...n+ type drain region, 3-- n
+ type source region, 4...n type active layer, 6...
...Source electrode, 6...Drain electrode, 7.
...gate electrode, 10...p-type conductive layer,
11.---Ohmic electrode. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Illustration No. 2 Fig. 3 Fig. Mi

Claims (1)

[Claims] A semi-insulating substrate has an active layer on one main surface, a conductivity type layer different from the active layer on the other main surface of the substrate, and an ohmic electrode is formed on the conductivity type layer. It is. A field effect transistor characterized in that a voltage is applied to the substrate.