JPS60127648A - Stroboscanning type electron microscope - Google Patents

Abstract

PURPOSE:To achieve a test of a long period LSI or the like without n-multifying the generation period and the delay time of a pulse electron beam by providing the detection system of a secondary electron signal with n-pieces of gate circuits synchronized with a clock signal. CONSTITUTION:The output terminal of a secondary electron detector 9 is provided with a gate circuit 18 and picture memories 17. Said memories 17 operate synchronously with a display device 7. The gate circuit 18 makes-and-breaks through a counter 15 synchronously operating with a clock signal of a sample driving circuit 11 giving a periodical change to the sample 14 while selectively supplying respective memories with the signals of the secondary electron detector 9. According to said constitution, a secondary electron signal generated by a pulse electron beam of ''1'' is stored in an M1 picture memory through G1, while a secondary electron signal generated by a pulse of ''2'' is stored in an M2 picture memory through G2 respectively. Thereby, the test of LSI or the like can be achieved without n-multifying a pulse beam generation period.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a strobe scanning electron microscope, and particularly to a strobe scanning electron microscope suitable for testing samples such as logic LSIs.

[Background of the invention]

A strobe scanning electron microscope is constructed by adding a beam pulsing device and a synchronization circuit to a normal scanning electron microscope. This will be explained below using figures.

FIG. 1 is a basic configuration diagram of a strobe scanning electron microscope. The electron beam 2 emitted from the electron gun 1 is transferred to the electron beam 6
is used to focus on the microscopic sample 10, and the scanning coil 8 is used to scan in a rectangular shape in the same manner as a television image pickup tube. When the electron beam collides with a solid, it causes secondary electrons or reflected electrons to be emitted from the solid. These secondary particles or reflected electrons are detected by a detector 9, and the sample image is displayed on a display device 7 operating in synchronization with a scanning coil 8 based on this signal strength. This is the basic principle of a scanning electron microscope.

However, with this scanning electron microscope, samples that change rapidly (
For example, if the position changes from A to B to C as shown in the figure)
When observed, the scanning speed cannot follow the rate of change in the sample, and all changes in the sample are displayed overlappingly. Therefore,
The output of the Norls circuit 12 synchronized with the sample drive circuit 11 which gives periodic changes to the sample is applied to the deflection plate 3 to deflect the electron beam. The t-beam is now pulsed, since the electron beam passes downward only when it is deflected onto the aperture of the aperture 4. When the sample is scanned with this noxious electron beam, the electrons are irradiated only when the sample changes at a certain phase, so all the moving azaleas do not overlap and the sample state changes at a certain point (phase). Only images can be selectively displayed.

Using the above method, in order to observe the entire change in the sample,
A delay circuit 5 is inserted between the oscillator 12 and the drive device 11.

The samples observed with a strobe scanning electron microscope are mainly highly integrated circuits (LSI). Here, the LSI clock signal becomes the trigger signal for pulsed electron beam & generation. This situation is shown in Figure 2.

■ is a clock signal and the period is TC, whose typical value is 100
~500ns. 2 is a signal waveform within the LSI, which in this example has the same period as the clock No. 1g.

■ is a pulsed electron beam created in synchronization with a clock signal. One pulsed electron beam is generated during the period Tc. ■' and ■'' show how the generation of the pulsed electron beam is delayed by the delay circuit 5. ■'' is the maximum delay (Tdl) necessary to observe the entire waveform change.
This is the case when you create . In this example, +ll C and T(1
1 is consistent.

However, the period of the clock signal and the period within the LSI may not match. This especially occurs when testing logic LSIs. Figure 3 shows the observation method when the periods do not match. (2) is a clock signal, and (2) is a signal waveform within the LSI. This signal waveform has a period four times that of the clock signal.

In actual logic LsI, the period is 100 to 1000 times longer. ■' is a signal with a period four times that of the clock signal, and is generated by the frequency conversion circuit 13 (see FIG. 1). ■、■′、
■〃 is a pulsed electron beam produced in synchronization with ■', and the required maximum delay is Td<, which is four times TC.

When observing a waveform of a lock signal having an n-fold period as shown in FIG. 3, the number of pulsed electron beams is l/n. Therefore, in the case of a long cycle such as a logic LSI, (1) n times longer measurement time is required compared to measurement of the same cycle.

(2) Delay circuit with long delay time (for example, Tc is 5
00 ns, neloo = 50 μS).

[Purpose of the invention]

The present invention has been made with attention to the above point, and is a strobe scanning type that enables testing of long-period LSIs, etc., without multiplying the generation period and delay time of the pulsed electron beam by n. Its purpose is to provide an electron microscope.

[Summary of the invention]

In order to achieve the above object, in the present invention, pulsed electron beams are generated in synchronization with a clock signal, and each pulsed electron beam synchronized with the clock signal is configured to share l/n of the entire measurement range. Monodeashi,
This is possible by providing n gate circuits synchronized with a clock signal in the secondary electron signal detection system.

[Embodiments of the invention] Hereinafter, the present invention will be explained in detail with reference to Examples.

FIG. 4 is a diagram illustrating an embodiment of the present invention.

In the conventional example shown in FIG. 1, a frequency conversion circuit 13 was inserted between the sample drive circuit 11 and the delay circuit 5, but the present example does not use a frequency conversion circuit. Instead, a gate circuit 18 and an image memory 17 are provided at the output of the secondary 1L child detector 9. This image memory 17 operates in synchronization with the display device 7. The gate circuit 18ri is opened and closed by a counter 15 that operates in synchronization with the clock signal of the sample drive circuit 11 which gives periodic changes to the sample 14, and the signals from the secondary electron detector 9 are sorted into respective memories. supply

The timing of opening and closing operations of this gate circuit 18 will be explained using FIG. (2) is a clock signal of the sample drive circuit 11; (2) is the internal signal waveform of the logic L8I operating with this clock, and here an example is shown in which the logic L8I operates with a period four times that of the clock signal. (2) indicates the timing of pulsed electron beam irradiation, which has the same period as the clock signal (in the conventional method, the timing of this pulsed beam irradiation was set to four times the period). (2) l is the timing of the pulsed electron beam when the maximum delay is given.

The delay amount Ta is the same amount as the period TC of the clock signal.

■From ■“′ is the gate ((b, G2, G3.G4)
This shows the timing of the operation. The gate opens when voltage is output. ■ is Gl, ■′ is G2
, ■" is the opening/closing signal of the gate of 03, and ■" is the opening/closing signal of the gate of G4 (gates up to number n are shown in FIG. 4).

With this configuration, the secondary electron signal generated by the pulse electron beam of "1" shown by ■ will pass through Gl to the image memory V of Ml, and the secondary electron signal generated by the pulse of "2" will pass through Gl.
2 and are respectively stored in the image memory of M2.

M3. The same goes for M4. This signal acquisition and storage in the memory is performed for a period of about 10 seconds to 1000 seconds, and the S/N ratio is measured.

If you select the memory M1 with the switch 19 (SI) and observe it with the display 16, you can observe the strobe 1?! in the area of '[''c(1) (see is diagram ■).If you select the switch 19, Similarly, TC(2), TC(3)
.

A strobe image in the region T c (4) can also be observed. In other words, with this configuration, 4 images (
n) different strobe images are obtained.

Another embodiment of the invention is shown in FIG. This is an embodiment that focuses on logic tests. Here, the width of the Hanoculus beam does not necessarily have to be as short as ln3, but may be a value smaller than the clock cycle '1'C. This pulse beam is set approximately at the center of the clock period. The gate circuit 18 is opened and closed by the counter 15 as in the previous embodiment. The detected secondary electron signals are stored in the respective memories 22 by opening and closing the gate circuits 18. When data is acquired, the amount of signals stored in this memory is stored in the soft circuit Z.
0 Te") (igll"), and "Low", and if it is 81gh", the lamp 21 is turned on ("L 0 W"
If so, it will not turn on). This display allows us to discuss how the logic progresses with respect to the clock signal. In addition to the lamp display, it is also possible to output to a printer or a round tube. In this test method, a display device 7 is used to illuminate the wiring whose logic is to be tested with an electron beam. Furthermore, if a two-dimensional memory 17 similar to that of the above embodiment is used instead of the memory 22, the electron beam can be scanned over one sample.
High”.

It is also possible to create an image of the "LOW" number (binarized number 1i), making it possible to speed up the science test.

Still another embodiment of the invention is shown in FIG. In contrast to the two embodiments described above, which measured binarization or images, this embodiment measures the logic signal waveform itself. In addition, in this embodiment, the gate circuit 1Q 1r+I 14$
It is opened and closed by a counter 15 synchronized with a clock signal. A -dimensional memory 23 is connected to each gate 18 .

The selection of this memory channel matches the selection of the delay circuit 5.

FIG. 8 shows the relationship between the timing of opening and closing the gate circuit and the irradiation of the pulsed pulse beam in this embodiment. ■ indicates the timing of pulse beam irradiation, and the period T of the clock signal
It is irradiated with C. It is assumed that this logic L8I is operating at four times the cycle of the TC. 3-4.3-4',
3-4" and 3-4"' are gate circuits 18 (
G1. The gate opens only when voltage is being output at the opening timing of G2, Gs, G4). (2) is the pulse beam irradiation timing when a delay (approximately Td/2) is added.

3'-4 and 3'-4' are the timings at which the gate circuit 18 (01 to G4, Ga and 04 are omitted) is opened during pulse beam irradiation in (2). Here, the gate is open only for the period TC, following the timing of pulse beam irradiation. The reason why the gate circuit 18 is operated to follow the pulse beam is that there is a delay of about 100 seconds in detecting secondary electrons. If the pulse beam is delayed while remaining synchronized with the sample clock signal, the signal will be mixed into the next gate when the maximum delay is applied.

Of course, it is also possible to apply this method to the above two embodiments.

(2) is the logical signal waveform to be measured. This waveform is measured as follows. First, the delay of the delay circuit 5 is set to zero, and the signal at this time is stored in the first channel of the memory, Ml, Ml + Ms +M4, through G, , G2°Gs, and G4. Next, a certain amount of delay is given by the delay circuit 5, and the signals at this time are sent to the memory, Ml, Ml,
Ms, store it in the next channel of M4. Next, a certain delay is applied again to store the signal. In this way, the signal is stored with a delay of the period TC of the clock signal. ■ in Figure 9), '9-'D, 'jD are
In this way, the memories Ml , Ml , Ms , M
This is the signal stored in 4. The horizontal axis represents the channel of the one-dimensional memory and corresponds to the delay time created by the delay circuit 5.

By arranging four of these, you can see the entire logic signal (MO in the figure). The display circuit 24 in FIG. 7 is a circuit for performing the above display.

〔Effect of the invention〕

According to the present invention, there are the following advantages compared to the conventional method.

(1) Measurement time can be reduced to l/n.

(2) The delay amount of the delay circuit can be small.

(3) The effectiveness of using electron beams is n times greater.

[Brief explanation of drawings]

Figure 1 is a diagram explaining a strobe SEM, Figure 2 is a diagram explaining the operation of a strobe SEM, Figure 1i143 is a diagram explaining a logic test (long cycle), and Figure 4 is a diagram explaining an embodiment of the present invention. FIG. 5 is a diagram for explaining the operation, FIG. 6 is a diagram for explaining another embodiment of the present invention, FIG. 7 is a diagram for explaining still another embodiment of the present invention, and FIG. 8 is a diagram for explaining the operation. and FIG. 9 are diagrams explaining the operation. DESCRIPTION OF SYMBOLS 1... Electron gun, 2... Electron beam, 3... Deflection plate, 4... Aperture, 5... Delay circuit, 6... Electron lens, 7... Display V-i device, 8... Scanning coil, 9... Secondary electron detector, 11... Sample drive circuit, 12... Pulse circuit, 14... Sample, 15...
・Counter, 16...Display, 17...Image memory, 18...Gelt circuit, Kaya 1 figure potato 20 1- Kaya 5 depression $40 Kayo prisoner Kaya 7 figure

Claims (1)

[Claims] 1. An electron beam irradiation system that generates a pulsed electron beam in synchronization with the excitation period of the sample, a delay circuit for adjusting the timing of pulsed electron beam generation, and a secondary electron signal path including the A strobe scanning electron microscope characterized by having a plurality of gates that open and close in synchronization with the excitation cycle of a sample. 2. The strobe scanning electron microscope according to claim 1, further comprising a memory circuit at a stage subsequent to the gate. 3. Generate a pulse beam in synchronization with the basic excitation period of the sample, and provide n gates If, and sequentially open and close them in synchronization with the basic excitation period to perform a logic L8Ik test in 0 step steps. A strobe scanning electron microscope according to claims 1 and 2, characterized in that: 4. A method of opening and closing the gate via the delay circuit 1
A strobe scanning electron microscope according to claim 3, in which the number F, 6 rows, 1 row, nλ, and % J, 6 LI.