JPH01311553A - Charged particle ray device - Google Patents

Abstract

PURPOSE:To remove error logic due to a logic for detecting true logical information by digitizing a secondary electron signal from a sample at an optional voltage level followed by neglecting a logical signal of the smaller pulse width than the clock width. CONSTITUTION:A primary electron beam 2 emitted from an electron gun 1 spot-irradiates the logical LSI 5 of a sample. A test pattern is impressed on the LSI 5 from a pattern generator to operate with the pulse width more than the clock frequency. Secondary electrons generated from the LSI 5 are detected by a secondary electron detector 6 through an energy analyzer 3 for being memorized by a memory 10. Next, a standardizing judgement circuit 11 digitizes a waveform inputted from a the memory 10 at an optional voltage level followed by neglecting a pulse of the smaller pulse width than the clock pulse width. Thereby, the error detection caused by the noise of a secondary is removed so that the true logic signal can be detected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a charged particle beam device, and particularly to suitable signal processing for an EB tester device.

[Conventional technology]

Electron beam tester device (EB) that applies a scanning electron microscope
The tester device) is used to measure the internal voltage of LSIs instead of the conventional general-purpose tester using the stylus method.

In general, a so-called strobe EB tester device that pulses an electron beam is predominant. This strobe method is a method in which a signal is applied to the sample, and in synchronization with the signal, an electron beam pulsed to an arbitrary width is irradiated onto the sample, and the voltage on the sample is measured from the secondary electron signal generated from the sample. It is. By controlling the sample application signal and the phase of the pulsed electron beam, a rapidly changing sample potential can be converted to a slow one for detection. Here, the pulse width of the electron beam determines the time accuracy of the voltage waveform to be measured.
It is set to 11500 to 1/1oOO in the return t and x periods, and is approximately ins or less. The strobe method EB tester is effective for samples that operate with relatively short repetition periods (1 μs or less), such as LSIs such as memories, but it is effective for samples that operate with long repetition periods (10 μs or more), such as logic LSIs such as gate arrays. Similarly, when measured with high resolution (electron beam pulse width ins or less), the duty ratio of the electron beam becomes 1/10' or less, resulting in a decrease in S/N. This requires a long time for measurement, making the strobe method unsuitable.

The above problem would be solved if an EB tester could develop a secondary electron detection system that irradiates a direct current electron beam without using a strobe method and responds to a sample voltage operating at high speed. This method is called the real-time method. Since the amount of secondary electron signal increases or decreases in proportion to the magnitude of the sample voltage, the sample voltage 4v10v (high/low
) logical information can be detected.

Conventionally, as this type of secondary electron detector, a detector using a combination of a scintillator and a photomultiplier has been used. Recently, microchannel plates (hereinafter abbreviated as MCP) with good high-speed response are also being adopted.

There are reports that realize a real-time method of about 9 MHz using these detectors [see M. Osdrova, E. Mentzen et al., [IC Internal Electron Beam Logic State Analysis], Scanning Electron Microscopy, 1982, 11°, pp. 563-572 (M, O
+qtrow, E, Menza l, at
e r IC-INTERNAL ELECTRON
BEAM LOGIC5TATE ANALYSI
S.J.

5CANNING ELECTRON MICRO5C
OPY/1982/II/(Pages563-572
))], where I10 (h i g h/ 1 o
For the determination of w), an arbitrary slice level is set for the secondary electron signal generated from the sample, and logical information is obtained by determining whether the slice level is greater than or less than that level.

[Problem to be solved by the invention]

In the above conventional technology, the S/N of the secondary electron signal is mainly determined by the probe current Ip of the primary electron and the frequency band f of the detection circuit.
S/NocJ5/, 17. Since the real-time method uses a high-speed amplifier circuit (frequency band is about 100 MHz), the S/N ratio of the secondary electron detection signal deteriorates significantly, making it difficult to detect faithful logic signals from the sample. .

An object of the present invention is to detect a true logic signal by eliminating erroneous detection of a logic signal caused by deterioration of the S/N ratio of a secondary electron signal generated from this sample.

[Means to solve the problem]

The above object is to include means for storing the time of the minimum pulse width applied to the sample, and means for considering the minimum pulse time in the determination conditions of a determination circuit that performs I10 determination from the detected secondary electron signal. This is achieved by

[Effect]

Logic LSI elements are generally operated by one or two basic clocks. Therefore.

The minimum pulse width among the pattern data (logic signals) supplied to the sample (logic LSI) is the clock cycle.

This clock pulse width is stored in the memory at the 0th order, and a signal determined to be 110 (high/low) and normalized from the secondary electron signal amount is searched. Then, the retrieved pulse width is compared with the clock width, and logic signals having a pulse width smaller than the clock width are ignored. This makes it possible to eliminate erroneous logic due to noise.

Through the above-described operations, the logical information of the sample can be detected correctly, and a highly accurate logical tester device can be realized.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. F
A primary electron beam 2 emitted from an E (field emission type) electron gun 1 is narrowly converged by a converging lens 4, and is spot-irradiated onto an arbitrary measurement location of a logic LSI 5, which is a sample.

An arbitrary test pattern is applied to the sample from the pattern generator 7.

This test pattern includes 1, for example, H i h g operating at a clock frequency of 50 MHz and low Ilo (5v /
Ov) patterns are applied continuously in several thousand patterns,
Moreover, various patterns are applied to hundreds of external pins of the LSI element. Therefore, the minimum pulse width τC operating in this logic LSI is 20 ns. Figure 2 (a
) shows the clock waveform.

The secondary electrons generated from the sample are turned into a signal containing sample potential information by the energy analyzer 3, and enter the detector 6. The incident secondary electron signal is amplified by a high-speed video amplifier (frequency band 100 MHz) 8 and converted to a voltage signal. Next, the signal is converted to a digital signal by an ultra-high-speed A/D converter 9 and stored in the memory 10. Remember.

FIG. 2(b) shows the stored waveform. As is clear from the figure, the waveform has a poor S/N ratio due to quantization noise, FE noise, and amplifier noise that depend on the amount of electron beam.

Next, this signal is input to the standardization determination circuit 11. The normalization determination circuit 11 is a circuit that sets a threshold level to an arbitrary voltage level of an input waveform and normalizes it to Ilo. Figure 2 (Q) is.

When the signal is larger than the 6th threshold level, which is the output waveform of the normalization judgment circuit obtained as a result of setting the threshold level to the level shown by the dotted line in Figure 2 (b),
1", and when it is smaller than the threshold level, an output of 0" is output. As shown in the figure, "1/O" logic of 2Qns or less, which is thought to be caused by noise, is detected. This LSI element cannot operate with a clock pulse width (20 ns) or less, and this is clearly an erroneous detection due to noise.

Therefore, this standardization judgment circuit has a judgment condition of τc=2.
Set a condition to ignore 0ns or less.

For example, the logic 1 in FIG. 2(c) (1 in the period of I I+ =
If τC, the logic rr 1 n is output, and if τ1<τC, the logic 110 I+ is output. Similarly, logic II
If the period τo>=τC of Ou, a logic 110 # is output, and if τ0<τC, a logic #I I+ is output. This operation is sequentially performed for all the logic signals shown in FIG. 2(c). The result is as shown in FIG. 2(d). As a result, false logic due to noise can be removed and true logic information can be detected.

〔Effect of the invention〕

According to the present invention, since true logic information can be detected, a highly accurate logic EB tester device can be realized.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing a vertical section of an electron beam irradiation system and blocks of a signal processing system according to an embodiment of the present invention, and FIG. 2 is a pulse waveform diagram illustrating the present invention in detail. DESCRIPTION OF SYMBOLS 1... Electron gun, 2... Secondary electron, 3... Analyzer, 4... Converging lens, 5... Sample, 6... Secondary electron detector. 7... Pattern generator, 8... Video amplifier, 9... Ultra high speed A/D converter, 10... Memory, -...-Next power J 3...A riser- 4...-q Mata Higashi Shinsu 5...Mato Yonago 6...2〉Out of power'! r 橡、を器7 ・ノV GOON RAY! -Old π---Megoso/l...PL development j #1 constant Ayo%1 12 - Meishi Riichi

Claims (1)

[Claims] 1. A charged particle beam is focused narrowly, irradiated onto a sample, and potential information is detected from the charged particles secondarily generated from the sample.
A charged particle beam apparatus for testing a sample, characterized in that a means for converting a detected signal into a logical signal and a minimum operating pulse width of the sample are used as a judgment condition for converting the detected signal into a logical signal. line equipment.