JPH02295046A - Logic analysis electron beam tester device - Google Patents

Abstract

PURPOSE:To perform checking easily by means of comparison at a logical simulator by using plural-stepped phase control circuits arranged in parallel to each other for the phase control of a radiation electron beam converted to a pulse with respect to the phase of a pulse voltage applied to a sample. CONSTITUTION:A test pattern is supplied from a pattern generator 16 to each input terminal of a sample so that an operation test is executed. Conversion of electron beam to pulse is controlled by connecting delay circuits PHI1, PHI2... PHIn to respective outputs of a pulse generator 13 which has plural outputs, and by synthesizing all the outputs using an AND circuit 15 and by applying the outputs synthesized to a blanking plate 2. In this case, the pulse generator 13 and the pattern generator 16, etc., are operated in synchronization with a reference clock oscillator 12. The phase of a logical LSI element, which is a sample, and the phase of the electron beam converted to a pulse are controlled freely by a desired amount at a desired logic step, and so the accuracy of logic detection is enhanced and checking by comparison at a logical simulator is simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a charged particle beam device, and particularly to an electron beam tester device suitable for evaluating logic LSI devices and the like.

[Prior Art] To measure the internal voltage of an LSI device, an electron beam tester (EB tester) using a scanning electron microscope is used instead of a conventional general-purpose tester using a stylus method. Among general conventional devices, the so-called S1-Robo EB tester device that pulses the electron beam is predominant.

The device using this S1Herobo method irradiates the sample with a pulsed electron beam of arbitrary width in synchronization with a signal applied to the sample, and uses the secondary electron signal generated from the sample to By controlling the phase of the sample application signal and the pulsed electron beam, a rapidly changing sample voltage can be converted to a slow one for detection. Here, the pulse width of the electron beam is 1/5 of the repetition period because it determines the time accuracy of the voltage waveform to be measured.
0 to 1/1000, approximately 1. ns or less.

By the way, this EB tester device using the S1-Robo method is effective for samples that operate at a relatively short repetition cycle (1 μs or less), such as LSI devices such as memories, but it is effective for samples that operate at a relatively short repetition cycle (1 μs or less), but for samples that have a long repetition cycle (10 μs or more). For example, in logic LSI devices such as gate arrays, the duty of the electron beam is 1/104 or less, resulting in a significant reduction in the S/N ratio.

This requires a long time to measure, and the logic LS
The strobe method is not suitable for measuring I elements.

As an improvement measure for this,
4. 8 has been proposed. In this conventional example, a pulsed electron beam is generated corresponding to each logic step, and the secondary electron signals of each logic step are detected separately and stored in a memory to be used as logic information. With this method, the EB tester device can solve the problem of S/N ratio and can also be applied to logic LSI devices.

[Problems to be Solved by the Invention] However, the prior art described in section 2 does not take into account phase control for each logical step, and has the following problems.

For example, consider a case where an 8-step logic as shown in FIG. 3 is operating. The pulse beam (b) has an arbitrary delay Φ for each logical step. and irradiate it. Now, when the pulse train is irradiated to the internal wiring of the logic LSI element that performs the logical operation as shown in (c), and the logical value is detected, when the pulse train is irradiated at the time of I Q v+ of the pulse waveform. When I O + is irradiated for a period of '5V', ']' is output. As a result, for the pulse waveform of (c), the logical value (d) (7) is '101101 11
' is detected. Failure analysis can be performed by comparing and collating the detected logical value with CAD data that has been preliminarily simulated.

However, since the gate circuit of a logic LSI device is composed of tens of thousands to millions of transistors, even if the input pulse waveform is an ideal waveform as shown in (c), The pulse waveform inside the element that has passed through many 1-transistors has a delay Td, a decrease in pulse width, and a slow rise and fall, resulting in a waveform as shown in (e), for example.

? When the logic is detected by irradiating the pulse beam (b) on a waveform like this, the detected logic value is '00010011' as shown in (f), which is a completely different logic detection from the above (d). I end up doing it. Conventionally, in order to eliminate this false detection, the delay amount Φ. Even if you scan
Making all the logic consistent with (d) in one measurement is
It was impossible.

The purpose of the present invention is to eliminate the above-mentioned erroneous logic detection,
The object of the present invention is to realize an electron beam tester device that facilitates comparison and verification with a logic simulator.

[Means for Solving the Problem] The above object is to provide a phase circuit that operates independently in synchronization with each step of a reference clock that operates a logic LSI element.
This is achieved by providing each step.

[Operation] If it becomes possible to independently control the phase corresponding to each logical step as in the present invention, as shown in FIG. 3 (9), the first step is the delay amount of Φ■, and the second step is is the delay amount of Φ2, and similarly, the different delay amounts Φ1 to Φ up to the 8th step
8 can be set. Since each delay amount can be set and scanned independently, it can be freely scanned independently in each step, and the delay amount that becomes '1' in each logical step can be set and scanned independently. Easy to search. As a result, the pulsed beam shown in FIG. 3(9) is obtained.

If the pulse waveform (e) is detected with this pulse beam,
The logical value becomes ']0110111' as shown in (h), and the same logical value as the correct logical value (d) can be detected at once.

Furthermore, when measuring multiple LSIs of the same type, you can determine the amount of delay for one, and then calculate the amount of delay for other LSIs of the same type.
Since it can also be used for SI, measurement time can be significantly shortened.

[Example] Hereinafter, a practical example of the present invention will be explained with reference to FIG. The primary electron beam emitted from the electron gun 1 is pulsed by the planking plate 2 and the aperture 3. The aperture is narrowed and irradiated onto the logic T-SI element, which is the sample 6. Then, secondary electrons are generated from the sample and reach the secondary electron detector 7 containing voltage information due to the function of the energy analyzer 5. This signal is amplified to an arbitrary voltage by an amplifier 8, converted to a digital signal by a high-speed AD converter 9, and stored in a memory 1 via a gate circuit 10.

The sample is given any desired test 1 from the pattern generator 16.
A pattern is applied to each input terminal and an operational test is performed. To control the pulsing of the electron beam, a delay circuit Φ■, Φ2...Φn (generally referred to as a phase control circuit 14) is connected to the output of a pulse generator 13 having a plurality of outputs. The outputs are combined by an AND circuit 15 and applied to the blanking plate. These pulse generator 13, pattern generator 16, etc. operate in synchronization with the reference clock oscillator 12.

Regarding phase control of pulsed electron beam using Fig. 2,
This will be explained in more detail.

The output waveform of the reference clock oscillator is shown in (a).

As shown in the figure, considering the case of operation with n-step logic, the output waveform P of the pulse generator has an amplitude of 5V and an arbitrary pulse width in synchronization with the first step of the reference clock lock. Output pulse waveform (b). Then, this output is introduced into the delay circuit Φ1 of the phase control circuit, given an arbitrary delay Φ, and output (c). In addition, the output P2 of the pulse generator synchronized with the evening lock of the second step enters the delay circuit Φ2, giving a delay Φ2 (d), and similarly generates pulses with arbitrary delays up to n steps. Create and input to the AND circuit (e). (f).

Calculating the logical product of all these results in the waveform (9). When this pulse is supplied to the planking plate, the sample is irradiated with the electron beam only when the pulse voltage is Ov, so the waveform of the pulse beam becomes as shown in (h).

Each delay circuit is configured to be able to independently select an arbitrary amount of delay from the outside and also to scan the amount of delay.

8-Furthermore, the detected logic information is stored in memory sequentially for each logic step. Therefore, the gate circuit operates in synchronization with the reference clock. This memory information is imported into a computer and compared with CAD data.
Perform failure analysis.

With the above configuration, it is possible to control the phase of the pulsed electron beam according to each logical step. Further, by scanning the delay amount of each logical step to find the delay amount that becomes '1', it becomes possible to measure the delay time of each pulse. Furthermore,
If the delay amount of each logic step is known in advance by simulation, the delay amount can be set in each delay circuit and logic detection can be performed without scanning the delay circuits.

Although this embodiment has been explained using one stage of planking plates as a method of pulsing the electron beam, it is clear that it can be easily adopted to a method using two stages of deflection plates in which the X and Y directions are orthogonal. be.

[Effects of the Invention] According to the present invention, the phase of the logic LSI element as a sample and the pulsed electron beam can be freely controlled by any amount in any logic chip, thereby improving the accuracy of logic detection. To realize an electronic beer l3 tester device that increases the performance of the electronic beer and facilitates comparison and verification with a logic simulator.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing one embodiment of the present invention, and FIG.
Pulse waveforms of various parts are shown to explain the operation of the present invention, and FIG. 3 is a pulse waveform showing the relationship between logical value detection and pulsed electron beam. Explanation of symbols 1... Electron gun, 2 - Planking plate, 3 Aperture, 4... Objective lens, 5... Energy analyzer, 6... Sample, 7... Secondary electron detector, 8 Amplifier , 9. High-speed AD converter. 10...Game 1~Circuit, 1
1. Memory, 12... Reference clock oscillator, 13.
- Pulse generator, 14... Phase control circuit (ΦU, Φ2, Φ3...Φ. Delay circuit), 15 - AND circuit, 16... Pattern generator.

Claims (1)

[Claims] 1. In an electron beam tester device that narrows down an electron beam, irradiates it onto a sample element, detects the generated secondary electrons, and measures the internal voltage of the sample. A logic analysis electron beam tester device characterized in that the phase control of a pulsed irradiation electron beam is performed by phase control circuits installed in parallel in a plurality of stages. 2. A logic analysis electron beam tester device comprising means for controlling a plurality of stages of phase control circuits installed in parallel in synchronization with each step of a reference clock for operating a sample.