JPH0582606A - Semiconductor integrated circuit testing device - Google Patents

Abstract

PURPOSE:To eliminate the restriction of trigger frequency and improve operability by providing a function for measuring the frequency of a trigger signal in synchronism with the operation of a sample and an automatic dividing function. CONSTITUTION:The device is provided with a frequency measuring means 3 which operates in synchronism with the operation of a sample 1 to be measured, a dividing rate deciding means 5, a programmable dividing means 7, a programmable delay circuit 9 which delays a divided trigger signal 57 based on the set value and a detecting means 11 which detects a secondary element for electronic beams and that detects polarized light caused by electro-optic effects for optical beams in synchronism with the delayed trigger signal 59. The dividing rate deciding means 5 decides a dividing rate which permits the frequencies of the device constituting elements to be lower than normal operation frequencies and that permits maximum frequencies within a rang that permits the detecting means 11 to classify a signal from a sample 1 according to the time. Thus, the device which eliminates the troubles of the operating frequencies and the dividing function and that automatically divides so as to permit the maximum frequencies with excellent operability is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit testing device such as an electron beam device or an optical beam sampling device for measuring the internal operating state of a test sample such as a semiconductor integrated circuit using an electron beam or a light beam, In particular, the present invention relates to a semiconductor integrated circuit test apparatus having a trigger frequency measurement automatic frequency division function and high operability.

An electron beam apparatus is a scanning electron microscope (S
EM) is a device that directly measures the wiring potential inside a semiconductor integrated circuit using the potential contrast (contrast on the SEM image that appears according to the surface potential), and is a sample of the semiconductor integrated circuit to be measured. Measurement is performed by controlling the phase by a programmable delay circuit, sampling, and averaging based on the trigger signal synchronized with the operation of.

The frequency of the trigger signal is to be measured,
Depends on test conditions and test patterns. Generally, the higher the trigger signal, the shorter the time required for the measurement of the electron beam device, but the upper limit of the sampling frequency of the sampling circuit, the bandwidth of the secondary electron signal amplification circuit, the upper limit of the addition frequency of the averaging circuit, and the programmable delay. It must satisfy the constraints such as the upper limit of the operating frequency of the circuit.

The same applies to the light beam sampling device.

[0005]

2. Description of the Related Art One example of the configuration of a conventional electron beam apparatus is shown in FIG.
Shown in. In the figure, the semiconductor integrated circuit testing device detects a secondary electron generated by irradiating a test sample (not shown) such as a semiconductor integrated circuit to be tested with an electron beam to obtain a secondary electron signal 65. A secondary electron signal amplifying circuit 21, a sampling circuit 23 for sampling the amplified secondary electron signal, an averaging circuit 25 for averaging the sampled signals, and a waveform of the test portion based on the averaging value. Etc. and outputs them to the image display system in the apparatus, and a calculation control circuit 29 for designating a delay time for the programmable delay circuit 9 and a trigger synchronized with the operation pattern of the sample such as the semiconductor integrated circuit to be tested. The signal 51 is delayed by the time signal 54 designated by the arithmetic control circuit 29 to generate signals 59 ', 60', and 61 ', which are respectively generated by the sampling circuit 23 and the addition circuit. Programmable supplied to the averaging circuit 25, and a deflector driver 15 delay circuit 9
And a deflector driver 15 which drives the deflector by a trigger signal 61 '. The arithmetic control circuit 2
9 is embodied by a microprocessor or the like.

In this conventional electron beam apparatus, the trigger signal 51 is measured, and the upper limit of the sampling frequency of the sampling circuit 23, the bandwidth of the secondary electron signal amplifier circuit 21, the upper limit of the operating frequency of the averaging circuit 25, and the programmable The delay circuit 9 does not have a function of automatically dividing and measuring in comparison with various restrictions such as the upper limit of the operating frequency. Therefore, when the operating frequency of a sample such as a semiconductor integrated circuit to be measured is high, a fixed frequency dividing circuit is individually provided to generate a trigger signal, or an LSI tester is used to generate a semiconductor integrated circuit or the like. In the case of driving the sample No. 2, a signal having a cycle that is a multiple of the operation cycle of the test pattern was made by the test program and used as the trigger signal.

[0007]

As described above, in the conventional semiconductor integrated circuit test apparatus, when a test sample has a high operating frequency or when it is desired to measure a wide range of phases, a device such as a programmable delay circuit is used. In order to exceed the operating frequency limit of the constituent elements, it is necessary to individually provide a fixed frequency dividing circuit to generate a trigger signal, and to change the test pattern of the trigger sending unit of the LSI tester. Therefore, there is a problem that the external frequency divider circuit is changed or the test pattern is changed for each test sample or according to the type of test, resulting in poor usability.

The present invention solves the above problems,
It is an object of the present invention to provide a semiconductor integrated circuit test device which has no trigger frequency restriction and has good operability by providing a trigger frequency measurement and an automatic frequency dividing function.

[0009]

FIG. 1 illustrates the principle of the present invention. In order to solve the above-mentioned problems, the semiconductor integrated circuit test device of the first feature of the present invention is a semiconductor integrated circuit test for measuring an internal operating state of a sample 1 such as a semiconductor integrated circuit using an electron beam or a light beam. In the apparatus, the frequency measuring means 3 for measuring the frequency of the trigger signal 51 synchronized with the operation of the sample 1 to be measured, the frequency division ratio determining means 5 for determining the frequency division ratio, and the determined frequency division ratio 55 are used. Programmable frequency dividing means 7 for dividing the trigger signal 51 based on the above
And a programmable delay circuit 9 that delays the frequency-divided trigger signal 57 based on a programmable value.
And a detection means 11 for detecting secondary electrons in the case of an electron beam and in the case of a light beam in synchronization with the delayed trigger signal 59, and for detecting the polarization due to the electro-optical effect. The frequency-ratio determining means 5 divides the frequency of the signal from the sample 1 into the highest frequency within the range in which each component of the apparatus operates normally or below and the detection means 11 can classify the signal from the sample 1 in terms of time. Determine the ratio.

A semiconductor integrated circuit test device according to a second aspect of the present invention is the semiconductor integrated circuit test device according to claim 1, wherein the detection means 11 is a secondary electron signal amplifier circuit for amplifying a secondary electron signal. 21, a sampling circuit 23 for sampling in synchronization with the delayed trigger signal 59, and an averaging circuit 25 for averaging the sampled values. ,
The bandwidth of the secondary electronic signal amplifier circuit 21, the upper limit value of the sampling frequency of the sampling circuit 23, the upper limit value of the operating frequency of the averaging circuit 25, and the upper limit value of the operating frequency of the programmable delay means 9 are compared. The frequency division ratio is determined so that the frequency becomes the fastest.

[0011]

In the semiconductor integrated circuit test device of the first feature of the present invention, as shown in FIG. 1, the frequency division ratio determining means 5 has a frequency equal to or lower than the frequency at which each element constituting the semiconductor integrated circuit test device operates normally. In addition, the frequency division ratio is determined so that the frequency becomes the highest within the range in which the resolution of the detection means 11 is preserved.

Therefore, the operating frequency and the resolution of each constituent element of the semiconductor integrated circuit tester can be satisfied, and the frequency can be automatically divided to the highest frequency within the restrictions. A good semiconductor integrated circuit test device can be realized.

Further, in the semiconductor integrated circuit testing device of the second feature of the present invention, as shown in FIG. 2, the frequency division ratio determining means 5 (arithmetic control circuit 27) has the bandwidth of the secondary electronic signal amplifying circuit 21. Compared with the upper limit value of the sampling frequency of the sampling circuit 23, the upper limit value of the operating frequency of the averaging circuit 25, and the upper limit value of the operating frequency of the programmable delay means 9, the frequency becomes the fastest within the range satisfying these constraints. The frequency division ratio is decided accordingly.

Therefore, the operating frequency and the bandwidth of each component of the semiconductor integrated circuit tester can be satisfied, and the frequency can be automatically divided to the highest frequency within the constraints, and the operability is improved. A good semiconductor integrated circuit tester can be realized.

[0015]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 2 shows a block diagram of a semiconductor integrated circuit test apparatus according to an embodiment of the present invention. In the figure, the same parts as those in FIG. 4 (conventional example) are designated by the same reference numerals to simplify the description.

Referring to FIG. 2, the semiconductor integrated circuit testing apparatus of this embodiment has a secondary electronic signal amplifier circuit 21, a sampling circuit 23, an averaging circuit 25, an arithmetic control circuit 27, a frequency measuring circuit 3, a programmable frequency dividing circuit 7. , A programmable delay circuit 9 and a deflector driver 15. It should be noted that this figure shows only the components directly related to the present invention, and an electron beam lens barrel system for irradiating an electron beam, an energy analyzer system, an image display system, and a waveform display system are omitted. The function of the frequency division ratio determining means 5 is realized by the arithmetic control circuit 27 implemented by a microprocessor or the like.

The frequency measuring circuit 3 measures the frequency of the trigger signal synchronized with the operation pattern of the semiconductor integrated circuit 1 to be tested, and transmits the result to the arithmetic control circuit 27. The arithmetic control circuit 27 previously sets the upper limit value of the sampling frequency of the sampling circuit 23, the bandwidth value of the secondary electronic signal amplifier circuit 21, the upper limit value of the averaging average frequency of the averaging circuit 25,
The limit values of the operating frequency of the programmable delay circuit 9 are respectively held in internal memory, and the trigger frequency obtained by the frequency measuring circuit 3 and the values held in these internal memories are compared, and each of these constituent elements is calculated. The frequency division ratio of the programmable frequency dividing circuit 7 is set so that the operating frequency and the bandwidth are restricted and the frequency becomes the highest speed within the restriction. The programmable frequency dividing circuit 7 divides the frequency of the trigger signal 51 input according to the frequency dividing ratio 55 set by the arithmetic control circuit 27. The programmable delay circuit 9 delays the frequency-divided trigger signal 57 by the time signal 54 designated by the arithmetic control circuit 27, and outputs signals 59, 60, and 6.
1 is generated and supplied to the sampling circuit 23, the averaging circuit 25, and the deflector driver 15, respectively. The deflector driver 15 drives the deflector so as to irradiate the semiconductor integrated circuit 1 with the electron beam in synchronization with the delayed trigger signal 61. Further, the sampling and arithmetic mean of the secondary electron signals detected by this are the trigger signal 59,
It is performed in synchronization with 60.

Next, the operation of this embodiment will be described with reference to the signal waveforms of the respective parts in FIG. FIG. 3 (1) shows a signal waveform of a test sample 1 such as a semiconductor integrated circuit to be tested which is to be measured. First, it is assumed that the trigger signal 51 synchronized with the operation pattern of the test sample 1 has the waveform shown in FIG. The frequency measuring circuit 3 measures the frequency of the trigger signal 51 and transmits it to the arithmetic control circuit 27. The arithmetic control circuit 27 satisfies the operating frequency and the constraint conditions of the bandwidth of each component and at the highest frequency. The frequency division ratio is set so as to operate, and the signal 55 is supplied to the programmable frequency dividing circuit 7. In the illustrated example, the frequency division ratio is set to 1/2, and the programmable frequency division circuit 7 outputs the trigger signal 57 having a waveform as shown in FIG. In the programmable delay circuit, the time 54 designated by the arithmetic control circuit 27
To produce signals 59, 60, and 61 delayed by only.
The trigger signal 61 supplied to the deflector driver 15 is as shown in FIG.
As shown in (4), the trigger signal 59 supplied to the sampling circuit 23 is a signal delayed by φ _i in order to control the phase of the electron beam pulse with which the test sample 1 is irradiated. ), In addition to the phase φ _i , Δ1 (time from the electron beam irradiation until the secondary electron signal 65 (see (5) in the figure) has a peak value, which is a value unique to the apparatus) It is a delayed signal. in this way,
The secondary electron signal 65 corresponding to the phase φ _i is sampled to obtain A / D-converted digital data D _i (waveform of the signal 67; see FIG. 3 (7)), and the averaging circuit 25 performs a predetermined number of times. Is averaged to obtain arithmetic mean data of one phase point corresponding to the phase φ _i . The waveform is measured by changing the analysis voltage and the phase φ _i of the energy analyzer (not shown) and performing the operation over the required phase range of the signal waveform in FIG. 3 (1). You can

[0019]

As described above, according to the present invention,
Limitation of operating frequency and resolution of each component of the semiconductor integrated circuit test device, for example, bandwidth of secondary electron signal amplification circuit, upper limit value of sampling frequency of sampling circuit, upper limit value of addition average frequency of addition averaging circuit, and programmable Since the frequency division ratio is determined so that the operating frequency of the delay means satisfies the upper limit value and the frequency becomes the fastest within the constraints, optimum automatic frequency division can be performed and the trigger frequency It is possible to provide a semiconductor integrated circuit testing device which can flexibly respond to changes in the above and has good operability.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a configuration diagram of a semiconductor integrated circuit test apparatus according to an embodiment of the present invention.

FIG. 3 is a signal waveform diagram of each part of the semiconductor integrated circuit test apparatus of the present invention.

FIG. 4 is a configuration diagram of a conventional electron beam apparatus.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Test sample (semiconductor integrated circuit etc.) 3 ... Frequency measuring means 5 ... Dividing ratio determining means 7 ... Programmable dividing means 9 ... Programmable delay circuit 11 ... Detecting means 13 ... Beam generating means 15 ... Deflector driver 21 ... 2 Next electronic signal amplification circuit 23 ... Sampling circuit 25 ... Addition and averaging circuit 27, 29 ... Arithmetic control circuit 51 ... Trigger signal 53 ... Measurement frequency 54 ... Delay time 55 ... Dividing ratio 57 ... Trigger signal after dividing 59, 59 ' ... Delayed trigger signal (for sampling) 60, 60 '... Delayed trigger signal (for addition and averaging) 61, 61' ... Delayed trigger signal (for deflector drive) 65 ... Secondary electron signal

Claims (2)

[Claims] 1. A semiconductor integrated circuit test apparatus for measuring an internal operating state of a sample (1) such as a semiconductor integrated circuit by using an electron beam or a light beam, which is used for the operation of the sample (1) to be measured. Frequency measuring means (3) for measuring the frequency of the synchronized trigger signal (51),
Frequency division ratio determination means (5) for determining the frequency division ratio, programmable frequency division means (7) for frequency dividing the trigger signal (51) based on the determined frequency division ratio (55), and after the frequency division. A programmable delay circuit (9) that delays the trigger signal (57) based on a programmable value, and a secondary electron in the case of an electron beam, in the case of an electron beam, in synchronization with the delayed trigger signal (59). In some cases, it has a detection means (11) for detecting polarized light due to an electro-optical effect, and the frequency division ratio determination means (5) has a frequency equal to or lower than a frequency at which each component of the apparatus normally operates, and the detection means. (11)
Is a semiconductor integrated circuit test apparatus, wherein the frequency division ratio is determined so that the signal from the sample (1) has the highest frequency within a range in which it can be separated in time. 2. The detection means (11) comprises a secondary electron signal amplifier circuit (21) for amplifying a secondary electron signal, and a sampling circuit (Sampling circuit for sampling in synchronization with the delayed trigger signal (59). 23) and an averaging circuit (25) for averaging the sampled values, wherein the frequency division ratio determining means (5) has the bandwidth of the secondary electronic signal amplifying circuit (21) and the sampling circuit. (23) Upper limit of sampling frequency, the averaging circuit (2
5. The frequency division ratio is determined so that the frequency becomes the highest speed by comparing with the upper limit value of the operating frequency of 5) and the upper limit value of the operating frequency of the programmable delay means (9). Semiconductor integrated circuit test equipment.