JP2552185Y2 - IC test equipment - Google Patents

Description

[Detailed description of the invention] "Industrial application field" This invention is based on driving IC (semiconductor integrated circuit).
By irradiating an electron beam on the IC wiring formation surface, the IC
The present invention relates to an IC test apparatus having a function of testing a test.

[Prior art] As a test method of an IC, the IC package is opened, the IC is driven, and at the same time, an electron beam is irradiated on an IC wiring forming surface to discharge secondary electrons from the IC wiring forming surface. There is a method of measuring a signal waveform applied to an IC by converting a next electron into an electric signal and detecting a potential state of a wiring forming surface of the IC.

FIG. 3 shows an example of a conventional IC test apparatus having such an electron beam IC test function. The test apparatus is an IC test circuit section.
10 and electron beam IC test section 20.

In the IC test circuit section 10, test pattern data TPD and an original trigger signal TRO, which will be described later, are obtained from the pattern generator 12 based on the timing signal from the timing generator 11, and the applied pattern data of the test pattern data TPD is obtained. Is supplied to the waveform generating circuit 14, and a signal waveform is obtained from the waveform generating circuit 14 by the clock obtained from the timing generator 11 and supplied to the waveform generating circuit 14. The signal voltage is converted into a signal voltage such as a level and supplied to IC1, and the signal voltage obtained from IC1 is compared with a reference voltage in a comparator 17, and the comparison output is supplied to a logical comparison circuit 18 to generate a timing signal. The test pattern data obtained from the pattern generator 12 is obtained by the strobe signal obtained from the generator 11 and supplied to the logic comparison circuit 18. Logical comparison with the expected value pattern data in the data TPD.

The IC 1 has a package opened so that an electron beam can be irradiated to the wiring forming surface 1 a.In the electron beam IC test unit 20, an electron beam 22 from an electron gun 21 is irradiated by a beam blanker 23 as described below. Is converted into a primary electron pulse beam 24 by the blanking control, and the primary electron pulse beam 24 is controlled by the deflection scanning means 25 to irradiate the wiring forming surface 1a of the IC 1 to emit secondary electrons 26 from the wiring forming surface 1a. Then, the secondary electrons 26 are detected by the secondary electron detecting means 27 and converted into electric signals.

The original trigger signal TRO obtained from the pattern generator 12 of the IC test circuit section 10 is used for the above-described blanking control in the electron beam IC test section 20.
In the electron beam IC test section 20, the original trigger signal TRO is supplied to the synchronous oscillator 28, and the original trigger signal TRO is supplied from the synchronous oscillator 28 as shown in FIG.
A clock CLA synchronized with TRO is obtained, and the clock CLA
The original trigger signal TRO is supplied to a pre-stage delay circuit 31 constituted by a counter. The pre-delay circuit 31 supplies the original trigger signal TRO to the original trigger signal TRO by a control circuit 29 constituted by a CPU of a clock CLA as shown in FIG. A trigger signal TRA delayed by a time τ ₁ corresponding to a predetermined number of cycles is obtained, and the trigger signal TRA is supplied to a fine adjustment delay circuit 32 constituted by an analog circuit, and the fine adjustment delay circuit
As shown in FIG. 4, a trigger signal TRB delayed from the trigger signal TRA by a time τ ₂ determined by the control circuit 29 within one cycle of the clock CLA is obtained, and the trigger signal TRB is pulsed. The pulse BLP is supplied to the generator 33 and a pulse BLP having a sufficiently narrow pulse width delayed from the trigger signal TRB by a predetermined time as shown in FIG. 4 is obtained from the pulse generator 33. The pulse BLP is supplied to the beam blanker 23. The beam blanker 23 is unblanked during the pulse width period of the supplied pulse BLP, and the primary electron pulse beam 24 is irradiated on the wiring forming surface 1a of the IC 1 as described above.

As an example, the period of the clock CLA is set to 10 nanoseconds,
That preceding stage delay circuit 31 is to be able to change the time tau ₁ above in units of 10 ns, and the fine delay circuit 32 so as to be able to vary the time tau ₂ in units of 10 picoseconds To be.

[Problem to be Solved by the Invention] In the conventional IC test apparatus shown in FIG. 3, the original trigger signal is used to obtain the clock CLA for delaying the original trigger signal TRO in the pre-stage delay circuit 31 as described above. TRO
A synchronous oscillator 28 driven by a synchronous oscillator 28 is used. However, in general, the stability of the oscillation cycle of the synchronous oscillator is not good, and the cycle of the output pulse changes considerably. Therefore, in the conventional IC test apparatus, the period of the clock CLA from the synchronous oscillator 28 changes considerably, which causes the trigger signal TRA from the preceding delay circuit 31, the trigger signal TRB from the fine adjustment delay circuit 32, and the pulse generation. Since the timing of the pulse BLP for blanking control from the detector 33 changes considerably from the expected timing,
In 20 it is difficult to set the timing with high precision, for example, in units of 10 picoseconds, and perform waveform measurement.In particular, as the delay time τ ₁ in the pre-stage delay circuit 31 is longer, the change in the cycle of the clock CLA is accumulated Therefore, there is an inconvenience that the tendency becomes more remarkable.

Therefore, this invention has an electron beam IC test function.
In an IC test apparatus, a timing measurement can be set with high precision in an electron beam IC test section so that waveform measurement can be performed.

[Means for Solving the Problem] An IC comprising a variable delay circuit to which an original clock CLO obtained from a timing generator 11 of an IC test circuit section 10 is inputted.
A clock CLA which receives the original trigger signal TRO obtained from the test circuit section 10 and which is a delay output of the variable delay circuit 34
Is provided, and a variable delay circuit 34 is provided.
Is the input of the comparison output of the phase comparison circuit 35 and the original trigger signal TR
Outputs the clock CLA whose rising edge or falling edge coincides with O, and the original trigger signal TRO is a variable delay circuit.
A delay circuit 31 for delaying by a time corresponding to a predetermined number of cycles of the clock CLA from 34, and a trigger signal from the delay circuit 31 having a time delay shorter than the delay time in the delay circuit 31 Fine adjustment delay circuit
An IC test apparatus comprising: a pulse generator 33 that outputs a pulse for controlling whether or not to irradiate an electron beam driven by a trigger signal from the fine adjustment delay circuit 32 on the wiring formation surface of the IC. Was configured.

"Operation" The IC test circuit of the IC test equipment that forms the signal waveform supplied to the IC from the applied pattern data and logically compares the signal voltage obtained from the IC with the expected value pattern data is subjected to timing calibration. The clock obtained from the timing generator has a very stable period.

In the IC test apparatus of the present invention configured as described above, a clock having a substantially constant cycle obtained from the timing generator of the IC test circuit section is used as an original clock, and the IC test circuit section is connected to the variable delay circuit 34. An original clock CLO obtained from the timing generator 11 of 10 is input, and an original trigger signal TRO obtained from the IC test circuit unit 10 is input to the phase comparator 35, and a delay output of the variable delay circuit 34 is used. A certain clock CLA is input, the comparison output of the phase comparison circuit 35 is input to the variable delay circuit 34, and the original trigger signal TRO
A clock CLA whose rising edge or falling edge is coincident with respect to the output signal is output, and the original trigger signal TRO is delayed via the pre-stage delay circuit 31 for a time corresponding to a predetermined number of cycles of the clock CLA output. Further, in the fine-adjustment delay circuit, the trigger signal from the preceding delay circuit is delayed by a time shorter than the delay time in the preceding-stage delay circuit.
Drives a pulse generator that outputs a pulse that controls whether or not to irradiate the wiring formation surface of the IC, so a trigger signal from the preceding delay circuit, a trigger signal from the fine adjustment delay circuit, and blanking from the pulse generator The timing of the control pulse can be set to an intended timing, and the waveform can be measured by setting the timing with high accuracy in the electron beam IC test unit.

In particular, the original clock CLO obtained from the timing generator 11 of the IC test circuit unit 10 is input to the variable delay circuit 34, and a phase comparison circuit 35 is provided, which receives the original trigger signal TRO obtained from the IC test circuit unit 10. The clock CLA, which is the delay output of the variable delay circuit 34,
The comparison output of 5 is input to the variable delay circuit 34 and the original trigger signal T
A clock CLA whose rising edge or falling edge coincides with RO is output, and the original trigger signal TRO is passed through the pre-delay circuit 31 for a time corresponding to a predetermined number of cycles of the clock CLA output. By delaying, the original trigger signal TRO caused by the delay generated from the time when the original trigger signal TRO reaches the electron beam IC test section 20 from the IC test circuit section 10
And the clock CLA used as a reference for counting the delay time in the pre-stage delay circuit 31, eliminates the
High precision blanking control pulse BL in test section 20
P can occur.

[Embodiment] FIG. 1 is an example of an IC test apparatus according to the present invention.
125MHz clock CLO as the original clock
It is the same as that of the conventional IC test apparatus shown in FIG. 3 except that it is sent to the test section 20. Since the IC test circuit section 10 is subjected to timing calibration, the original clock CLO obtained from the timing generator 11 has a significantly stable cycle. A mechanism for irradiating the wiring forming surface 1a of the IC 1 with the primary electron pulse beam 24 of the electron beam IC testing unit 20, and for detecting the secondary electrons 26 emitted from the wiring forming surface 1a and converting them into electric signals. The configuration of the third
This is the same as that of the conventional IC test apparatus shown in the figure.

The original clock CL obtained from the timing generator 11 of the IC test circuit unit 10 and transmitted to the electron beam IC test unit 20
O is a variable delay circuit 3 provided in the electron beam IC test section 20.
4 and is delayed so as to have a predetermined phase relationship with respect to the original trigger signal TRO obtained from the pattern generator 12 of the IC test circuit section 10 and sent to the electron beam IC test section 20. Specifically, the original trigger signal TRO and the variable delay circuit 3
4 is supplied to the phase comparison circuit 35 to compare the phases of the two, and the comparison output is supplied to the variable delay circuit 34 as a signal for determining the amount of phase shift, and the original trigger signal TR
The phase difference between O and the clock CLA is made a phase difference as shown in FIG. 2 determined by the control circuit 29 constituted by the CPU. Here, since the original clock CLO is almost constant from the cycle as described above, the cycle of the clock CLA from the variable delay circuit 34 is also almost constant.

Further, the comparison output of the phase comparison circuit 35 is input to the variable delay circuit 34, and a clock CLA whose rising edge or falling edge coincides with the original trigger signal TRO is output. Eliminating the delay difference between the clock CLA serving as the reference for counting the delay time in 31 allows the electron beam IC test unit 20 to generate a high-precision blanking control pulse BLP. That is, the original trigger signal TRO is generated and sent out via the pattern generator 12 of the IC test circuit section 10 and reaches the electron beam IC test section 20, and when viewed from the electron beam IC test section 20, the original trigger signal TRO is generated. Compared with the clock CLO, delay variation and jitter are large. Where the variable delay circuit
The original trigger signal TRO is delayed by delaying the original clock CLO by 34.
This compensates for the adverse effects caused by delay variation and jitter, which contributes to the generation of a high-precision blanking control pulse BLP in the electron beam IC test unit 20.

The clock CLA from the variable delay circuit 34 and the original trigger CLO
Is supplied to a pre-stage delay circuit 31 constituted by a counter, and corresponds to the number of periods determined by the control circuit 29 of the clock CLA with respect to the original trigger signal TRO from the pre-stage delay circuit 31 as shown in FIG. trigger signal TRA delayed by time tau ₁ to obtain, the trigger signal TRA trigger signal as shown in Figure 2 from the fine delay circuit 32 is supplied to the fine delay circuit 32 constituted by an analog circuit TRA , A trigger signal TRB delayed by a time τ ₂ determined by the control circuit 29 within one cycle of the clock CLA is obtained, and the trigger signal TRB is supplied to the pulse generator 33 and Trigger signal as shown in FIG.
A pulse BLP having a sufficiently narrow pulse width delayed by a certain time with respect to TRB is obtained, and the pulse BLP is supplied to the beam blanker 23, and during the pulse width period of the pulse BLP, the beam blanker 23 is unblanked and the primary electron pulse is generated. The beam 24 is irradiated on the wiring forming surface 1a of the IC1.

Therefore, the trigger signal TRA from the pre-stage delay circuit 31
The timing of the trigger signal TRB from the fine adjustment delay circuit 32 and the timing of the pulse BLP for blanking control from the pulse generator 33 can be set to the desired timing, and the electron beam
The waveform can be measured by setting the timing with high accuracy in the IC test section 20.

In the example shown in FIG. 1, the original trigger signal TRO is
Although it is obtained from the 0 pattern generator 12, it may be obtained from the timing generator 11 of the IC test circuit unit 10.

[Effects of the Invention] As described above, the IC test apparatus of the present invention inputs the original clock CLO obtained from the remarkably stable timing generator 11 of the IC test circuit unit 10 to the variable delay circuit 34, and performs phase comparison. The circuit 35 is provided with an original trigger signal TRO obtained from the IC test circuit section 10 and a clock CLA which is a delay output of the variable delay circuit 34.
The comparison output of 5 is input to the variable delay circuit 34 and the original trigger signal T
A clock CLA whose rising edge or falling edge coincides with RO is output, and the original trigger signal TRO is passed through the pre-delay circuit 31 for a time corresponding to a predetermined number of cycles of the clock CLA output. A configuration to delay is adopted. Thereby, the original trigger signal TRO caused by the delay generated until the original trigger signal TRO reaches the electron beam IC test unit 20 from the IC test circuit unit 10 and the clock used as a reference for counting the delay time in the pre-stage delay circuit 31 The electron beam IC test unit 20 can generate a high-precision blanking control pulse BLP by eliminating a delay difference from the CLA.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of the IC test apparatus of the present invention, FIG. 2 is a time chart for explaining its operation, FIG. 3 is a block diagram showing an example of a conventional IC test apparatus, and FIG. FIG. 4 is a time chart for explaining the operation.

Claims (1)

(57) [Scope of request for utility model registration] A variable delay circuit to which an original clock obtained from a timing generator of the IC test circuit section is inputted, wherein an original trigger signal obtained from the IC test circuit section is inputted, and a delay output of the variable delay circuit is inputted. A variable delay circuit receives the comparison output of the phase comparison circuit and outputs a clock whose rising edge or falling edge matches the original trigger signal, A delay circuit for delaying the original trigger signal by a time corresponding to a predetermined number of cycles of the clock from the variable delay circuit, wherein the trigger signal from the delay circuit is shorter than the delay time of the delay circuit in the delay circuit; A fine adjustment delay circuit for delaying time is provided. Whether or not the electron beam is irradiated on the wiring formation surface of the IC by being driven by a trigger signal from the fine adjustment delay circuit IC test apparatus characterized by comprising a pulse generator for outputting a control pulse.