JPH0244270A - Method for measuring potential of wiring of semiconductor device - Google Patents

Abstract

PURPOSE:To stably measure the potential of wiring without generating charge on an insulating protective film by dividing a phase into the high and low regions of the level of a logic timing waveform within a measuring cycle and irradiating both regions with electron beam in timing wherein the phase is rearranged so that both regions are made alternate. CONSTITUTION:The node name of the corresponding measuring point and logic timing data are extracted from a logic timing file 5 storing the result of logical simulation 4 by key input by a control computer 2 to be displayed on a display device 1. The number N of measuring points, an irradiation pulse width, a measuring cycle and a start phase are inputted. Low and high level phase point queues are preliminarily prepared in the computer 2 and phase point values are alternately drawn out from the matrice at the time of measurement to be sent to a delay generator 7 and, after predetermined delay, voltage is applied to a deflector 9 through a driver 8 to irradiate a sample 10 with beam. The secondary electron from the sample 10 is caught by a detector 11 and a detection signal is processed by a signal processing circuit 12 to calculate the potential at a measuring point. By this constitution, an insulating film is irradiated with electron beam to stably know the potential of wiring without charging said film.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention provides logic timing information corresponding to a node at which a wiring potential of a semiconductor device is to be measured from a database storing logic timing waveforms. A wiring potential of a semiconductor device in which a waveform is extracted, an electron beam is irradiated to the semiconductor device based on the extracted logic timing waveform, and a wiring potential is measured based on a detection signal of secondary electrons generated from the semiconductor device. Regarding the measurement method.

(Prior Art) Generally, the surface of an integrated circuit element is PSG (phosp
It is covered with an insulating protective film such as horsillcate glass) or Si3N4. Therefore, when an electron beam is irradiated onto the insulating protective film to measure the wiring potential with an electron beam tester (hereinafter also referred to as an EB tester), a charge-up phenomenon occurs. For this reason, conventionally, a method of removing the insulating protective film and then measuring the wiring potential of a semiconductor device has been widely used. However, the process of removing the insulating protective film on the chip surface is complicated and may affect the operation of the element. Therefore, a technology has been developed to measure the voltage waveform of the element with the insulating protective film attached, that is, a technology to observe the wiring potential as a capacitively coupled potential contrast. To observe this capacitively coupled potential contrast, in order to avoid charge-up due to electron beam irradiation on the insulating protective film directly above the measurement point, the phase of one cycle is changed by changing the phase at regular intervals, and when the phase is finished, it returns to the original state. There is a high-speed phase scanning method in which returning to the phase is repeated a predetermined number of times, and a random phase scanning method in which the phase value is randomly changed instead of sequentially changing the phase by a fixed amount.

(Problems to be Solved by the Invention) As described above, the method of removing the insulating protective film before measurement has been widely used, but it is necessary to know the type and thickness of the insulating film in advance. Furthermore, with the recent trend towards higher integration, multilayer wiring structures have been adopted, and in some cases, it is not possible to obtain the necessary information only from the wiring directly under the insulating protective film.

Furthermore, the high-speed phase scanning method aims to reduce the amount of irradiation per -phase point to prevent charging, that is, charge-up. The problem with this method is that, first of all, it is unclear to what extent the beam irradiation amount must be reduced, and it is extremely difficult to unambiguously determine this value. Second, reducing the amount of beam irradiation is equivalent to reducing the amount of detected signals, which leads to a decrease in the S/N ratio and may lead to deterioration of the 1TF1 determination accuracy.

On the other hand, the random phase scanning method is based on the idea that by randomly changing the phase, the probability that the potential at the measurement point changes every time the beam irradiation phase changes is increased. However, although this probability increases statistically, it is never 100%.
It will never become.

Furthermore, this method is effective when the low (Low) and high (HLgh) levels appear evenly, such as in a logic timing waveform, but it is difficult to suppress the effects of charging when using a single shot pulse waveform. The problem is that it can't be done.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for measuring the wiring potential of a semiconductor device, which allows stable measurement at any position without causing a charge-up phenomenon even when an electron beam is irradiated from above an insulating protective film. .

[Structure of the invention]

(Means for Solving the Problem) The present invention extracts a logic timing waveform corresponding to a measurement point at which a wiring potential of a semiconductor device is to be measured from a database storing logic timing waveforms, and In a method for measuring the wiring potential of a semiconductor device in which the semiconductor device is irradiated with an electron beam based on a logic timing waveform and the wiring potential is measured based on the detection signal of secondary electrons generated from the semiconductor device, the wiring potential is measured within the wiring potential measurement period. The phase of the logic timing waveform is divided into high-level and low-level regions, and the high-level and low-level regions are alternated in terms of the electron beam irradiation timing. The feature is that the phase is rearranged and measured.

(Function) According to the method for determining Δ1 of the wiring potential of a semiconductor device according to the present invention configured as described above, an area where the level of the logic timing waveform is at a high level and an area where the level is at a low level is determined within the measurement cycle of the wiring potential. The phases are divided into n1, and the phases are rearranged so that the divided high-level regions and low-level regions alternate in terms of the electron beam irradiation timing.
to be determined. This allows stable measurement at any position without generating electrical charge on the insulating protective film.

(Example) FIG. 1 shows the wiring potential of 7rP+ of the semiconductor device according to the present invention.
A specific example of an electron beam tester (hereinafter referred to as an EB tester) that implements the method is shown below. In this EB tester, first, the node name of the measurement point to be measured is entered manually via the display 1. Based on the input node name, the control computer 2 extracts the corresponding node name and the logic timing data corresponding to the related node name from the logic timing file 5 that stores the results of the logic simulation 4, and displays them on the display 1. to be displayed. Then, display the data such as the number of phase points to be measured (N), irradiation pulse width, measurement period, starting phase, etc.
Enter via. After the input, the control computer 2 divides the logic timing waveform into a high-level region and a low-level region within the measurement cycle of the node to be measured. That is, in the logic timing waveform shown in FIG. 2, areas I and ■ are low level areas, and area ■
, ■ is the area where the level is high. Changes in the wiring potential under the insulating protective film appear on the protective film due to capacitive coupling.

This change in wiring potential, that is, the potential contrast, is stable immediately after the wiring potential changes. Therefore, the timing of the irradiation beam is shifted sequentially from TI (instead of the conventional measurement method, T (wiring potential is low level) - T, (wiring potential is high level) → T3 (low level) → T4 (high level) →
By alternately repeating regions I and IF within the measurement period, changes in the wiring potential appear on the protective film due to capacitive coupling without charge-up.

After areas I and If are completed, move areas ■ and ■ to TN.
/2+1 (wiring potential is low level) - TN/2+2(
Wiring potential is high level) -”N/2+3 (low level)
→T (high level) Repeat alternately like N/2+4 (here, N is an even number).

In order to realize such a phase change, a queue of low-level phase points is created in advance in the control computer 2: (T1.T3゜” ”
"TN/2+I = TN/243'""T)
J-1) 5 ゛High level phase point queue: (T2.T4゜T
..., T, T...T)
6' N/2 N/2+2'
N, and during measurement, phase point values are alternately extracted from the above queue and output to the delay generator graph shown in FIG.

Normally, in an EB tester, since the repetitive phenomenon is fixed at /fp1, an input signal that causes the logic timing waveform shown in FIG. 2 to occur repeatedly is applied to the sample 10.

Here, the timing at the left end of the timing chart in FIG. 2 is assumed to be t-0. The timing of t-Q is determined from the IC driver 6 to the delay generator 7 as shown in FIG.
It is always sent as a trigger signal, and the operation of the sample 10 and the delay generator 7 are always synchronized. Next, when the timing (t-T1) of the irradiation beam is sent from the queue determined as described above, the delay generator 7 sends a trigger signal to the driver 8 at a timing that is 1-0 multiplied by T1. occurs.

Then, a voltage is applied to the deflector 9 by the driver 8 and the beam is irradiated. Similarly, a phase is selected from the queue so that the potential changes each time the beam is irradiated, and this is sent to the delay generator tough. The delay generator 7 triggers the driver 8 at a timing when -0 is delayed by the amount of the sent phase, and emits a beam (see FIG. 2). Repeat this.

When the sample 10 is irradiated with the beam, secondary electrons are emitted from the sample 10. This secondary electron is detected by a detector 11. The detection signal of the detector 11 is then transmitted to the signal processing circuit 1.
2, and the potential at the measurement point is calculated.

FIG. 3 shows the results obtained when the measurement phase region is fixed at n1 without sequentially changing the phase points in exactly the same way as in the conventional method.

It can be seen that at high levels a stable waveform is shown, whereas at low levels the waveform is distorted due to the charge-up effect on the insulating protective film. Furthermore, it can be seen that at the low level in the second cycle, the influence of the charge-up in the first cycle overlaps.

FIG. 4 shows the results of waveform measurements performed using the method of the present invention.

That is, this is a measured waveform obtained when the phase is alternately changed at the low/high level of the first cycle, and then the low/high level of the second cycle is measured in the same manner. In this way, the charge-up effect does not appear in either the low or high level regions, and a stable 1j constant can be achieved.

In addition, in FIG. 2, the case where the number of low-level measurement points and the number of high-level measurement points within the measurement period are equal was explained.
If the number of measurement points in each case is different, this is possible by repeating one point in the smaller queue.

In other words, it is sufficient to repeat the above 1 point for the missing amount.

Further, in order to obtain a desired SIN ratio, after changing the phase of the queue described above, it can be obtained by repeating this phase change.

Note that Fig. 4 shows an example where the low and high level ranges are equal in the measurement phase region, but if they are different, by overlapping the phase points on the narrow level side of the range, exactly the same stable result can be obtained. Waveform measurement is possible.

As described above, according to this embodiment, the logical waveform corresponding to the measurement node name is extracted from the CAD database of logical simulation results, and within the measurement phase range,
By sequentially arranging the measurement phases so that regions with low levels and regions with high levels alternate, it is possible to stably determine M at any position without causing charge-up even on the insulating protective film. .

Note that the link between the EB tester and the CAD system shown in Figure 1 is via LAN (Local AreaNet
The CAD database may be accessed directly by the CAD database, or the logic timing file may be output to a medium such as a magnetic tape and then read into the control computer 2. On the other hand, by linking with a CAD system via LAN, if there is no logic simulation result at the corresponding node, logic simulation can be executed immediately, which is a great advantage.

〔Effect of the invention〕

According to the present invention, even if an electron beam is irradiated from above the insulating protective film, the wiring potential can be stably measured at any position without causing a charge-up phenomenon.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an EB tester that implements the method of measuring the wiring potential of a semiconductor device according to the present invention, and FIG. 2 shows the logic timing waveform extracted from the logic simulation results and the timing of the EB tester's irradiation beam. Figure 3 is a graph showing the potential on the Al1-Si wiring measured from above the insulating film using the conventional method. Figure 4 is the same as the n1 constant in Figure 3. It is a graph when the wiring potential is measured using the method according to the present invention on the nj fixed point of . 1...Display, 2...Control computer, 3...
・Logic description file, 4...Logic simulation,
5... Logic timing file, 6... IC driver, 7... Delay generator, 8... Driver, 9... Deflector, 10... Sample, 11... Detector, 12... ...Signal processing circuit. Figure 3 Figure 4

Claims (1)

[Claims] A logic timing waveform corresponding to a measurement point at which the wiring potential of a semiconductor device is to be measured is extracted from a database storing logic timing waveforms, and an electronic In a method for measuring a wiring potential of a semiconductor device in which a beam is irradiated onto the semiconductor device and a wiring potential is measured based on a detection signal of secondary electrons generated from the semiconductor device, the logic timing waveform is The phase is divided into regions with a high level and regions with a low level, and the phases are arranged so that the divided regions with a high level and regions with a low level alternate in terms of the irradiation timing of the electron beam. 1. A method for measuring a wiring potential of a semiconductor device, characterized in that the wiring potential of a semiconductor device is measured by changing the wiring potential.