WO1997013157A1 - Ic tester and method of locating defective portions of ic - Google Patents

Ic tester and method of locating defective portions of ic Download PDF

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Publication number
WO1997013157A1
WO1997013157A1 PCT/JP1995/002053 JP9502053W WO9713157A1 WO 1997013157 A1 WO1997013157 A1 WO 1997013157A1 JP 9502053 W JP9502053 W JP 9502053W WO 9713157 A1 WO9713157 A1 WO 9713157A1
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WO
WIPO (PCT)
Prior art keywords
test
image data
test pattern
pattern
ion beam
Prior art date
Application number
PCT/JP1995/002053
Other languages
French (fr)
Japanese (ja)
Inventor
Masayuki Kuribara
Akira Goishi
Koshi Ueda
Original Assignee
Advantest Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP6095678A priority Critical patent/JPH07280890A/en
Priority claimed from JP6095678A external-priority patent/JPH07280890A/en
Priority to US08/418,498 priority patent/US5592099A/en
Priority to DE19513309A priority patent/DE19513309A1/en
Application filed by Advantest Corporation filed Critical Advantest Corporation
Priority to PCT/JP1995/002053 priority patent/WO1997013157A1/en
Priority to KR1019960705778A priority patent/KR100225011B1/en
Publication of WO1997013157A1 publication Critical patent/WO1997013157A1/en

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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/302Contactless testing
    • G01R31/303Contactless testing of integrated circuits

Definitions

  • Ic test apparatus and method for identifying defective part of ic using this apparatus
  • the present invention irradiates an IC under test with an ion beam, measures the amount of secondary electrons generated from the irradiated point, displays the potential distribution in the IC as a potential contrast image, and displays the defect portion.
  • the present invention relates to an IC test apparatus used for specifying an IC, an ion beam tester used therefor, and a method for specifying a defective portion of an IC to be measured. Background art
  • the chip of the IC under test is swept and irradiated with an ion beam (irradiating while scanning), and the amount of secondary electrons generated from each irradiation point is measured for each irradiation point.
  • an IC test device that displays the potential distribution in the IC as a potential contrast image and uses it for analysis of defective parts has been put into practical use. I have.
  • Fig. 13 shows the schematic configuration of this type of conventional IC test equipment.
  • 1Q0 indicates the entire IC test apparatus.
  • the IC test apparatus 100 is roughly divided into a test device, a turn generator 200, and an ion beam tester 300.
  • the test pattern generator 200 gives a test pattern signal to the device under test DUT mounted on the ion beam tester 300.
  • the conventional test pattern generator 200 includes a start switch 201 for starting the generation of a test pattern and a stop switch used for stopping the generation of the test pattern at an arbitrary time.
  • the test pattern Pattern setting means 203 for stopping the update of the pattern, and a pattern for detecting the occurrence of the test pattern set in the stop pattern setting means 203 and stopping the update of the test pattern. It comprises a holding means 204 and a stop signal generating means 205 for transmitting a signal indicating that the updating of the test pattern has been stopped.
  • the control for stopping the update operation of the test pattern in the test pattern is performed.
  • the ion beam test 300 is provided with a lens barrel 301 for irradiating the device under test with an ion beam and a lower portion of the lens barrel 301, and the device under test DUT is placed in a vacuum. And a stage provided inside the chamber and moving the position of the device under test DUT in the X-Y direction, and a device under test DUT Sensor 304 for measuring the amount of secondary electrons generated from the image, an image data acquisition device 3005 for capturing the electric signal detected by the sensor 304 as image data, and image data A monitor 306 that displays the image data processed by the acquisition device 305 as a potential contrast image, emission of the ion beam and its emission amount (current value), acceleration voltage, scanning speed, and scanning
  • the lens barrel controller 307 controls the area and the like.
  • the pattern holding means 204 suspends the update operation of the test pattern.
  • the test pattern set in the stop pattern setting means 203 continues to be output.
  • a stop signal indicating that the update operation of the test pattern has been stopped is supplied from the stop signal generation means 205 to the image data acquisition device 300 and the lens barrel controller 300.
  • the mirror controller 307 controls the emission of the ion beam in response to the supply of the stop signal.
  • the image data acquisition device 300 starts to acquire image data. You.
  • the method of specifying the defective part of the IC is to confirm the test pattern that generates the defect of the defective product tested in advance with the IC tester, and set the test pattern that causes the defect in the stop pattern setting means 203. Do.
  • the test pattern generator 200 detects that a test pattern that causes a failure has been set in the stop pattern setting means 203, the test pattern update operation is paused and the stop pattern is set. Continue to output the test pattern set in means 203.
  • the lens barrel controller 307 controls the firing of the ion beam in response to the supply of the stop signal.
  • the image data acquisition device 305 starts capturing image data. The above image data is taken in for non-defective and non-defective products, and a comparison operation is performed by the image data acquisition device 305, and a difference between the two is specified as a defective portion.
  • the stop time of the test pattern is set to be slightly longer than the time required for capturing the image data overnight. For this reason, if it is attempted to change the image data capture conditions, the stop time of the test pattern must also be changed, which has the disadvantage of poor operability. Force for setting ion beam acceleration voltage, scanning speed, scanning area, number of scans, etc .; changing these settings will change the time required to capture image data. For this reason, if the conditions for capturing image data are changed, the stop time of the test pattern must be changed accordingly. As a result, since both the test pattern generator 200 and the ion beam tester 300 must be operated, the operation is troublesome.
  • the device under test DUT is already covered with an insulating film as a protective layer.
  • the X-ray of the wiring conductor buried under this insulating film will be observed.
  • the potential distribution gradually disappears due to the accumulation of electric charges on the insulating film in proportion to the irradiation time, and the potential contrast image originally required is obtained.
  • Figure 14A shows the potential contrast image when the potentials of L logic, H logic, L logic, and H logic are given to the conductors under the insulating film, L2, La, and L, respectively. Is shown.
  • the potential contrast image is white (a large amount of secondary electrons reach sensor 304) by applying the L logic potential (voltage close to OV or negative potential). Is displayed as.
  • H logic voltage more positive than 0 V
  • the insulating substrate PB has an intermediate potential between the L logic and the H logic, and is displayed in gray.
  • Fig. 14B shows the state immediately after the irradiation and scanning of the ion beam (after 0.1 to 0.3 seconds). A few seconds after the start of ion beam irradiation, the potential contrast rapidly decreases as shown in Fig. 14C, and the potential contrast disappears. Therefore, the capture of image data is effective only in the state shown in Fig. 14A. Even if the image data is captured in the image memory due to the short time in which the potential contrast exists, only one time is required. It is difficult to obtain clear images simply by capturing image data.
  • An object of the present invention is to improve the operability of this type of IC test apparatus, to obtain a clear potential contrast image even when a potential contrast reduction phenomenon exists, and It seeks to provide a way to identify defective parts of an IC.
  • Another object of the present invention is to improve the quality of a potential contrast image representing a potential distribution of a wiring conductor in an IC chip in a state where a desired test pattern is applied.
  • a brief supplementary description of this purpose is provided.
  • the potential contrast image is obtained by applying a desired test pattern to the DUT under test, irradiating a partial area of the DUT under test with an ion beam, and measuring the amount of secondary electrons generated.
  • the force is proportional to the irradiation amount of the ion beam.
  • the potential distribution formed on the insulating film disappears. For this reason, the acquisition of image data is limited to only the first surface sweep of ion beam irradiation.
  • Image data is captured only during this one-time sweep irradiation of the ion beam, and this image data is repeatedly read out and displayed even if the potential contrast image on the monitor 310 is displayed.
  • One way to solve this drawback is to continuously update the test patterns and continue until a specific test pattern n is reached.
  • a method of continuing the ion beam sweep irradiation is considered. By adopting this method, while the test pattern is changing at a high speed, the ion beam is swept and irradiated, so the potential of the insulating film covering the top surface of the IC chip is the average of the potential change of the wiring conductor.
  • this method also has the following disadvantages. That is, when the pattern update operation is stopped with the desired test pattern, the wiring conductor that appears as a potential contrast image based on the immediately preceding potential and the potential contrast image as the potential contrast image There are mixed wiring conductors that do not appear, resulting in a potential contrast image that is not suitable for failure analysis. The reason why a conductor appearing as a potential contrast image and a conductor not appearing as a mixture will be understood from the operation description of this application. Disclosure of the invention
  • the present invention proposes a device capable of improving the operability and the image quality of a potential contrast image, and a particularly effective method for specifying a defective portion of an IC to be measured.
  • an ion beam tester that sweeps and irradiates the device under test with an ion beam, measures the amount of secondary electrons generated from each irradiation point, and reproduces the potential distribution inside the device under test as an image.
  • a test pattern generator for providing a test pattern to the device under test, a stop pattern setting means for setting a test pattern to be stopped in the test pattern generator; Means for temporarily stopping the test pattern update operation when the test pattern set by the means has been generated, and a pattern indicating that the test pattern update operation has stopped.
  • a stop signal generating means for outputting a pattern stop signal, and a release means for releasing the holding state of the pattern holding means by receiving an acquisition completion signal indicating completion of image data acquisition from the ion beam tester.
  • the image data acquisition means which starts the image data acquisition in response to the pattern stop signal generated by the stop signal generation means, and indicates that the image data acquisition means has acquired the required image data.
  • An acquisition completion signal generating means for generating an acquisition completion signal is provided.
  • the acquisition completion signal generation unit when the image data acquisition unit acquires the required image data, the acquisition completion signal generation unit generates an acquisition completion signal indicating the completion of the acquisition of the image data.
  • the pattern generator starts the test pattern update operation in response to the acquisition completion signal.
  • test pattern stop time it is not necessary to set a test pattern stop time in the test pattern generator, and the acquisition of image data and the automatic start and stop of the test pattern are repeated, so that no manual operation is required. There is no need.
  • test pattern generation it is possible to repeatedly acquire image data in a state where the same test pattern is applied.
  • Another object of the present invention is to improve the image quality by compensating for the phenomenon of lowering the potential contrast.
  • the present invention is configured so that at least two test patterns can be set in the stop pattern setting means provided in the test pattern generator, and the test pattern is generated every time the first test pattern and the second test pattern are generated. Stop the update operation of. Simultaneously, ion beam irradiation and acquisition of image data are performed both when the first test pattern is generated and when the second test pattern is generated, and the difference between the image data with a different test pattern applied is obtained.
  • the potential is obtained by calculating the difference between the image data obtained when the first test pattern is applied and the image data obtained when the second test pattern is applied. Only the changed part can be displayed as a potential contrast image.
  • the power of the device under test is turned off (disconnected) at the time of the first test pattern r.
  • the logic of the wiring conductor in the r pattern is forcibly fixed to the L logic, and the image is captured.
  • the power is turned on (connected) and the image is captured.
  • FIG. 1 is a block diagram showing one embodiment of the present invention.
  • FIG. 2 is a waveform chart for explaining the operation of the embodiment shown in FIG.
  • FIG. 3 is another waveform chart for explaining the operation of the embodiment shown in FIG.
  • FIG. 4 is a waveform chart for explaining the operation of the method invention.
  • FIG. 5 is another waveform diagram for explaining the operation of the method invention.
  • FIG. 6 is a plan view for explaining the potential applied to the wiring in the device under test when the test pattern r of FIG. 1 is applied.
  • FIG. 7 shows the wiring in the device under test when the test pattern n in Fig. 1 is applied.
  • FIG. 3 is a plan view for explaining potentials given to the thyristor.
  • FIG. 8 is a front view showing a potential contrast image obtained when the test pattern r is applied after the test patterns r and n in FIG. 1 are alternately applied.
  • FIG. 9 is a front view showing a potential contrast image obtained when test patterns n are applied after patterns r and n are alternately applied.
  • FIG. 10 is a front view showing a potential contrast in which the polarity of the potential contrast shown in FIG. 8 is inverted.
  • FIG. 11 is a front view showing a result calculated by the calculating means of FIG. 1 as a potential contrast.
  • FIG. 12 is a waveform diagram illustrating the reason why the potential contrast of a portion to which a potential of the same polarity is applied disappears when the test patterns r and n in FIG. 1 are alternately applied.
  • FIG. 13 is a block diagram for explaining a conventional technique.
  • FIG. 14 is a front view showing an example of a potential contrast image for explaining a drawback of the conventional technique.
  • FIG. 1 shows a block diagram of the IC test equipment used in the present invention. Parts corresponding to those in FIG. 13 are denoted by the same reference numerals.
  • the structure of the IC test apparatus 100 is characterized in that the ion beam tester 300 is provided with acquisition completion signal generating means 310 for transmitting an acquisition completion signal indicating the completion of the acquisition of image data.
  • acquisition completion signal generating means 310 for transmitting an acquisition completion signal indicating the completion of the acquisition of image data.
  • the acquisition completion signal generating means 308 is an image data acquiring means. It detects that the acquisition of the image data has been completed in 305A and 305B, and transmits an acquisition completion signal at the time of this detection. This acquisition completion signal is input to the pattern holding means 204 provided on the test pattern generator 200 side.
  • the pattern holding means 204 gives a command to the test pattern generator 200 to release the stop of the test pattern when the acquisition completion signal is input.
  • the test pattern generator 200 starts the update operation of the test pattern released from the stop state.
  • the pattern holding means 2 is generated each time the stop patterns r and n are generated. 04 operates to stop the update operation of the test pattern of the test pattern generator 200, and maintains the state where the test pattern r or n is output.
  • Figure 2 shows the situation.
  • Figure 2A shows the start signal
  • Figure 2B shows the test pattern signal.
  • the pattern holding means 204 temporarily updates the pattern of the test pattern generator 200. Stop and maintain the state where pattern r or n is output.
  • a stop signal is output from the stop signal generating means 205, and the stop signal is input to the image data capturing device 30 ⁇ to start capturing image data.
  • FIG. 2F shows the operation period for acquiring image data.
  • Completion of image data capture can be known, for example, by detecting a vertical retrace signal indicating that the ion beam sweep irradiation has reached one screen.
  • an acquisition completion signal is output when the ion beam scans one to several screens for any screen. Can be sent.
  • Figure 2G shows the acquisition completion signal.
  • a test is performed by giving an acquisition completion signal to the pattern holding means 204.
  • the pattern signal generator 200 is released from the stop state, and updates the test pattern as r + l, r + 2, ... or n + l, n + 2 ... as shown in Fig. 2B. Output up to the last pattern Last. If the test pattern generation is set to one time, the operation stops with the last pattern last generated. If the test pattern generation is set to be continuous and the restart after image data acquisition is set back to the first pattern, the test pattern r is automatically stopped when a test pattern r is generated as shown in Fig. 3.
  • the image data with the specified test patterns r and n applied can be automatically acquired multiple times. The end can be stopped by operating the stop switch 202.
  • the test pattern generator 20 Since the start and stop operations of 0 are linked to the image data acquisition operation of the ion beam tester 300, the test pattern generator 200 and the ion beam test device 300 even if the image data acquisition conditions are changed. There is no need to change the side settings. This simplifies operation and improves operability.
  • the invention of this application is to obtain a method of comparing the potential contrast between a good product and a defective product by using the IC test apparatus with improved operability and specifying a defective portion of the IC.
  • image data obtained by applying different test patterns to a plurality of image data acquisition means 300A and 300B are captured. That is, image data in a state where the test pattern r is given to the device under test DUT is taken into the image data acquisition means 3 ⁇ 5A. Also get image data overnight The image data in a state where the test pattern n is given to the device under test DUT is taken into the means 3 05 B.
  • the image data acquired by the image data acquisition means 300 A is inverted in polarity and applied to the arithmetic means 309, and the image data acquired by the image data acquisition means 305 B is directly used by the arithmetic means 309. 0 9 is given.
  • the calculating means 309 adds the image data given from the image data obtaining means 305A and 305B, and displays the result of the addition on the monitor 306. By displaying the calculation result of the calculating means 309 on the monitor 306, the potential contrast image becomes a clear image.
  • FIG. 6 shows the potential applied to the wiring conductors 1 , 2 , 3 , and 3 in the device under test 011 when the test pattern r is applied.
  • Conductor in the example of means that FIG 6 L, to L logic, H logic conductor L 2, conductors to L logic, the conductor L 4 shows a case of giving the H logic.
  • Figure 7 shows the potential applied to the wiring conductor ⁇ L 4 of the device under test in the DUT when applying a test pattern n.
  • Figures 8 and 9 show these potential contrast images.
  • Fig. 8 shows a potential contrast image when test pattern r is applied
  • Fig. 9 shows a potential contrast image when test pattern n is applied.
  • the potential co emissions trusses IMAGING shown in FIG. 8 the potential co emissions trusses bets the conductor is lost, only the potential co emissions trusses DOO conductor L 2 and L 3 are left.
  • the potential co down trusts conductor and L 4 are disappeared, only the potential co emissions trusses DOO conductor L z and L 3 are left. The reason is that the potentials applied to the conductors L 1 and L 4 are the same both when the test pattern r is applied and when the test pattern n is applied.
  • Figure 12 shows how the potential contrast disappears.
  • Figure 12 A shows the test pattern. The periods during which the turns r and ⁇ are applied and the ion beam irradiation period are shown.
  • Figure 1 2 beta are potential co emissions trusses event to occur in the insulating film existing on the surface of the conductor
  • Fig. 1 2 C is 3 ⁇ 4 position co emissions trusses event to occur in the insulating film existing on the surface of the conductor L 2
  • FIG. 1 2 D potential co emissions trusses event to occur in the insulating film existing on the surface of the conductor L
  • FIG. 1 2 E represents a potential co emissions trusses event to occur on the surface of the conductor L 4.
  • FIG. 10 shows image data obtained by inverting the polarity of the image data (potential contrast) acquired by the image data acquisition means 305A.
  • the image data shown in FIG. 11 is obtained by adding the image data shown in FIG. 10 and the image data shown in FIG. Image data shown in FIG. 1 1 is a conductor L 2 It has been added and emphasized about the potential contrast of this. As a result, the quality of the image is improved, and a potential contrast image with good resolution can be obtained.
  • Table 1 shows the correspondence table between the logic signals of non-defective ICs and defective ICs and the potential contrast images.
  • the logic signal pattern is a combination of H logic and L logic.If the same potential is applied to the first test pattern r and the second test pattern n, a gray potential contrast image is obtained. When L logic is given at the first test pattern r and H logic is given at the second test pattern n, a black potential contrast image is obtained.H logic is given at the first test pattern r, and the second test pattern is given. When logic is given at time n, a white potential contrast image is obtained.
  • Table 1 shows the combination of logical patterns that can occur between good and defective products, and shows whether there is a difference in potential contrast images between good and defective products, and whether there is a problem in fault detection.
  • Item 3, item 8, item 9, and item 14 in Table 1 have the same image because the logical signals of good and defective products are the same.
  • the problems in fault detection are item 2 and item 15. In other words, it does not appear as a difference even though the logic level of each test pattern is different between good and defective products.
  • the present invention is a method for solving this problem in fault detection.
  • FIG. 5 is a waveform chart for explaining the operation of the present invention.
  • This feature is that the power of the device under test is turned off (turned off) at the time of the first test pattern r, and in that state the image data is acquired by irradiating and scanning the ion beam.
  • the logic is always low because the power is off.
  • the power is turned on (contacted), the ion beam is irradiated and scanned, and image data acquisition is performed.
  • FIG. 4 shows an example of a method of performing measurement by repeatedly turning off and on the power supply. Table 2 shows whether there is a difference between the potential contrast images of good and defective products and whether there is a problem in fault detection using the method of the present invention. / 13157
  • test patterns for example, r and n are alternately applied, and a difference in potential contrast generated by the test patterns is displayed.
  • the quality of the image can be improved as compared with a potential contrast image in a state in which one of n is applied.
  • the potential distribution of the wiring conductor in the IC chip can be analyzed with higher accuracy, so that there is an advantage that a defective portion can be specified in a short time.
  • the power of the device under test is turned off to change the logic of the wiring conductor in the first test r pattern to L.
  • the logic is fixed and the image can be captured by turning on the power in the second test pattern n.

Abstract

An apparatus for analyzing failures of an IC chip and locating defective portions by irradiating the surface of an IC with an ion beam and displaying a potential contrast image of a wiring conductor on the surface of the chip, which provides improved handling and better image quality. To this end, means for setting a plurality of patterns for stopping an updating operation of the patterns is provided in a test pattern generator, the pattern updating operation of the test pattern generator is stopped wherever this stop pattern is generated, and a stop signal is sent to an ion beam tester so as to acquire image data. When acquisition of the image data is completed, signal generation means transmits an acquisition completion signal, and the test pattern generator again starts the pattern updating operation. As a result, different test patterns can be applied alternately to the chip under test, and image quality can be improved by adding and subtracting the image data. A method of locating defective portions of the IC comprises turning off a power supply of the chip at the time of a first test pattern (r) so as to fix the logic of the wiring conductor at the (r) pattern to LOW so that a difference always occurs in a potential contrast image when any difference of the logic exists between acceptable and defective chips by the acquisition of the image data at the second test pattern (n).

Description

明 細 書  Specification
I C試験装置及びこの装置を用いた I Cの不良部分の特定方法 技術分野 Ic test apparatus and method for identifying defective part of ic using this apparatus
この発明は被試験 I C にイ オンビームを照射 し、 その照射点から発生 する 2次電子の量を計測 して I C 内の電位分布を電位コ ン ト ラ ス ト像と して表示 し、 欠陥部分を特定する こ と等に用いる I C試験装置並びにそ れに使.われるイ オンビームテスタ及び被測定 I Cの不良部分の特定方法 に関する。 背景技術  The present invention irradiates an IC under test with an ion beam, measures the amount of secondary electrons generated from the irradiated point, displays the potential distribution in the IC as a potential contrast image, and displays the defect portion. The present invention relates to an IC test apparatus used for specifying an IC, an ion beam tester used therefor, and a method for specifying a defective portion of an IC to be measured. Background art
従来よ り被試験 I Cのチ ッ プにイ オンビームを掃引照射 (走査しなが ら照射するこ と) し、 各照射点から発生する 2次電子の量を各照射点ご と に計測 し、 この計測量を電気信号と して取り 込むこ と によ り I C内の 電位分布を電位コ ン ト ラス ト像と して表示 し、 不良箇所の解析等に利用 する I C試験装置が実用されている。  Conventionally, the chip of the IC under test is swept and irradiated with an ion beam (irradiating while scanning), and the amount of secondary electrons generated from each irradiation point is measured for each irradiation point. By taking this measured amount as an electrical signal, an IC test device that displays the potential distribution in the IC as a potential contrast image and uses it for analysis of defective parts has been put into practical use. I have.
図 1 3 に従来のこの種の I C試験装置の概略の構成を示す。 図中 1 Q 0は I C試験装置の全体を指す。 I C試験装置 1 0 0 は大き く 分けて試 験ノ、 °ターン発生器 2 0 0 と、 イ オンビ一ムテス タ 3 0 0 と によ って構成 される。  Fig. 13 shows the schematic configuration of this type of conventional IC test equipment. In the figure, 1Q0 indicates the entire IC test apparatus. The IC test apparatus 100 is roughly divided into a test device, a turn generator 200, and an ion beam tester 300.
試験パターン発生器 2 0 0 はイ オンビームテスタ 3 0 0 に装着した被 試験素子 D U Tに試験パターン信号を与える。 従来の試験パターン発生 器 2 0 0 は試験パターンの発生を開始させるス ター ト スィ ッチ 2 0 1 と 、 任意の時点で試験パターンの発生を停止させるこ と に用いるス ト ッ プ スィ ッ チ 2 0 2 と、 特定 した試験パターンが発生した と き、 試験パター ンの更新を停止させるための停止パターン設定手段 2 0 3 と、 停止パ夕 —ン設定手段 2 0 3に設定した試験パターンが発生したこ とを検出して 試験パターンの更新を停止させるパター ン保持手段 2 0 4 と、 試験パ夕 ーンの更新が停止したこ と を表す信号を発信する停止信号発生手段 2 0 5 と を具備し、 試験パターン信号の発生開始制御と、 停止制御及び特定 の試験パターンにおいて試験パターンの更新動作を停止させる制御と を 行う こ とができるよ う に構成されている。 The test pattern generator 200 gives a test pattern signal to the device under test DUT mounted on the ion beam tester 300. The conventional test pattern generator 200 includes a start switch 201 for starting the generation of a test pattern and a stop switch used for stopping the generation of the test pattern at an arbitrary time. When the specified test pattern occurs, the test pattern Pattern setting means 203 for stopping the update of the pattern, and a pattern for detecting the occurrence of the test pattern set in the stop pattern setting means 203 and stopping the update of the test pattern. It comprises a holding means 204 and a stop signal generating means 205 for transmitting a signal indicating that the updating of the test pattern has been stopped. The control for stopping the update operation of the test pattern in the test pattern is performed.
一方、 イ オ ンビームテス夕 3 0 0は被試験素子 D U Tにイ オ ンビーム を照射する鏡筒部 3 0 1 と、 この鏡筒部 3 0 1 の下部に設けられ、 被試 験素子 D U Tを真空中に配置するチ ャ ンバ 3 0 2 と、 こ のチ ャ ンバ 3 0 2の内部に設けられ、 被試験素子 D U Tの位置を X— Y方向に移動させ るステージ 3 0 3 と、 被試験素子 D U Tから発生する 2次電子の量を計 測するためのセンサ 3 0 4 と、 センサ 3 0 4 によ って検出 した電気信号 を画像データ と して取り込む画像データ取得装置 3 0 5 と、 画像データ 取得装置 3 0 5で処理した画像データを電位コ ン ト ラ ス ト像と して表示 するモニタ 3 0 6 と、 イ オンビームの出射及びその出射量 (電流値) 、 加速電圧、 走査速度、 走査面積等を制御する鏡筒制御器 3 0 7 と によ つ て構成される。  On the other hand, the ion beam test 300 is provided with a lens barrel 301 for irradiating the device under test with an ion beam and a lower portion of the lens barrel 301, and the device under test DUT is placed in a vacuum. And a stage provided inside the chamber and moving the position of the device under test DUT in the X-Y direction, and a device under test DUT Sensor 304 for measuring the amount of secondary electrons generated from the image, an image data acquisition device 3005 for capturing the electric signal detected by the sensor 304 as image data, and image data A monitor 306 that displays the image data processed by the acquisition device 305 as a potential contrast image, emission of the ion beam and its emission amount (current value), acceleration voltage, scanning speed, and scanning The lens barrel controller 307 controls the area and the like.
パター ン保持手段 2 0 4は試験パターン発生器 2 0 0が停止パター ン 設定手段 2 0 3に設定された試験パターンを発生したこ と を検出する と 、 試験パター ンの更新動作を一時停止し、 停止パター ン設定手段 2 0 3 に設定した試験パターンを出 し続ける。 これと共に画像データ取得装置 3 0 5及び鏡筒制御器 3 0 7 に停止信号発生手段 2 0 5から試験パター ンの更新動作が停止したこ と を表す停止信号が与えられる。 鏡阇制御器 3 0 7は停止信号の供給を受けてイ オンビームを発射させる制御を行う 。 これと共に画像データ取得装置 3 0 5は画像データの取込みを開始す る。 When the test pattern generator 200 detects that the test pattern generator 200 has generated the test pattern set in the stop pattern setting means 203, the pattern holding means 204 suspends the update operation of the test pattern. The test pattern set in the stop pattern setting means 203 continues to be output. At the same time, a stop signal indicating that the update operation of the test pattern has been stopped is supplied from the stop signal generation means 205 to the image data acquisition device 300 and the lens barrel controller 300. The mirror controller 307 controls the emission of the ion beam in response to the supply of the stop signal. At the same time, the image data acquisition device 300 starts to acquire image data. You.
I Cの不良部分を特定する方法は、 予め I Cテスタで試験した不良品 の不良を発生する試験パターンを確認し、 その不良を起こす試験パター ンを停止パターン設定手段 2 0 3 に設定するこ とで行う。 試^パターン 発生器 2 0 0が停止パターン設定手段 2 0 3 に設定された、 不良を起こ す試験パターンを発生したこ と を検出する と、 試験パターンの更新動作 を一時停止し、 停止パターン設定手段 2 0 3 に設定した試験パターンを 出 し続ける。 鏡筒制御器 3 0 7 は停止信号の供給を受けてイ オ ンビーム を発射させる制御を行う。 これと共に画像データ取得装置 3 0 5 は画像 データの取込みを開始する。 以上の画像データの取込みを良品と不良品 について行い、 画像データ取得装置 3 0 5 で比較演算 し、 両者の相違部 分を不良部分と特定する。  The method of specifying the defective part of the IC is to confirm the test pattern that generates the defect of the defective product tested in advance with the IC tester, and set the test pattern that causes the defect in the stop pattern setting means 203. Do. When the test pattern generator 200 detects that a test pattern that causes a failure has been set in the stop pattern setting means 203, the test pattern update operation is paused and the stop pattern is set. Continue to output the test pattern set in means 203. The lens barrel controller 307 controls the firing of the ion beam in response to the supply of the stop signal. At the same time, the image data acquisition device 305 starts capturing image data. The above image data is taken in for non-defective and non-defective products, and a comparison operation is performed by the image data acquisition device 305, and a difference between the two is specified as a defective portion.
従来のこの種の I C試験装置では、 試験パターンの停止時間を画像デ 一夕の取込みに要する時間よ り余裕を持たせて多少長い時間に設定する 。 このために画像データの取込条件を変更 しょ う とする と、 試験パター ンの停止時間も変更 しなければならな く な り、 操作性が悪い欠点がある つま り、 画像データの取込みにはイ オンビームの加速電圧、 走査速度 、 走査面積、 走査回数等を設定しなければならない力;、 これらの設定を 変更する と画像データの取込みに要する時間が変化するこ と になる。 こ のよ う な理由から画像データの取込条件を変更すると、 これに見合う よ う に試験パターンの停止時間も変更しなければならない。 この結果、 試 験パターン発生器 2 0 0 と イ オンビームテス タ 3 0 0の双方を操作 しな ければならないから操作が面倒である。  In this type of conventional IC test apparatus, the stop time of the test pattern is set to be slightly longer than the time required for capturing the image data overnight. For this reason, if it is attempted to change the image data capture conditions, the stop time of the test pattern must also be changed, which has the disadvantage of poor operability. Force for setting ion beam acceleration voltage, scanning speed, scanning area, number of scans, etc .; changing these settings will change the time required to capture image data. For this reason, if the conditions for capturing image data are changed, the stop time of the test pattern must be changed accordingly. As a result, since both the test pattern generator 200 and the ion beam tester 300 must be operated, the operation is troublesome.
—方、 画像データの取込条件は試験の目的に応じて各種変更する必要 がある。 特に被試験素子 D U Tが表面に既に保護層と して絶縁膜が被せ られている I Cチ ップでは、 この絶縁膜の下に埋もれている配線導体の 霄位を観測するこ と になる。 しかしながら、 表面に絶縁膜が被着された I Cチ ッ プの 線導体の電位分布を電位コ ン ト ラス ト像と して取り 出す こ とはむずか しい点がある。 つま り、 絶縁膜の表面にイ オンビームを照 射する と、 照射時間に比例して絶縁膜上の電荷の蓄積によ り電位の分布 が次第に消滅し、 本来求める電位コ ン ト ラ ス ト像を得る こ とができな く なる不都合がある。 図 1 4 にその様子を示す。 図 1 4 Aは絶縁膜の下に 存在する導体 、 L 2 、 L a 、 L , にそれぞれ L論理、 H論理、 L論 理、 H論理の電位を与えた場合の電位コン ト ラ ス ト像を示す。 図示する よ う に L論理の電位 ( O V に近い電圧又は負電位) を与えるこ と によ り 電位コ ン ト ラス ト像は白色 ( 2次電子のセ ンサ 3 0 4 への到達量大) と して表示される。 H論理の電位 ( 0 Vよ り正側の電圧) を与えた場合は 黒色 ( 2次電子のセンサ 3 0 4への到達量が少ない) に表示される。 こ こで絶縁基板 P Bは L論理と H論理の中間の電位となり、 灰色で表示さ れる。 —On the other hand, it is necessary to change the conditions for capturing image data according to the purpose of the test. In particular, the device under test DUT is already covered with an insulating film as a protective layer. In the IC chip used, the X-ray of the wiring conductor buried under this insulating film will be observed. However, it is difficult to extract the potential distribution of the wire conductor of an IC chip having an insulating film adhered on the surface as a potential contrast image. In other words, when the surface of the insulating film is irradiated with an ion beam, the potential distribution gradually disappears due to the accumulation of electric charges on the insulating film in proportion to the irradiation time, and the potential contrast image originally required is obtained. There is a disadvantage that it is not possible to obtain Figure 14 shows the situation. Figure 14A shows the potential contrast image when the potentials of L logic, H logic, L logic, and H logic are given to the conductors under the insulating film, L2, La, and L, respectively. Is shown. As shown in the figure, the potential contrast image is white (a large amount of secondary electrons reach sensor 304) by applying the L logic potential (voltage close to OV or negative potential). Is displayed as. When the potential of H logic (voltage more positive than 0 V) is applied, it is displayed in black (the amount of secondary electrons reaching the sensor 304 is small). Here, the insulating substrate PB has an intermediate potential between the L logic and the H logic, and is displayed in gray.
図 1 4 Bはイ オ ンビームを照射及び走査させた直後 (0. 1 〜 0. 3 秒経 過時点) の状態を示す。 イ オ ンビームを照射し始める と、 数秒後には図 1 4 C に示すよ う に電位コ ン ト ラス ト は急速に低減し、 電位コ ン ト ラス トは消滅する。 従って画像データの取込みは図 1 4 A に示す状態でのみ 有効であり、 電位コ ン ト ラス トが存在する時間が短いため画像データを 画像メモ リ に取り 込むに して も、 ただ 1 回の画像データの取込みだけで は鮮明な画像を得るこ とはむずか しい。  Fig. 14B shows the state immediately after the irradiation and scanning of the ion beam (after 0.1 to 0.3 seconds). A few seconds after the start of ion beam irradiation, the potential contrast rapidly decreases as shown in Fig. 14C, and the potential contrast disappears. Therefore, the capture of image data is effective only in the state shown in Fig. 14A. Even if the image data is captured in the image memory due to the short time in which the potential contrast exists, only one time is required. It is difficult to obtain clear images simply by capturing image data.
この電位コ ン ト ラス 卜 の低下現象が存在するため、 画像データの取込 条件 (イ オンビームの走査面積、 イ オンビームの電流値等) を変更する 頻度は高い。 従って画像データの取込条件を変更する都度、 試験パ夕一 ンを停止させる時間の設定も変更 しなければならないから、 この点で操 作性が悪い不都合がある。 Because of this phenomenon of potential contrast reduction, the frequency of changing the image data acquisition conditions (ion beam scanning area, ion beam current value, etc.) is high. Therefore, every time the image data capture conditions are changed, the setting of the time during which the test panel is stopped must be changed, and operation is not performed at this point. There is an inconvenience with poor workability.
この発明の目的は、 この種の I C試験装置の操作性を向上し、 電位コ ン ト ラス トの低下現象が存在しても鮮明な電位コ ン ト ラス ト像を得るこ とができ、 また、 I Cの不良部分を特定する方法を提供しょ う とするも のである。  An object of the present invention is to improve the operability of this type of IC test apparatus, to obtain a clear potential contrast image even when a potential contrast reduction phenomenon exists, and It seeks to provide a way to identify defective parts of an IC.
この発明の他の目的は、 所望の試験パターンを印加 した状態にある I Cチ ップ内の配線導体の電位分布を表す電位コ ン ト ラス ト像の画質を向 上させる こ と にある。 この目的について簡単に補足説明する。  Another object of the present invention is to improve the quality of a potential contrast image representing a potential distribution of a wiring conductor in an IC chip in a state where a desired test pattern is applied. A brief supplementary description of this purpose is provided.
電位コ ン ト ラス ト像は被試験 D U Tに所望の試験パター ンを印加 した 状態で被試験 D U Tの一部の領域にイ オンビームを掃引照射し、 2次電 子の発生量を画像デ一夕 と して取り込むこ と によ り得る ものである力;、 被試験素子の表面に絶縁膜が被せられている I Cチ ッ プでは先に説明 し たよ う にイ オンビームの照射量に比例 して絶縁膜上に形成される電位分 布が消滅する現象がある。 このため画像データの取り込みはィ オンビー ム照射の最初の 1 回の面掃査時だけに限られて しま う。 この 1 回のィ ォ ンビームの掃引照射時だけで画像データを取り込み、 この画像デ一夕を 繰り返 し読みだしてモニタ 3 0 6 の電位コ ン ト ラス ト像を表示 しても画 像のデータ量が少ないため細部にわたる部分が不鲜明になる欠点がある この欠点を解消する一つの方法と して、 試験パターンを順次更新させ て特定の試験パターン n に到達するまでの間、 継続してイ オンビームの 掃引照射を続ける方法が考えられる。 この方法を採るこ と によ り試験パ ターンが高速で変化している間、 イ オンビームを掃引照射するから、 I Cチ ップの上面を覆う絶縁膜の電位は、 配線導体の電位変化の平均値、 つま り H論理と L論理の中間値と なり、 目 的とする試験パターン nでパ ター ンの更新動作が停止する と、 その試験パターンによ っ て決まる電位 分布が電位コ ン ト ラス ト像と して取り込むこ とができ る。 画像データの 取り込み後再び試験パターンの更新動作を再開 し、 その状態でもイ オン ビームの椅引照射を続けると絶縁膜の電位は再び H論理と L論理の中間 値と なる。 The potential contrast image is obtained by applying a desired test pattern to the DUT under test, irradiating a partial area of the DUT under test with an ion beam, and measuring the amount of secondary electrons generated. As described above, in the case of an IC chip where the surface of the device under test is covered with an insulating film, the force is proportional to the irradiation amount of the ion beam. There is a phenomenon that the potential distribution formed on the insulating film disappears. For this reason, the acquisition of image data is limited to only the first surface sweep of ion beam irradiation. Image data is captured only during this one-time sweep irradiation of the ion beam, and this image data is repeatedly read out and displayed even if the potential contrast image on the monitor 310 is displayed. There is a drawback that details are unclear due to the small amount of data.One way to solve this drawback is to continuously update the test patterns and continue until a specific test pattern n is reached. A method of continuing the ion beam sweep irradiation is considered. By adopting this method, while the test pattern is changing at a high speed, the ion beam is swept and irradiated, so the potential of the insulating film covering the top surface of the IC chip is the average of the potential change of the wiring conductor. Value, that is, an intermediate value between the H logic and the L logic, and when the pattern update operation stops at the target test pattern n, the potential determined by the test pattern n The distribution can be captured as a potential contrast image. After retrieving the image data, the test pattern update operation is resumed, and in this state, if the irradiation of the ion beam is continued, the potential of the insulating film returns to an intermediate value between H logic and L logic.
従ってこれを繰り返すこ と によ り所望の試験パターンを印加した状態 の電位コ ン ト ラス ト像を繰り返し得る こ とができ、 画像データ量を大き く するこ とができ平均値処理等を施すこ と によ り電位コ ン ト ラス ト像の 画質を向上させるこ とができる利点が得られる。  Therefore, by repeating this, a potential contrast image in a state where a desired test pattern is applied can be repeatedly obtained, the image data amount can be increased, and an average value processing or the like is performed. This provides an advantage that the quality of the potential contrast image can be improved.
しかしながら、 この方法にも次のよ う な欠点がある。 つま り 所望の試 験パターンでパターンの更新動作を停止する と き、 その直前の電位によ つて電位コ ン ト ラス ト像と して表れる配線導体と、 電位コ ン ト ラス ト像 と して表れない配線導体とが混在し、 不良解析には不向きな電位コ ン ト ラス ト像となる。 電位コ ン ト ラス 卜像と して表れる導体と表れない導体 とが混在する理由はこの出願の動作説明によ り理解されよ う。 発明の開示  However, this method also has the following disadvantages. That is, when the pattern update operation is stopped with the desired test pattern, the wiring conductor that appears as a potential contrast image based on the immediately preceding potential and the potential contrast image as the potential contrast image There are mixed wiring conductors that do not appear, resulting in a potential contrast image that is not suitable for failure analysis. The reason why a conductor appearing as a potential contrast image and a conductor not appearing as a mixture will be understood from the operation description of this application. Disclosure of the invention
この発明では操作性を向上するこ と と、 電位コ ン ト ラス ト像の画質を 向上するこ とができる装置と、 特に有効な被測定 I Cの不良部分の特定 方法を提案するものである。 つま り被試験素子にイ オ ンビームを掃引照 射し、 各照射点から発生する 2次電子の量を計測して被試験素子内の電 位分布を画像と して再現するイ オンビームテス タと、 被試験素子に試験 パターンを与える試験パターン発生器とを具備 して構成された I C試験 装置において、 試験パターン発生器に停止すべき試験パターンを設定す る停止パターン設定手段と、 この停止パターン設定手段で設定 した試験 パターンを発生した状態で試験パターンの更新動作を一時停止させるパ ター ン保持手段と、 試験パターンの更新動作が停止したこ とを表すパ夕 ーン停止信号を出力する停止信号発生手段と、 イ オンビームテスタから 画像データの取得完了を表す取得完了信号の供給を受けてパターン保持 手段の保持状態を解除する解除手段と を設ける と共に、 イ オンビームテ ス夕 には停止信号発生手段が発生するパターン停止信号を受けて画像デ 一夕の取込みを開始する画像データ取得手段と、 この画像データ取得手 段が所要の画像データを取得したこ と を表す取得完了信号を発生する取 得完了信号発生手段とを設けた構造と した ものである。 The present invention proposes a device capable of improving the operability and the image quality of a potential contrast image, and a particularly effective method for specifying a defective portion of an IC to be measured. In other words, an ion beam tester that sweeps and irradiates the device under test with an ion beam, measures the amount of secondary electrons generated from each irradiation point, and reproduces the potential distribution inside the device under test as an image. A test pattern generator for providing a test pattern to the device under test, a stop pattern setting means for setting a test pattern to be stopped in the test pattern generator; Means for temporarily stopping the test pattern update operation when the test pattern set by the means has been generated, and a pattern indicating that the test pattern update operation has stopped. A stop signal generating means for outputting a pattern stop signal, and a release means for releasing the holding state of the pattern holding means by receiving an acquisition completion signal indicating completion of image data acquisition from the ion beam tester. The image data acquisition means which starts the image data acquisition in response to the pattern stop signal generated by the stop signal generation means, and indicates that the image data acquisition means has acquired the required image data. An acquisition completion signal generating means for generating an acquisition completion signal is provided.
この構成によれば、 画像データ取込手段が所要の画像データを取得す ると、 取得完了信号発生手段が画像データの取得完了を表す取得完了信 号を発生する。 この取得完了信号によ りパターン発生器は試験パターン の更新動作を開始する。  According to this configuration, when the image data acquisition unit acquires the required image data, the acquisition completion signal generation unit generates an acquisition completion signal indicating the completion of the acquisition of the image data. The pattern generator starts the test pattern update operation in response to the acquisition completion signal.
従って、 この構成によれば試験パターン発生器に試験パターン停止時 間を設定する必要がなく 、 画像データの取得と、 試験パターンの自動ス ター ト、 ス ト ップとが繰り返され、 人手を全く 必要とする こ とがない。 また試験パターンの発生を繰り返し発生モー ドに設定するこ と によ り 同一の試験パターンを印加した状態の画像データを繰り返 し取得するこ とができる。  Therefore, according to this configuration, it is not necessary to set a test pattern stop time in the test pattern generator, and the acquisition of image data and the automatic start and stop of the test pattern are repeated, so that no manual operation is required. There is no need. In addition, by setting the test pattern generation to the repetition generation mode, it is possible to repeatedly acquire image data in a state where the same test pattern is applied.
この発明では電位コ ン ト ラス 卜の低下現象を補って画質の向上を達す るこ と も 目的にしている。 このためこの発明では試験パターン発生器に 設けた停止パターン設定手段に少なく と も 2 つの試験パターンを設定で きるよ う に構成し、 第 1 試験パターン と第 2試験パターンが発生する毎 に試験パターンの更新動作を停止させる。 これと共に第 1 試験パターン 発生時及び第 2試験パターン発生時共にイ オンビームの照射と画像デー 夕の取得を実行し、 更に異なる試験パターンを印加した状態の画像デー 夕の差を求める。  Another object of the present invention is to improve the image quality by compensating for the phenomenon of lowering the potential contrast. For this reason, the present invention is configured so that at least two test patterns can be set in the stop pattern setting means provided in the test pattern generator, and the test pattern is generated every time the first test pattern and the second test pattern are generated. Stop the update operation of. Simultaneously, ion beam irradiation and acquisition of image data are performed both when the first test pattern is generated and when the second test pattern is generated, and the difference between the image data with a different test pattern applied is obtained.
このよ う に第 1 試験パターン発生時及び第 2試験パターン発生時共に イ オンビーム掃引照射と、 画像データの取得動作を実行し、 第 1 試験パ ターン印加時に得られる画像データ と第 2試験パターン印加時に得られ る画像データの差を求めるこ と によ り、 電位が変化した部分だけを電位 コ ン ト ラス ト像と して表示するこ とができる。 Thus, both when the first test pattern and the second test pattern occur, By performing ion beam sweep irradiation and acquiring image data, the potential is obtained by calculating the difference between the image data obtained when the first test pattern is applied and the image data obtained when the second test pattern is applied. Only the changed part can be displayed as a potential contrast image.
この場合、 2つの画像データの差を求めるから、 第 1 試験パターン と 第 2試験パターンの印加時に電位が逆転した部分の電位コ ン ト ラス トが 強調されて得られ、 像の画質が向上し、 鲜明な画像を得る こ とができる  In this case, since the difference between the two image data is obtained, the potential contrast at the portion where the potential is inverted when the first test pattern and the second test pattern are applied is emphasized, and the image quality is improved. You can get clear images
I Cの不良部分を特定する特別な方法と しては、 第 1 試験パターン r 時に被試験素子の電源をオフ (断) にする。 これによ り、 rパターンで の配線導体の論理を強制的に L論理に固定 して画像を取 り 込み、 第 2試 験パターン nでは電源をオン (接) に して画像を取り 込む。 このよ う に して、 良品と不良品間に論理に相違があっ た場合には、 必ず電位コ ン ト ラス ト像に差像が表れるよ う にする。 つま り、 良品と不良品の電位コ ン ト ラス ト像の差像によ っ て、 I Cの不良部分を特定するこ とができる。 図面の簡単な説明 As a special method of specifying the defective part of IC, the power of the device under test is turned off (disconnected) at the time of the first test pattern r. As a result, the logic of the wiring conductor in the r pattern is forcibly fixed to the L logic, and the image is captured. In the second test pattern n, the power is turned on (connected) and the image is captured. In this way, if there is a difference in logic between a good product and a defective product, a difference image must appear in the potential contrast image. In other words, the IC defective portion can be identified by the difference image between the potential contrast images of the non-defective product and the defective product. BRIEF DESCRIPTION OF THE FIGURES
図 1 は、 本発明の一実施例を示すプロ ッ ク図である。  FIG. 1 is a block diagram showing one embodiment of the present invention.
図 2 は、 図 1 に示した実施例の動作を説明するための波形図である。 図 3 は、 図 1 に示した実施例の動作を説明するための他の波形図であ る。  FIG. 2 is a waveform chart for explaining the operation of the embodiment shown in FIG. FIG. 3 is another waveform chart for explaining the operation of the embodiment shown in FIG.
図 4 は、 この方法発明の動作を説明するための波形図である。  FIG. 4 is a waveform chart for explaining the operation of the method invention.
図 5 は、 この方法発明の動作を説明するための他の波形図である。 図 6 は、 図 1 の試験パターン r を印加した場合の被試験素子内の配線 に与えられる電位を説明するための平面図である。  FIG. 5 is another waveform diagram for explaining the operation of the method invention. FIG. 6 is a plan view for explaining the potential applied to the wiring in the device under test when the test pattern r of FIG. 1 is applied.
図 7 は、 図 1 の試験パターン n を印加した場合の被試験素子内の配線 に与えられる電位を説明するための平面図であ 。 Fig. 7 shows the wiring in the device under test when the test pattern n in Fig. 1 is applied. FIG. 3 is a plan view for explaining potentials given to the thyristor.
図 8は、 図 1 の試験パターン r と n を交互に印加した後に試験パター ン r を印加した状態で得られる電位コ ン ト ラス ト像を示す正面図である 図 9は、 図 1 の試験パターン r と n を交互に与えた後に試験パターン nを印加した状態で得られる電位コ ン ト ラス ト像を示す正面図である。 図 1 0 は、 図 8 に示した電位コ ン ト ラス トの極性を反転した電位コ ン ト ラス ト を示す正面図である。  FIG. 8 is a front view showing a potential contrast image obtained when the test pattern r is applied after the test patterns r and n in FIG. 1 are alternately applied. FIG. 9 is a front view showing a potential contrast image obtained when test patterns n are applied after patterns r and n are alternately applied. FIG. 10 is a front view showing a potential contrast in which the polarity of the potential contrast shown in FIG. 8 is inverted.
図 1 1 は、 図 1 の演算手段によ り演算した結果を電位コ ン ト ラス ト と して表示 した正面図である。  FIG. 11 is a front view showing a result calculated by the calculating means of FIG. 1 as a potential contrast.
図 1 2 は、 図 1 の試験パターン r と n を交互に印加 した場合に、 同一 極性の電位が与え られる部分の電位コ ン ト ラス トが消失する理由を説明 する波形図である。  FIG. 12 is a waveform diagram illustrating the reason why the potential contrast of a portion to which a potential of the same polarity is applied disappears when the test patterns r and n in FIG. 1 are alternately applied.
図 1 3 は、 従来の技術を説明するためのブロ ッ ク図である。  FIG. 13 is a block diagram for explaining a conventional technique.
図 1 4 は、 従来の技術の欠点を説明するための電位コ ン ト ラス ト像の 一例を示す正面図である。 発明を実施するための最良の形態  FIG. 14 is a front view showing an example of a potential contrast image for explaining a drawback of the conventional technique. BEST MODE FOR CARRYING OUT THE INVENTION
図 1 に この発明に使用する I C試験装置のブロ ッ ク図を示す。 図 1 3 と対応する部分には同一符号を付 して示す。 この I C試験装置 1 0 0の 特徴とする構造はイ オンビームテスタ 3 0 0 に画像データの取得完了を 表す取得完了信号を発信する取得完了信号発生手段 3 0 8 を設けた点と 、 画像データ取得手段を 3 0 5 A と 3 0 5 Bの複数設けた点と、 これら 画像データ取得手段 3 0 5 A と 3 0 5 B に取得 した画像データの差を求 める演算手段 3 0 9 を設けた点である。  Figure 1 shows a block diagram of the IC test equipment used in the present invention. Parts corresponding to those in FIG. 13 are denoted by the same reference numerals. The structure of the IC test apparatus 100 is characterized in that the ion beam tester 300 is provided with acquisition completion signal generating means 310 for transmitting an acquisition completion signal indicating the completion of the acquisition of image data. There are provided a plurality of means of 305 A and 305 B, and a calculation means 309 for obtaining the difference between the image data obtained by the image data obtaining means 305 A and 305 B. It is a point.
この実施例では、 取得完了信号発生手段 3 0 8は画像データ取得手段 3 0 5 A及び 3 0 5 Bにおいて画像データの取得が完了 したこ と を検出 し、 この検出時点で取得完了信号を発信する。 この取得完了信号は試験 パターン発生器 2 0 0側に設けたパターン保持手段 2 0 4 に入力する。 パターン保持手段 2 0 4 は取得完了信号が入力されるこ と によ り試験 パター ン発生器 2 0 0 に試験パターンの停止を解除するコマン ドを与え る。 試験パターン発生器 2 0 0 は停止状態から解放された試験パター ン の更新動作を開始する。 In this embodiment, the acquisition completion signal generating means 308 is an image data acquiring means. It detects that the acquisition of the image data has been completed in 305A and 305B, and transmits an acquisition completion signal at the time of this detection. This acquisition completion signal is input to the pattern holding means 204 provided on the test pattern generator 200 side. The pattern holding means 204 gives a command to the test pattern generator 200 to release the stop of the test pattern when the acquisition completion signal is input. The test pattern generator 200 starts the update operation of the test pattern released from the stop state.
つま り、 この装置によれば停止パター ン設定手段 2 0 3 に例えば停止 ノ ター ン r と nを設定したとする と、 この停止パター ン r と n が発生す る毎にパター ン保持手段 2 0 4 が働いて試験パターン発生器 2 0 0の試 験パター ンの更新動作を停止させ、 試験パター ン r 又は n を出力 した状 態を維持する。 図 2 にその様子を示す。 図 2 Aはスター ト信号、 図 2 B は試験パター ン信号を示す。 試験パターン信号のパターンが r 又は n ( 一般にパターン発生順序を表わすア ド レスを指す) に達すると、 パター ン保持手段 2 0 4 が試験パター ン発生器 2 0 0 のパター ンの更新動作を 一時停止させ、 パターン r 又は n を出力 した状態を維持する。 これと共 に停止信号発生手段 2 0 5から停止信号が出力され、 この停止信号が画 像データ取込装置 3 0 δ に入力され画像データの取込を開始させる。 図 2 F は画像データの取得動作期間を示す。  In other words, according to this apparatus, if, for example, the stop patterns r and n are set in the stop pattern setting means 203, the pattern holding means 2 is generated each time the stop patterns r and n are generated. 04 operates to stop the update operation of the test pattern of the test pattern generator 200, and maintains the state where the test pattern r or n is output. Figure 2 shows the situation. Figure 2A shows the start signal, and Figure 2B shows the test pattern signal. When the pattern of the test pattern signal reaches r or n (generally indicates the address indicating the pattern generation order), the pattern holding means 204 temporarily updates the pattern of the test pattern generator 200. Stop and maintain the state where pattern r or n is output. At the same time, a stop signal is output from the stop signal generating means 205, and the stop signal is input to the image data capturing device 30δ to start capturing image data. FIG. 2F shows the operation period for acquiring image data.
画像データの取り込み完了は例えばイ オ ンビームの掃引照射が 1 画面 分に達したこ とを表す垂直帰線信号を検出するこ と によ り知るこ とがで きる。 垂直帰線信号を 1 個ない し任意の個数検出 した と き取得完了信号 を発信させる こ と によ り、 イ オ ンビームが 1 画面分から数画面分の任意 の画面分走査した と き取得完了信号を発信させるこ とができる。 図 2 G に取得完了信号を示す。  Completion of image data capture can be known, for example, by detecting a vertical retrace signal indicating that the ion beam sweep irradiation has reached one screen. By transmitting an acquisition completion signal when one or any number of vertical retrace signals are detected, an acquisition completion signal is output when the ion beam scans one to several screens for any screen. Can be sent. Figure 2G shows the acquisition completion signal.
取得完了信号がパターン保持手段 2 0 4 に与えられるこ と によ り試験 パターン信号発生器 2 0 0は停止状態から開放され、 図 2 B に示すよ う に、 試験パターンを r + l、 r + 2、 …又は n + l、 n + 2…のよ う に 更新し最終パターン L a s t まで出力する。 試験パターンの発生を 1 回 に設定 した場合は最終パターン L a s t を発生 した状態で停止する。 試験パターンの発生を連続して、 また画像データ取得後の再スター ト を先頭のパターンに戻すよ う に設定した場合は、 図 3 に示すよ う に試験 パターン r を発生すると 自動的に停止し、 画像データの取得が完了する と先頭のパターンに戻って再スター ト し、 次回は試験パターン nで停止 し、 画.像データの取得後は再び先頭の試験パターンに戻り、 パターンの 発生を繰返す。 このよ う に設定するこ と によ り特定 した試験パターン r と n を印加した状態の画像データを自動的に複数回取得するこ とができ る。 終了はス ト ップスィ ツチ 2 0 2 を操作する こ と によ り試験パターン の発生を停止させるこ とができる。 A test is performed by giving an acquisition completion signal to the pattern holding means 204. The pattern signal generator 200 is released from the stop state, and updates the test pattern as r + l, r + 2, ... or n + l, n + 2 ... as shown in Fig. 2B. Output up to the last pattern Last. If the test pattern generation is set to one time, the operation stops with the last pattern last generated. If the test pattern generation is set to be continuous and the restart after image data acquisition is set back to the first pattern, the test pattern r is automatically stopped when a test pattern r is generated as shown in Fig. 3. When the acquisition of image data is completed, it returns to the first pattern and restarts, the next time it stops at test pattern n, and returns to the first test pattern after image data acquisition, and repeats pattern generation . With this setting, the image data with the specified test patterns r and n applied can be automatically acquired multiple times. The end can be stopped by operating the stop switch 202.
このよ う に、 この装置によれば電位コン ト ラス ト像を観測したり試験 ノ ターン n と基準と なるパターン r と を停止パターン設定手段 2 0 3 に 設定すれば、 試験パターン発生器 2 0 0の起動と停止動作がイ オンビー ムテスタ 3 0 0側の画像データの取得動作に連動するから、 画像データ の取得条件を変更 しても試験パターン発生器 2 0 0及びイ オンビームテ ス夕 3 0 0側の設定を変更する必要がない。 よ つて操作が簡素化され操 作性を向上するこ とができる。  As described above, according to this apparatus, when the potential contrast image is observed or the test pattern n and the reference pattern r are set in the stop pattern setting means 203, the test pattern generator 20 Since the start and stop operations of 0 are linked to the image data acquisition operation of the ion beam tester 300, the test pattern generator 200 and the ion beam test device 300 even if the image data acquisition conditions are changed. There is no need to change the side settings. This simplifies operation and improves operability.
この出願の発明は、 操作性を向上したこの I C試験装置を利用 して、 良品と不良品の電位コ ン トラス ト を比較し、 I Cの不良部分を特定でき る方法を得るこ とである。 図 1 に示すよ う に複数の画像データ取得手段 3 0 5 A と 3 0 5 B に異なる試験パターンを印加した状態の画像デ一夕 を取込む。 つま り画像データ取得手段 3 ◦ 5 Aに試験パターン r を被試 験素子 D U Tに与えた状態の画像データを取込む。 また画像デ一夕取得 手段 3 0 5 Bに試験パターン nを被試験素子 D U Tに与えた状態の画像 データを取込む。 The invention of this application is to obtain a method of comparing the potential contrast between a good product and a defective product by using the IC test apparatus with improved operability and specifying a defective portion of the IC. As shown in FIG. 1, image data obtained by applying different test patterns to a plurality of image data acquisition means 300A and 300B are captured. That is, image data in a state where the test pattern r is given to the device under test DUT is taken into the image data acquisition means 3◦5A. Also get image data overnight The image data in a state where the test pattern n is given to the device under test DUT is taken into the means 3 05 B.
画像データ取得手段 3 0 5 Aに取込んだ画像データは極性反転して演 算手段 3 0 9 に与えると共に、 画像データ取得手段 3 0 5 Bに取込んだ 画像データをそのま ま演算手段 3 0 9 に与える。 演算手段 3 0 9では画 像データ取得手段 3 0 5 Aと 3 0 5 Bから与え られた画像データを加算 し、 その加算結果をモニタ 3 0 6 に表示する。 演算手段 3 0 9の演算結 果をモニタ 3 0 6 に表示する こ と によ り電位コ ン ト ラ ス ト像は鲜明な画 像と なる。  The image data acquired by the image data acquisition means 300 A is inverted in polarity and applied to the arithmetic means 309, and the image data acquired by the image data acquisition means 305 B is directly used by the arithmetic means 309. 0 9 is given. The calculating means 309 adds the image data given from the image data obtaining means 305A and 305B, and displays the result of the addition on the monitor 306. By displaying the calculation result of the calculating means 309 on the monitor 306, the potential contrast image becomes a clear image.
その理由を以下に説明する。 図 6に試験パターン r を印加した場合に 被試験素子011丁内の配線導体 1, し 2, し 3, し に与えられる電位を示 す。 つま り図 6の例では導体 L , に L論理、 導体 L 2 に H論理、 導体し に L論理、 導体 L 4 に H論理を与えた場合を示す。 一方図 7は試験パ ターン nを印加した場合に被試験素子 D U T内の配線導体 〜L 4 に 与えられる電位を示す。 図 7の例では導体 L > に L論理、 導体 L 2 にし 論理、 導体 L 3 に H論理、 導体 L 4 に H論理を与えた場合を示す。 The reason will be described below. Fig. 6 shows the potential applied to the wiring conductors 1 , 2 , 3 , and 3 in the device under test 011 when the test pattern r is applied. Conductor in the example of means that FIG 6 L, to L logic, H logic conductor L 2, conductors to L logic, the conductor L 4 shows a case of giving the H logic. While Figure 7 shows the potential applied to the wiring conductor ~L 4 of the device under test in the DUT when applying a test pattern n. L logic to the conductor L> in the example of FIG. 7, the conductor L 2 illustrates logic, H logic conductor L 3, the conductor L 4 a case of giving the H logic.
図 8 と図 9にこれらの電位コ ン ト ラス ト像を示す。 図 8は試験バタ一 ン r を印加したと きの電位コ ン ト ラス ト像、 図 9は試験パターン n を印 カロしたと きの電位コ ン ト ラス ト像を示す。 図 8に示す電位コ ン ト ラス ト 像において、 導体 と の電位コ ン ト ラス トは消失され、 導体 L 2 と L 3 の電位コ ン ト ラス トだけが残される。 また図 9 に示す電位コ ン ト ラス ト像において、 導体 と L 4 の電位コ ン トラス ト は消失し、 導体 L z と L 3 の電位コ ン ト ラス トだけが残される。 その理由は導体 L , と L 4 に与えられる電位は試験パターン rの印加時も、 試験パターン nの 印加時も同一の電位であるからである。 Figures 8 and 9 show these potential contrast images. Fig. 8 shows a potential contrast image when test pattern r is applied, and Fig. 9 shows a potential contrast image when test pattern n is applied. In the potential co emissions trusses IMAGING shown in FIG. 8, the potential co emissions trusses bets the conductor is lost, only the potential co emissions trusses DOO conductor L 2 and L 3 are left. In the potential co emissions trusses IMAGING shown in FIG. 9, the potential co down trusts conductor and L 4 are disappeared, only the potential co emissions trusses DOO conductor L z and L 3 are left. The reason is that the potentials applied to the conductors L 1 and L 4 are the same both when the test pattern r is applied and when the test pattern n is applied.
図 1 2 に電位コ ン ト ラス トが消失する様子を示す。 図 1 2 Aは試験パ ターン r と ηを印加している期間と、 イ オンビームの照射期間を示す。 図 1 2 Βは導体 の表面に存在する絶縁膜に発生する電位コ ン ト ラス ト、 図 1 2 Cは導体 L 2 の表面に存在する絶縁膜に発生する ¾位コ ン ト ラス ト、 図 1 2 Dは導体 L 3 の表面に存在する絶縁膜に発生する電位コ ン ト ラス ト、 図 1 2 Eは導体 L 4 の表面に発生する電位コ ン ト ラス ト を 示す。 Figure 12 shows how the potential contrast disappears. Figure 12 A shows the test pattern. The periods during which the turns r and η are applied and the ion beam irradiation period are shown. Figure 1 2 beta are potential co emissions trusses event to occur in the insulating film existing on the surface of the conductor, Fig. 1 2 C is ¾ position co emissions trusses event to occur in the insulating film existing on the surface of the conductor L 2, FIG. 1 2 D potential co emissions trusses event to occur in the insulating film existing on the surface of the conductor L 3, FIG. 1 2 E represents a potential co emissions trusses event to occur on the surface of the conductor L 4.
図 1 2 Bと図 1 2 Eに示すよ う に、 試験パターン r を印加した 1 回目 には電位コ ン ト ラス トは発生する力 その後試験パターン nを印加 した 時点では同一方向の電位が与えられるため、 電位コ ン ト ラス トの発生は なく 、 イ オンビームの照射によ り 電位コン ト ラス トは消失する方向に変 化し、 平衡電位 V s に収束する。 その後試験パターン r と nが交互に印 加されても導体 L , と L 4 の表面に存在する絶縁膜には電位コ ン ト ラス ト は発生 しない。 As shown in Fig. 12B and Fig. 12E, the first time the test pattern r was applied, the potential contrast generated a force.Then, when the test pattern n was applied, the same potential was applied. It is because, rather than the occurrence of potential co-down truss door, I Ri potential con trusses door to the irradiation of Lee Onbimu is strange turned into the direction to disappear, to converge to the equilibrium potential V s. Then the test patterns r and n conductors be marked pressurized alternately L, and potential co emissions trusses DOO the insulating film existing on the surface of L 4 are not generated.
これに対し、 導体 L 2 と L 3 の表面に存在する絶縁膜には試験パター ン r と nが印加される毎に逆極性の電位が与え られるから、 試験パター ン r と nが印加される毎に逆向の電位コ ン ト ラス トが発生する。 In contrast, because the insulating film existing on the surface of the conductor L 2 and L 3 are opposite polarity potential is applied to each of the test patterns r and n is applied, the test patterns r and n are applied Each time, a reverse potential contrast occurs.
以上の説明によ り導体 と L 4 の電位コ ン ト ラス トが消失する理由 が理解できる。 このよう に して残された電位コ ン ト ラス トの何れか一方 、 この例では画像データ取得手段 3 0 5 Aに取得した画像データ (電位 コ ン ト ラス ト と同 じ意) を極性反転して演算手段 3 0 9に与え、 演算手 段 3 0 9で画像データ取得手段 3 0 5 Bに取得した画像デ一夕 と加算す る。 I can understand why I Ri potential co emissions trusses DOO conductor and L 4 disappears the foregoing description. In this example, the polarity of either one of the potential contrasts left in this case and the image data (same as the potential contrast) acquired by the image data acquisition means 300A is inverted. The result is given to the calculating means 309, and added to the image data obtained by the image data obtaining means 305 B by the calculating means 309.
図 1 0は画像データ取得手段 3 0 5 Aに取得 した画像データ (電位コ ン ト ラス ト) を極性反転した画像データを示す。 この図 1 0に示 した画 像データ と図 9に示 した画像データと を加算するこ と によ り、 図 1 1 に 示す画像データが得られる。 図 1 1 に示した画像データは導体 L 2 と し の電位コ ン トラス ト に関して加え合わされて強調されている。 この結 果画像の質が向上し、 解像度のよい電位コ ン ト ラス ト像を得るこ とがで きる。 FIG. 10 shows image data obtained by inverting the polarity of the image data (potential contrast) acquired by the image data acquisition means 305A. The image data shown in FIG. 11 is obtained by adding the image data shown in FIG. 10 and the image data shown in FIG. Image data shown in FIG. 1 1 is a conductor L 2 It has been added and emphasized about the potential contrast of this. As a result, the quality of the image is improved, and a potential contrast image with good resolution can be obtained.
次に、 上述のイ オンビームテス タ 3 0 0 を用いて被測定 I Cの不良部 分を特定する方法の発明について説明する。  Next, a description will be given of an invention of a method for specifying a defective portion of the measured IC by using the above-mentioned ion beam tester 300.
始めに、 良品の I C と不良品の I C との論理信号と電位コ ン ト ラス ト 像との対応表を表 1 に示す。 First, Table 1 shows the correspondence table between the logic signals of non-defective ICs and defective ICs and the potential contrast images.
PC PC
15  Fifteen
【表 1 】 良品と不良品の ^理 ί言号と電位コントラス ト像との対応 [Table 1] Correspondence between non-defective products and defective products and word contrast and potential contrast images
良品 不良品 良品/ Good product Defective product Good product /
降^出 r n* J  Descent r n * J
タ ηη·ターン 電位:!ン Γ '、 :  TA ηη-turn Potential:! ン Γ ',:
項目 · -/ n'、'タ-ン 電位]ン 不 R IU  Item ·-/ n ',' turn potential] no R IU
上の問 SS トラ 像 トラス 笋 IS  Above question SS Tiger Image Truss Sun IS
1 Η α ¾ し I 白色 m 1 Η α し I I White m
9 し 灰色 ■Pi 9 gray
理 灰色  Gray
H H II 灰色 ">、  H H II gray ">,
4 LI 3 Ι(Π  4 LI 3 Ι (Π
し 黒&  Black &
5 白色 有  5 White Yes
6 Li 灰色 有  6 Li Gray Yes
し^理 H  Shiri H
7 i 黒色  7 i black
1 里 H 理 灰色 有 iut 1 ri H ri gray having iut
8 LS 理 Η1¾ϊΙ 黑色 m 8 LS process Η1¾ϊΙ m color m
9 H i し^理 白色 、 9 H i
1 0 灰色 有 «"、 m 白色 1 0 Gray Yes «", m White
1 1 i 灰色 有  1 1 i Gray Yes
1 2 し ½理 H ^理 黒色 有  1 2 Shi H H
1 3 m Li 白色 有 M 1 3 m Li White Yes M
1 4 し^理 灰色 1 4 gray
him 灰色  him gray
1 5 ト 理 灰色 有 1 5 G
1 6 H 2^11 黑色 有 1 6 H 2 ^ 11 黑 with color
論理信号のパターンは H論理と L論理の組み合わせであり、 第 1 試験 パターン r時と第 2試験パターン n時と に同一の電位が与えられる と灰 色の電位コン ト ラス ト像が得られ、 第 1 試験パターン r時で L論理、 第 2試験パターン n時で H論理が与えられる と黒色の電位コ ン ト ラス 卜像 が得られ、 第 1 試験パターン r時で H論理、 第 2試験パターン n時でし 論理が与えられる と 白色の電位コ ン ト ラス ト像が得られる。 The logic signal pattern is a combination of H logic and L logic.If the same potential is applied to the first test pattern r and the second test pattern n, a gray potential contrast image is obtained. When L logic is given at the first test pattern r and H logic is given at the second test pattern n, a black potential contrast image is obtained.H logic is given at the first test pattern r, and the second test pattern is given. When logic is given at time n, a white potential contrast image is obtained.
このこ とを利用 して、 良品と不良品の論理信号の電位コ ン ト ラス ト像 を比較して I Cの不良部分の特定が可能となる。 表 1 は良品と不良品に 起こ り得る論理パターンの組み合わせ して、 良品と不良品の電位コ ン ト ラス ト像の差の有無、 故障検出上の問題の有無を示したものである。 表 1 の項目 3、 項目 8、 項目 9、 項目 1 4 は、 良品と不良品の論理信号が 同 じであるため像が同じ になる。 故障検出上の問題は項目 2 と項目 1 5 である。 つま り、 良品と不良品で各試験パターンの論理レベルが違って いるにもかかわらず差と して表れない。 本発明は、 この故障検出上の問 題を解消する方法である。  By utilizing this fact, it is possible to identify the defective portion of the IC by comparing the potential contrast images of the logic signals of the good product and the defective product. Table 1 shows the combination of logical patterns that can occur between good and defective products, and shows whether there is a difference in potential contrast images between good and defective products, and whether there is a problem in fault detection. Item 3, item 8, item 9, and item 14 in Table 1 have the same image because the logical signals of good and defective products are the same. The problems in fault detection are item 2 and item 15. In other words, it does not appear as a difference even though the logic level of each test pattern is different between good and defective products. The present invention is a method for solving this problem in fault detection.
図 5 にこの発明の動作を説明するための波形図を示す。 この特徴は、 第 1 試験パターン r時に被試験素子の電源をオフ (断) に し、 その状態 でイ オンビームを照射走査し画像データ取得を実行する。 第 1 試験バタ —ン r時は電源オフの状態のため常に L論理となる。 第 1 試験パターン r を終了 して次に第 2試験パターン n時には電源をオ ン (接) に して、 イ オ ンビームを照射走査し画像データ取得を実行する。 この電源のオフ 、 オ ンを繰り返して測定を行う方法の一例を図 4 に示す。 この発明での 方法で、 良品と不良品の電位コ ン トラス ト像の差の有無、 故障検出上の 問題の有無を表 2 に示す。 /13157 FIG. 5 is a waveform chart for explaining the operation of the present invention. This feature is that the power of the device under test is turned off (turned off) at the time of the first test pattern r, and in that state the image data is acquired by irradiating and scanning the ion beam. When the first test pattern is r, the logic is always low because the power is off. At the end of the first test pattern r and then at the second test pattern n, the power is turned on (contacted), the ion beam is irradiated and scanned, and image data acquisition is performed. FIG. 4 shows an example of a method of performing measurement by repeatedly turning off and on the power supply. Table 2 shows whether there is a difference between the potential contrast images of good and defective products and whether there is a problem in fault detection using the method of the present invention. / 13157
1 7  1 7
【表 2 】 良品と不良品の^理信号と電位コン ト ラス ト像との 応 [Table 2] Responses of non-defective and defective products and potential contrast images
( rパターン時電源 OFF )  (Power off at r pattern)
Figure imgf000019_0001
Figure imgf000019_0001
表 2 に示すよ う に故陣検出上の問題がな く なり、 良品と不良品の像の 差異が確実に得られ、 鼋位コ ン ト ラス ト を比較するこ とで、 I Cの不良 部分を確実に特定するこ とができる。 産業上の利用可能性 As shown in Table 2, there is no problem in detecting the position of the defective site, the difference between the image of the good product and the image of the bad product can be reliably obtained, and the defective parts of the IC can be determined by comparing the top contrast. Can be specified reliably. Industrial applicability
以上説明 したよ う に、 本発明によれば異なる試験パターン例えば r と n を交互に印加し、 これによ つて発生する電位コ ン ト ラス トの差を表示 する構成と したから、 試験パターン r 又は nの何れか一方を印加してい る状態の電位コ ン ト ラス ト像よ り画像の質を向上する こ とができる。 こ の結果、 I Cのチ ップ内の配線導体の電位分布をよ り高い精度で解析す るこ とができるから不良箇所を短時間に特定するこ とができる利点が得 られる。  As described above, according to the present invention, different test patterns, for example, r and n are alternately applied, and a difference in potential contrast generated by the test patterns is displayed. Alternatively, the quality of the image can be improved as compared with a potential contrast image in a state in which one of n is applied. As a result, the potential distribution of the wiring conductor in the IC chip can be analyzed with higher accuracy, so that there is an advantage that a defective portion can be specified in a short time.
また試験パターン nをそのまま に、 試験パターン r を順次他の試験パ ターンを選択すれば試験パターン r と nの組み合わせでは見られない他 の導体の電位コ ン ト ラス ト像を見るこ とができる。 更にまた同一の試験 パターン例えば n を繰り返し印加し、 その印加毎に被試験素子 D U Tに 与える例えば電源電圧を変化させるこ と によ り、 異常動作を試験パター ン停止毎に交互に起こ させる こ と によ り、 異常動作する部分だけに電位 コ ン ト ラス ト を発生させるこ とができる。 従ってこの場合は不良箇所を 直接特定せるこ とができ る利点が得られる。  In addition, if another test pattern is selected for the test pattern r in sequence while the test pattern n is left as it is, a potential contrast image of another conductor that cannot be seen by the combination of the test pattern r and n can be seen. . Furthermore, by applying the same test pattern, for example, n repeatedly, and changing, for example, the power supply voltage applied to the device under test DUT for each application, abnormal operation is caused alternately every time the test pattern is stopped. As a result, a potential contrast can be generated only in a portion where an abnormal operation occurs. Therefore, in this case, there is an advantage that the defective portion can be directly specified.
また第 1 試験パターン r時のイ オンビーム照射走査、 画像データ取得 を行う と きに、 被試験素子の電源をオフにするこ とによ り 第 1 試験 r パ ターンでの配線導体の論理を L論理に固定し第 2試験パターン nでは電 源をオンに して画像を取 り込むこ とができる。 この画像の良品の場合と 不良品の場合の比較によ り、 両者に相違が有る場合には必ず電位コ ン ト ラス ト像に差像が表れるため、 I Cの不良部分を特定する こ とができる 利点が得られ、 被測定 I Cの故障の解析に大きな効果を発揮できる。 When performing ion beam irradiation scanning and image data acquisition during the first test pattern r, the power of the device under test is turned off to change the logic of the wiring conductor in the first test r pattern to L. The logic is fixed and the image can be captured by turning on the power in the second test pattern n. By comparing the non-defective product with the non-defective one in this image, if there is a difference between the two, a difference image will appear in the potential contrast image, so it is possible to identify the defective part of the IC. it can Advantages can be obtained, which can be very effective in analyzing the failure of the IC under test.

Claims

請 求 の 範 囲 The scope of the claims
1. 被試験素子の表面にイオンビームを掃引照射し、 各照射点から 発生する 2次電子の!:を計測して上記被試験素子表面の電位分布を画像 と して表示するイ オンビームテスタ ( 3 0 0 ) と、 上記被試験素子に試 験パターン信号を順次更新して与える試験パターン発生器 ( 2 0 0 ) と を具備して構成される I C試験装置 ( 1 0 0 ) において、  1. The surface of the device under test is swept and irradiated with an ion beam, and the secondary electrons generated from each irradiation point! : An ion beam tester (300) for measuring the potential distribution on the surface of the device under test as an image, and a test pattern generator (300) for sequentially updating the test pattern signal to the device under test. In an IC test apparatus (100) comprising:
上記試験パターン発生器 ( 2 0 0 ) 側に、 上記試験パターン発生器 ( 2 0 0 ) のパター ン更新動作をそこで一時停止すべき試験パターンを少 なく と も 2つ設定する停止パターン設定手段 ( 2 0 3 ) と、 上記試験パ ターン発生器 ( 2 0 0 ) が上記停止パターン設定手段 ( 2 0 3 ) に設定 した各試験パターンを発生する毎にその状態でその試験パターンの更新 動作を一時停止させるパターン保持手段 ( 2 0 4 ) と、 上記試験パ夕一 ンの更新動作が停止する毎にそれを表すパターン停止信号を出力する停 止信号発生手段 ( 2 0 5 ) と を設け、  On the test pattern generator (200) side, a stop pattern setting means (200) for setting at least two test patterns for temporarily stopping the pattern update operation of the test pattern generator (200). Each time the test pattern generator (200) generates each test pattern set in the stop pattern setting means (203), the test pattern updating operation is temporarily performed in that state. A pattern holding means (204) for stopping and a stop signal generating means (205) for outputting a pattern stop signal representing the updating operation of the test pattern every time the updating operation of the test panel is stopped,
上記イ オンビームテスタ ( 3 0 0 ) に、 上記停止信号発生手段 ( 2 0 5 ) が上記 2つの停止パターンでそれぞれ供給 した上記パターン停止信 号に応答 して画像デ一夕をそれぞれ取り込む少なく と も 2つの画像デ一 夕取得手段 ( 30 5 A、 30 5 B ) と、 上記 2つの画像データ取得手段 に取得し た画像データの差を求める演算手段 ( 3 0 9 ) と、 上記演算手 段 ( 3 0 9 ) で演算した差の画像データを表示するモニタ ( 3 0 6 ) と を設けたこ と を特徴とする I C試験装置。  The ion beam tester (300) captures image data in response to the pattern stop signals supplied by the stop signal generating means (205) respectively in the two stop patterns to the ion beam tester (300). Two image data acquisition means (305A, 305B), an arithmetic means (309) for calculating a difference between the image data acquired by the two image data acquisition means, and an arithmetic means (309) An IC test apparatus comprising: a monitor (306) for displaying the image data of the difference calculated in (309).
2. ク レーム 1項記載の I C試験装置 ( 1 00 ) において、 上記ィ オンビームテス夕 ( 3 0 0 ) は各上記画像データ取得手段 ( 3 0 5 A、2. In the IC test apparatus (100) described in claim 1, the ion beam test apparatus (300) is connected to each of the image data acquisition means (305A,
3 0 5 B ) が画像データの取得を完了 した らそれを表す上記取得完了信 号を発生する取得完了発生手段 ( 3 0 8 ) を含み、 上記パター ン保持手 段 ( 2 0 4 ) は上記イオンビームテス 夕 ( 3 0 0 ) から画像データの取 得完了を表す取得完了信号の供給を受ける と上記試験パターン発生器 ( 2 0 0 ) のパターン更新を再開させるよう に構成されている I C試験装 置。 The acquisition completion signal indicating the completion of the acquisition of the image data Means for generating an image completion signal (308), and the pattern holding means (204) includes an acquisition completion signal indicating completion of image data acquisition from the ion beam test (300). An IC tester configured to restart the pattern update of the test pattern generator (200) upon receiving the supply of the test pattern.
3. 被試験素子に試験パターンを印加する試験パターン発生器 ( 2 0 0 ) と共に I C試験装置 ( 1 0 0 ) を構成し、 上記被試験素子の表面 にイ オンビームを掃引照射し、 各照射点から発生する 2次電子の量を計 測して上記被試験素子表面の電位分布を画像と して表示するイ オンビー ムテス 夕 ( 3 0 0 ) において、 3. Construct an IC test apparatus (100) together with a test pattern generator (200) for applying a test pattern to the device under test. Sweep irradiate the surface of the device under test with an ion beam, In the ion beam test (300), which measures the amount of secondary electrons generated from the surface and displays the potential distribution on the surface of the device under test as an image,
上記試験パターン発生器 ( 2 0 0 ) が少なく と も 2つの停止パターン でそれぞれ供給したパターン停止信号に応答してそれぞれ取得 した画像 データを取り込む少なく と も 2つの画像デ一夕取得手段 ( 3 0 5 A、 3 0 5 B ) と、 上記 2つの画像データ取得手段 ( 3 0 5 A、 3 0 5 B ) に 取得 した画像データの差を求める演算手段 ( 3 0 9 ) と、 上記演算手段 ( 3 0 9 ) で演算した差の画像データを表示するモニ タ ( 3 0 6 ) と、 を設けた こ と を特徴とするイ オンビームテス 夕。  The test pattern generator (200) captures image data acquired in response to the pattern stop signals supplied in at least two stop patterns, respectively, and at least two image data acquisition means (300) 5A, 305B), calculating means (309) for obtaining the difference between the image data obtained by the two image data obtaining means (305A, 305B), and the calculating means (309) A monitor (306) for displaying the image data of the difference calculated in (309), and an ion beam tester provided with.
4. ク レーム 3項記載のイ オンビームテス 夕 ( 3 0 0 ) において、 上記画像データ取得手段 ( 3 0 5 A、 3 0 5 B ) が所要の画像データの 取得を完了する毎にそれを表す取得完了信号を発生し、 上記試験パター ン発生器 ( 2 0 0 ) に供給するための取得完了信号発生手段 ( 3 0 8 ) を設けた こ と を特徴とするイ オンビームテス夕。 4. At the ion beam test (300) described in claim 3, each time the image data acquisition means (305A, 300B) completes the acquisition of the required image data, it is displayed. An ion beam test device characterized by comprising an acquisition completion signal generating means (308) for generating an acquisition completion signal and supplying the acquisition completion signal to the test pattern generator (200).
5. 被試験素子に試験パターンを印加する試験パターン発生器 ( 2 0 0 ) と共に I C試験装置 ( 1 0 0 ) を構成し、 上記被試験素子の表面 にイ オンビームを掃引照射し、 各照射点から発生する 2次電子の量を計 測して上記被試験素子表面の電位分布を画像と して表示するイ オンビー ムテスタ ( 3 00 ) で、 少な く と も 2つの停止パターンによ り第 1 試験 パターン r及び第 2試験パターン nにおける画像データを取り込む測定 方法において、 5. A test pattern generator (2) that applies a test pattern to the device under test Together with an IC test apparatus (100), sweeping and irradiating the surface of the device under test with an ion beam, measuring the amount of secondary electrons generated from each irradiation point, and measuring the amount of secondary electrons An ion beam tester (300) that displays the potential distribution on the surface as an image in a measurement method that captures the image data in the first test pattern r and the second test pattern n by at least two stop patterns. ,
少なく と も上記第 1試験パターン r時に上記被試験素子の電源をオフ に し、 イ オンビームを照射して第 1画像を取り込み、  At least at the time of the first test pattern r, the power of the device under test is turned off, and the first image is captured by irradiating an ion beam.
少なく と も上記第 2試験パターン nには上記被試験素子の電源をオン に してイ オンビームを照射して第 2画像を取り 込み、  At least for the second test pattern n, the power of the device under test is turned on, and an ion beam is irradiated to acquire a second image.
上記第 1 画像と上記第 2画像の差の画像を求め、  Calculating an image of a difference between the first image and the second image,
上記被試験素子の上記差の画像が、 良品 I Cの上記差の画像と異なる 位置を被測定 I Cの不良部分と特定する、  A position where the image of the difference of the device under test is different from the image of the difference of the non-defective IC is specified as a defective portion of the measured IC.
I Cの不良部分の特定方法。  How to identify defective parts of IC.
PCT/JP1995/002053 1994-04-08 1995-10-06 Ic tester and method of locating defective portions of ic WO1997013157A1 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP6095678A JPH07280890A (en) 1994-04-08 1994-04-08 Ic test system, ion beam tester therefor and method for specifying defective part of ic
US08/418,498 US5592099A (en) 1994-04-08 1995-04-07 IC tester joined with ion beam tester and the detection method of the failure part of IC
DE19513309A DE19513309A1 (en) 1994-04-08 1995-04-07 Ion beam integrated circuit test appts.
PCT/JP1995/002053 WO1997013157A1 (en) 1994-04-08 1995-10-06 Ic tester and method of locating defective portions of ic
KR1019960705778A KR100225011B1 (en) 1995-10-06 1996-10-15 Ic tester and method of locating defective portions of ic

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP6095678A JPH07280890A (en) 1994-04-08 1994-04-08 Ic test system, ion beam tester therefor and method for specifying defective part of ic
PCT/JP1995/002053 WO1997013157A1 (en) 1994-04-08 1995-10-06 Ic tester and method of locating defective portions of ic

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0244270A (en) * 1988-08-04 1990-02-14 Toshiba Corp Method for measuring potential of wiring of semiconductor device
JPH06249928A (en) * 1993-02-25 1994-09-09 Nippon Telegr & Teleph Corp <Ntt> Fault diagnostic method of integrated circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0244270A (en) * 1988-08-04 1990-02-14 Toshiba Corp Method for measuring potential of wiring of semiconductor device
JPH06249928A (en) * 1993-02-25 1994-09-09 Nippon Telegr & Teleph Corp <Ntt> Fault diagnostic method of integrated circuit

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
SCANNING ELECTRON MICROSCOPY, (1986), S. GOERLICH et al., "Capacitive Coupling Voltage Contrast", pages 447-464. *

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