JPS5976439A - Diagnostic method of semiconductor device - Google Patents

Abstract

PURPOSE:To facilitate fault analysis of LSI by appliying in common a test voltage pattern to a normal apparatus and sample, executing scanning by electron beam under a voltage pattern where outputs do not match, and indicating a fault by comparing voltage images through detection of secondary electron in unit of region. CONSTITUTION:Semiconductor devices 10, 11 are irradiated with electron beam by controlling 17 it, the secondary electron is detected 14 through an energy analyzer 13, and an output is supplied to a controller 17 after A/D conversion and additional average processing 22. A test data of apparatuses 10, 11 is read 17 from an auxiliary apparatus 24 and the same data is applied independently through a driver 25. Outputs are independently read and are compared 31 with RAM24 and the result is returned to the controller 17. The X-Y board 8 is driven 26 by a control pulse 17. Matching and unmatching for all regions of apparatus 10, 11 are indicated 27, 28, unmatching region is designated with the cursor consoles 29, 30 and voltage picture of such region is indicated 27, 28 in order to analyze a fault. According to this structure, voltage measurement of wiring of LSI can be performed in unit of fault region for diagnosis of LSI.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method for diagnosing a semiconductor 4i (J), and in particular to failure analysis using an electron beam.

(2) Technical background In recent years, the degree of integration of integrated circuits in semiconductor devices has increased dramatically, and their patterns have become extremely fine. As a result, integrated circuit diagnosis (testing to see if the integrated circuit is working properly, and if it is defective, identifying where the cause is inside the integrated circuit) is a part of product development. It's important, but it's very difficult to get out of the way.

(3) Prior Art and Problems Conventionally known integrated circuit testing equipment that performs the above-mentioned diagnosis tests whether an integrated circuit is good or bad by applying various input signals to the integrated circuit and determining whether the resulting output signal is normal or not. There is. In the case of a defect, the content of the abnormal output signal is further analyzed to estimate where within the integrated circuit the cause of the defect is. If this estimation is insufficient, remove the top plate of the integrated circuit package to expose the integrated circuit chip, touch a metal needle with a minute tip to a specific point on the chip, and measure the voltage. υThe cause of the failure is being identified. However, this mechanical stylus has problems in that it may destroy the integrated circuit, and is not sufficiently spatially resolved and takes time at the top of the furnace, so it cannot be applied to large-scale integrated circuits.

Therefore, a method using an electron beam glove as an alternative method for diagnosing the inside of an integrated circuit has recently been described in "Seimu Bloving", 9 Nikkei Electronics, March 15, 1982 issue, PP 172-201.

This method utilizes the fact that secondary electrons generated when an operating integrated circuit is irradiated with an electron beam contain information about the surface voltage. That is, in the secondary electron signal obtained by detecting these secondary electrons with a secondary playback detector, the signal of secondary electrons generated from a high voltage area is small, and the signal of secondary electrons generated from a low voltage area is small. The signal has a characteristic of being thick.

Therefore, like a scanning electron microscope (SEM), a secondary electron signal obtained by scanning an operating integrated circuit two-dimensionally with a finely focused electron beam is transmitted to the Z-axis ( By inputting electron beam scanning signals to the x and y axes (brightness modulation axis), the display device (CRT) displays an integrated circuit display where high voltage areas are dark and low voltage areas are bright. An image of is obtained. This is a scanning electron microscope (SE
It is well known as the voltage contrast image of M).

Using this method, the surface of the integrated circuit chip can be removed.

Since the pressure status can be clearly understood at a glance, it is a powerful weapon for diagnosing integrated circuits.

However, as the area of semiconductor devices has become larger and the fine pattern size has become smaller in recent years, the discovery and detection of defects in the design, process, etc. of defective devices has become possible using this method of observing voltage contrast images using electron beam scanning. It is difficult to do so alone. That is, the size of the chip is 10. If you take a picture of the entire surface of a chip with a scanning electron microscope for a pattern size of 2 μm, there will be hundreds of photographs.
Two voltage contrast images (voltage line) photographs are required.
Another drawback is that this photograph cannot be deciphered by anyone but a skilled semiconductor device designer in order to analyze it.

In addition, although it is possible to qualitatively judge from voltage image observation that wiring with dark contrast has high intervoltage and wiring with bright contrast has low voltage, quantitatively it is not possible to determine how many volts are applied to the At wiring. It is impossible to know if there are any.

In view of this, the inventors of the present invention have filed the patent application
No. 841 "Failure analysis device for integrated circuits" 1985, 23
I proposed an application. This involves scanning the corresponding areas of a normal semiconductor device and a semiconductor device to be diagnosed with an electron beam, sequentially importing voltage contrast images into a storage device, and displaying the stored data as 1'-Wt Ic and calculating the ratio. However, since the positioning of the corresponding areas of the normal semiconductor device and the semiconductor device to be diagnosed and the comparison of display speed are done using a visual aid, the drawback of time-consuming process at the top of the furnace has not been completely overcome. do not have.

Also, as mentioned above, it is impossible to accurately measure the voltage '=-.

(4) Object of the Invention An object of the present invention is to solve the above-mentioned drawbacks and facilitate failure analysis of large-scale semiconductor devices.

(5) Structure of the Invention In order to achieve the above object, the present invention applies a common test voltage pattern to a normal semiconductor device and a semiconductor device to be diagnosed, and detects a mismatch by comparing the output states of the bidirectional conductor devices. Each semiconductor device is scanned by an electron beam while the test voltage pattern in which the discrepancy was detected is applied to the amphibonic conductor device, and a voltage image is obtained by detecting secondary electrons obtained in the scan, which is divided into multiple parts. By comparing the voltage images of the bidirectional conductor device at the regional position of each semiconductor device, it is possible to display the abnormal state of the semiconductor device in each region, and to measure the wiring voltage in each region where the abnormal state has occurred. (6) Embodiments of the Invention First, an outline of an embodiment of the present invention will be explained. A means for supplying test data to a normal semiconductor device installed in a vacuum chamber and a semiconductor device to be diagnosed using an electron beam device commonly installed outside the vacuum chamber, and outputs of the amphibatic conductor device for the test data independently. A means for detecting and a means for comparing and collating the detected output results are provided to detect discrepancies in the output results of the amphibian conductor, and to analyze the inside of the defective half body.
+ (Performed using a child beam. In the first stage of analysis, the chip of the normal/diagnosed semiconductor device is sequentially scanned two-dimensionally by an electron beam with an aperture of, for example, 500 μm, the secondary electron signal at that time is detected, and AD conversion is performed. The device is equipped with means for sequentially storing and accumulating the voltage images of the above area size in the auxiliary storage device via the !1III control device, and while performing the X-Y stay gradient, the normal semiconductor device and the half to be diagnosed are... A voltage image of the entire surface of the Y-body device chip is acquired.After that acquisition, both voltage data are sent to a pattern comparator, which is a means for automatically comparing the voltage image data of the corresponding area of the amphibonic conductor device chip. Matching degree data is obtained, it is determined whether the voltage images of the corresponding areas match or do not match, and a voltage image mismatch area map of the semiconductor device chip to be diagnosed is obtained and displayed on the display device.

Using this map, it is possible to limit the location of the cause of the defect in the semiconductor device to be diagnosed.

Next, the area where the cause of the defect may exist is estimated from the map, the stage address of the corresponding defective semiconductor area is determined, and the area is moved to the electron beam scanning area by moving the stage.

After the movement is completed, the electron beam is two-dimensionally scanned over the area by digital deflection, and the secondary electron signal at that time is AD converted and written on the display device. On this display device, operate the cursor console attached to the display device, place the cursor on the kt wiring pattern whose voltage is to be measured, and send the coordinates to the control device. These coordinates are in one-to-one correspondence with the digital deflection coordinate position of the electron beam. This coordinate data is input to the deflection control device to position the adult beam on the At wiring, and the energy analyzer analyzes the Ti pressure. While successively changing the voltage, the beam blanker is released for each analysis voltage setting, and the electron beam is irradiated to the At wiring for a certain period of time.
The secondary electronic signals generated therefrom are processed by a signal processing circuit including an addition/average circuit, and then read by a control device. The relationship between this analyzer voltage and the secondary electron signal is called an analysis curve. The At wiring voltage is determined from the amount of shift of this analysis curve in the analyzer voltage axis direction.

Hereinafter, the present invention will be explained in more detail with reference to the drawings.

FIG. 1 shows a system configuration diagram that is one embodiment of the present invention. 2. An electron gun that generates an electron beam 1. A beam blanker that chops the generated electron beam 1. 3. electron beam 1
A focusing lens for focusing and deflecting 4. The objective lens 5 and the X-Y deflection coil 6 constitute a simulator optical system.

In addition, in the sample chamber 7 kept in vacuum, there is an X-Y stage 8.
A semiconductor device under test 10.11 to be analyzed is mounted on a printed board 9 provided on an xy stage 8. These X-Y stages8. Printed board9. Semiconductor device 10.
A metal box 12 that covers 11 is provided. This metal-like box 12 is connected to the energy analyzer 13. This is a shield box to prevent it from reaching the space of the secondary electron detector 14. Between the shield box 12 and the objective diaphragm 15, there is provided an energy analyzer 13 composed of three pieces of metal mesh, for example, 100 meshes.
Approximately 91 circular holes are provided in the center of each metal mesh and in the shield box so that the electron beam 1 can pass through. Shield box 12 and energy analyzer 1
3 can be moved by an X-Y stage 16 from outside the sample chamber 7.

The electron beam 1 is turned on and off by a control device 17 consisting of an electronic computer, and a beam fist blanking controller 18.
This is done by Also, the x-y deflection of the electron beam 1,
- Rotational correction of the y deflection is performed by the control device [17 and the deflection control device 19.

It is generated by irradiating the semiconductor device 10 or 11 with the electron beam 1. Secondary electrons 20 of 0 to several tens of eV are detected by a secondary electron detector 14 through an energy analyzer 13 . The detected secondary electron signal is subjected to AD conversion processing and averaging processing in the signal processing circuit 22, and is then input to the control device 17.

The energy analyzer 13 is a three-layer electric field blocking type,
The first grid 131 is an extraction grid with a voltage of 1-2 KV, and the second grid 132 is a buffer grid with a voltage of 60 KV.
A DC voltage of ~120 μm is applied. The third grid 133 is 0 to number 1 generated from the semiconductor device 1o or 11.
This grid is controlled to detect the energy of secondary electrons 20 having an energy of 0 eV, and a voltage of -10 to 10 V is supplied to this grid 133 by a voltage controller 23 provided outside the vacuum chamber.

The output designation of the voltage controller 23 is made by the control device 17.

The driving of the semiconductor device 10.11 to be tested and the internal reading of the semiconductor device are performed by a plurality of signal lines through a connector 91 of the printed circuit board 9 and a hermetically sealed terminal 92 provided on the wall of the vacuum chamber.

The drive signal is stored in the auxiliary storage device 2 of the control device 17 using test data created in advance when stacking the integrated circuit device.
This is done by reading the data stored in the controller 4 and transmitting it to the driver 25.

From the driver 25, the same test data is applied independently to the semiconductor devices 10.11. Also, the output signals of the semiconductor devices 10.11 are read out independently to the driver 25. Oshi, Semiconductor 10.11
The output signals of are compared with each other and match.

The stage driver 26 controls the control signal sent from the control device 17, and the stepper motor moves the stage in a stepwise manner. This stage driver 26 is provided with a counter for the Y-axis and the Y-axis, and has the function of counting the control pulses sent to the driver 26 from the control device 17 and always maintaining the current position of the stage. ing. Therefore, the control device 17 can know the current position of the x--y stage 8 by reading the counter value.

The display devices 27 and 28 are cathode tube display devices equipped with a 2-6 x 25684 bit video ram and have a spatial resolution of 256 x 256 dots and a brightness of 16 levels. Display is performed. Consoles 29 and 30 are connected to the display devices 27 and 28 so that a cursor can be displayed superimposed on the displayed image, and the cursor can be moved by annealing an X-Y cursor movement mechanism provided on the console 29 or 30. It is done. Further, the position coordinates of the cursor can always be read and retrieved by the control unit @17.

The pattern comparator 31 has two internal random access memories with a capacity of 256 x 256 bits, and
Binary image data to be subjected to pattern comparison is transferred from the device 17 to the memory, and when a comparison start command is given, the double-sided images are compared and the results are returned to the control device 17.

Accordingly, FIG. 2 shows the driving of the semiconductor devices 10 and 11.

A detailed configuration diagram of the driver 25 in this embodiment for comparing output signals is shown. The test data stored in the auxiliary storage device 24 is sequentially read by the control device 17, and the test data is transmitted to the driver 32 of the semiconductor device 10 and the semiconductor device 1.
1 driver 33 in common.

This test data is based on the pins of the semiconductor device, the leads,
A voltage corresponding to the data uQ", -\1" is applied to the light bin having the discrimination information of the light pin.

The voltage information appearing on the read/write bin of the semiconductor device 10.11 is input to the comparator 34, and the voltage is binarized for all pins, and the comparator determines whether it matches or does not match for each corresponding pin. . If all the corresponding pin voltages of the semiconductor devices 10 and 11 match, the test data is replaced and the above process is repeated. On the other hand, if a difference also occurs at the - pin, the comparator 34 sends a mismatch signal 35 to the control device 17.

Upon detecting this discrepancy signal 35, the control device 17 controls the controller 17 that maintains the pressure application state when the discrepancy state occurred.
\The next step is to start analyzing the inside of the semiconductor device using an electron beam.

Next, analysis of the inside of this semiconductor device will be explained.

In the present invention, as means for analyzing a semiconductor device using an electron beam, there is provided a means for creating a map of a mismatch area by comparing the voltages of a normal semiconductor device and a semiconductor device to be diagnosed, and a means for measuring voltage in the mismatch area using an egg beam.

First, the creation of a mismatch area map by voltage image comparison will be explained. Figure 3 shows each chip 3 of the semiconductor device 10.11.
6.37, which are arranged on a printed board 9.

Since the positional relationship between the chips of the semiconductor device and the socket is not strictly defined, the positional relationship with respect to the printed board 9 is not necessarily parallel to the chips 36 and 37 shown in the figure, and there is a left-right misalignment. Semiconductor device 1o, 1
In order to compare the voltage images of the chips 36 and 37 in each corresponding region, it is necessary to rotate the two-dimensional scanning direction of the electron beam in accordance with the rotation direction of the chip. Furthermore, when moving the region within the chip where the voltage image is to be obtained to the scanning position of the electron beam, stage movement ωI control is required that takes into consideration the rotation of the chip and the vertical and horizontal deviations.

Note that the size of this region is set to 50 μm on the X solid line side because it is necessary that the internal At wiring of the semiconductor device can be sufficiently observed on the display device by scanning with an electron beam.

Regarding the comparison of the intra-chip pressure images of the normal semiconductor device 1o and the semiconductor device to be diagnosed 11, each chip 36.
372, . . .) to provide - times of electron beam scanning regions. The electron beam scans this area two-dimensionally in parallel as shown at 3611 in FIG.

The secondary electron signal generated from this scanning point is directly sent to the control device 17 through the signal processing circuit 22 in FIG.
The auxiliary storage device 24 is read using the memory access method.
will be written to. The voltage image of one region is stored in the auxiliary storage device 2.
4, the stage is moved so that the irradiation region of the electron beam comes to an adjacent region (361 to 362) in the chip of the semiconductor device (for example, 1o). This operation is repeated to store the 'fli' pressure image of the entire area within the chip in the auxiliary storage device 24.

Next, similar processing is performed on the other semiconductor device (for example, 11) chip. Each area 361, 362 . . . of the semiconductor device chip 36 , 37 in FIG.
..., 371,372. The voltage image data of ... becomes the data of the voltage ratio axis. Therefore, it is necessary that the scanning matching accuracy of the egg beam for each corresponding area of the chips 36 and 37 is at least as high as the feeding accuracy of the XY stage 8. In order to obtain this accuracy, it is necessary to match the scanning direction of the chip and the electron beam before starting the analysis. Also, chip 36 and chip 3 in FIG.
It is necessary to obtain the stage address of each left corner area of 7.

Therefore, this pressure extraction method will be described below.

Semiconductor device fi? for printed board 9 in FIG.
10.1 ] is generally known, and since the semiconductor device 10.11 with respect to the Zayanagi origin of the x-y stay 8 is also taken, the semiconductor device chips 36 and 37 in FIG.
It is also roughly known as Asahi. Therefore, the position of the overlay exposure mark (for example, a cross-shaped cross-shaped turn made of an At thin film) normally provided on a semiconductor device can be approximately specified in the stage coordinate system.

The approximate stage coordinates of these marks are input to the control device 17 shown in FIG. 1, and the x-y stage 8 is moved to the scanning area of the electron beam. Then, the beam blanker 3 is released and the deflection control device 19 is activated to perform two-dimensional digital scanning of the 500 μm aperture area with a resolution of 256×256. Due to the two-dimensional scanning, secondary electrons 20 are generated from the sample surface, passed through the energy analyzer 13, and detected by the secondary electron detector 14. This detected secondary electron signal is sampled by an AD conversion sampling signal generated in synchronization with the digital scanning, and is transferred to a storage device (not shown) of the control device 17 using a direct memory access method. Upon completion of the two-dimensional scanning of the electron beam (scanning of the area is completed), the beam blanker 3 is activated by the beam-blanker controller 18 to turn off the electron beam 1 again.

The mark image data taken in by the control device 17 is displayed on the display device 27 or 28, and on the display screen, the mark center position and two points on the straight line part of the mark are specified using the full cursor movement console 29 or 30, and the specified coordinates are displayed. is read into the control device 17.

As a result, the control device 17 determines the rotation angle of the chip 36 or 37 of the semiconductor device shown in FIG. 3 with respect to electron beam scanning and the error in the mark position. As a result, the rotation angle with respect to the chip 36 is θ. .

The mark position error is △XO + △Yo, and similarly chip 3
The rotation angle with respect to 7 is θ7. The mark position error is △X1
．． If ΔY, then it is stored in the storage device of the control device 17. The details of the deflection control device 19, which is a rotation correction means that performs two-dimensional scanning of the electron beam on the chips 36 and 37 using such information, are shown in FIG. 4 (C). , respectively Sinθ.+Cosθe or Sinθ++C
The digital data corresponding to osθ is the signal ft1A39
and output to 38. This digital data is multiplied DA converter 40.41.42.4
3 is applied. On the other hand, the signal line 47.48 is converted into a digital signal XIY provided inside the deflection control device 19.
The signal is supplied to the DA converters 40 to 43 via the DA converters 40 to 43.

Therefore, the DA converters 40 to 43 multiply the two signals, the outputs of the DA converters 40 and 41 are subtracted by the operational amplifier 49, and the outputs of the DA converters 42 and 43 are heated by the operational amplifier 50. Ru.

As a result, from the operational amplifier 49, XCo5θ. −YSjnθ0 ・・・・・・・・・・・・
(1) Or X Co 3θ+-YSinθ1 ・・・・・・・・・
...The signal of (2) is obtained.

Also, from the operational amplifier 50, X5inθo+Ycos 06...
・・・・・・(3) Or X S inθ++YCo3θ1 ・・・・・・・・・
...The signal of (4) is obtained.

These signals are applied to the electron optical system X-Y deflection coil 6 via signal lines 51 and 52, respectively.

By this deflection control device 19! The rotation angle θ of the semiconductor chips 36 and 37 shown in FIG.
. , θ,.

Furthermore, in two-dimensional scanning of the electron beam, a digital scan generator 44 provided in the deflection control device 19 is used.
The output signal is used as a digital deflection control signal. Switching between the digital deflection control signal from the control 1ii1 device 17 and the digital deflection control signal from the scan generator 44 is performed by switches 53 and 54, and this switching is performed by ii.
This is done from the i control device 17. From the digital scan generator 44, a zumbling signal of the secondary observer signal is outputted to the signal line 55 to the signal processing circuit 22 shown in FIG.

Therefore, when scanning or irradiating the semiconductor device chip 36 shown in FIG.
The digital value of is transmitted from the control device 17 in FIG. 4 to the signal line 39.
38 respectively. Also x-y stage 8
In the movement control, the origin of the semiconductor chip 36 is corrected using ΔXo and △Yo, and the movement direction is corrected using Sinθ0 and Cosθ0.

Next, details of the means for comparing and collating the semiconductor chip internal voltage data stored in the auxiliary storage device 24 and creating a mismatch area map are shown in FIG.

Voltage image data for each divided region of the semiconductor chips 36 and 37 shown in FIG. 3 is stored in the auxiliary storage device 24. Therefore, the voltage image data of the corresponding chip division area of each semiconductor chip 36, 37 is transferred from the auxiliary storage device 24 to the control device 1.
7, and the data for the semiconductor chip 36 is read out to the random access memory 56 of the pattern comparator 31.
Next, voltage image data for the semiconductor chip 37 is written into the random access memories 5, 7, where each random access memory 56, 57 is composed of 256×256 bits. Upon completion of writing to the image random access memory, a comparison start command is given from the control device 17 to the comparator unit 58.

In the comparator section 58, the 200x200 bit area 561 of the random access memory 57 shown in FIG. 5 71.572. is shown with diagonal lines. ..., cut out into 573 buckets and compare them bit by bit.

The comparator unit 58 counts the results of comparing the bits of the data areas 561 and 571 to 573 cut out in this way, and determines the optimum overlapping state, that is, the state with the minimum number of mismatched bits, and the number of mismatched pits at that time is 62. is sent to the control device 17.

The control device 17 compares the number of mismatch bits 62 with the slice level set in advance in the control device 17, that is, the allowable mismatch bit a, and calculates the number of mismatch bits for each corresponding area of the semiconductor chip 36 and 37 shown in FIG. A match or a mismatch is determined, and the determination result is stored in the control device jii 17.

The above processing is performed on all area data of the semiconductor chips 36 and 37, and the determination results for all areas accumulated and stored in the control device 17 are displayed on the display device 27 or 28. This display state is shown in FIG. 7. The example shown is a comparison map of two semiconductor devices with a chip size of 7 mm, and one rectangle indicates a divided area of 500 μm. There is.

The symbols in the figure indicate that the corresponding regions of the two semiconductor devices do not match, and the openings indicate that they match.

Therefore, when one of the graphic areas is designated on this map from the cursor console 29 or 30, the corresponding voltage images of the semiconductor chips 36 and 37 are read out from the auxiliary storage device 24 to the control device 17, and displayed on the display devices 27 and 28. Display the voltage image. The result is shown in FIG.

Here, what is displayed with bright contrast (white area) is the At wiring of approximately 4 μm, and its voltage is Ov.

Note that the 5V At wiring has a dark contrast, which is almost the same as the insulating film contrast (hatched area) and cannot be identified.

However, as shown in FIG. 8, the semiconductor device chip 36.
The voltage images of the 37 corresponding regions are different.

That is, FIG. 8(4) shows the voltage image of the specified region' of the normal semiconductor device chip 36, and FIG. The wiring in the parts indicated by ■ and 0 in the Bj diagram is not recognized in the diagram.Thus, although it is possible to make a tentative determination of the defective part, it is not possible to make a more detailed determination of the defect.

Therefore, next, we will introduce a method for conducting a more detailed analysis of a defective semiconductor device.
The means for measuring the voltage of the t-wire will be described.

First, the cursor console 30 of the display device @ 28 was operated on the screen of the display device @ 28 that displayed the mismatched area marks and bumps, and after detailed analysis, the area of the defective semiconductor device chip 37 was designated. When, ft11. 'The control device 17 calculates the corresponding stage address of the defective semiconductor device chip 37 from the cursor coordinates, moves the X-y stage 8 to the calculation point L/S, and after completing the movement, displays the wind pressure image of the specified area. It is displayed on display devices 27 and 28.

Then, the voltage image is displayed, and as soon as the voltage is measured using the cursor console 30 attached to the display device 28, one point on the At wiring is indicated. The indicated coordinates are read by the control device 17.

These coordinates are the digital two-dimensional scanning position 1lF of the electron beam.
- and 17J1, and is output as the coordinate data to the deflection control data lines 171, 172 of the deflection control device 19 shown in the fourth sheet, and at that time, the changeover switch 53
．． 54 is set on the control device 17 side.0 By this operation, the electron beam 1 can be positioned on the At wiring specified from the display screen.0 After the positioning is completed, the 3
Voltage controller 2 from control device 17 to grid 133
3, the voltage is increased and applied in a linear knob-like manner in steps of BmV in the range of -10 to 10V. After setting each third grid voltage, the control device fff17 sends a message to the beam blanking controller 18.
A command is issued to turn on the electron beam 1 for 64 μs, and the At wiring is irradiated with the electron beam. During the period of irradiation with lightning or a sub beam, secondary electrons modulated by the voltage are emitted from the At wiring. These secondary electrons are traced through the energy analyzer 13 with the voltage applied to the third grid 133, photoelectrically converted into an electric signal by the secondary single-child detector 14, and sent to the signal processing circuit 22. The signals are AD-converted every 1 μs, and the signals are added for 64 μs, averaged, and sent to the control device 17.

This process is repeated over all steps of the third grid pressure of the energy analyzer 13.

As a result, the energy analyzer 13 shown by XV in FIG.
The relationship between the third group IJ voltage Vc and the secondary electron signal Va, that is, an analytical curve is obtained.

Incidentally, FIG. 9 shows analysis curves for At wiring voltages Ov, Xv, and 5v, but what is desired here is the test voltage indicated by Xv, which is unknown. Therefore, the determination of the voltage of Xv will be described below. , measure the analysis curve in advance,
The secondary electron output of the analysis curve v! Maximum value of I VSM
AX, find the minimum value VSMIυ, and set the output of 1/2 thereof as the slice level VSL. When the secondary electron signal output Vs matching this slice level VSL is given, the third grit L' screaming pressure of the energy analysis 2i13 is determined as At wiring stable pressure O
v and 5v, respectively.

That is, assuming that the grid voltages are VGO and VC, respectively, Vco and Vc are stored in the storage device of the control device 17. In this state, the control device 17 (based on the analysis curve for the voltage Xv of the unknown At wiring just obtained, set the value of 1/2 of the maximum value and minimum value of the secondary electron output Vs as the slice level, Grid voltage value Vcx
demand.

Next, the control device 17 performs the following calculation using the voltage values VG, Va, which have been stored in advance in the storage device.

X = A X Vc x −A X Va6 =-・
...=”(5) A=5/ (VGy Vco
) ・'=””=””’ (6) This allows the unknown A
The voltage X of the t wiring is determined.

Therefore, for example, by specifying the source/drain and gate wiring of a functional element formed on a semiconductor device chip and determining the voltage X for each, it is possible to know the leakage state of the functional element in detail.

(7) As described in detail, according to the present invention, in failure analysis of large-scale, high-density semiconductor devices, a normal semiconductor device and a semiconductor device to be diagnosed are driven with the same test data, and both semiconductor devices are driven with the same test data. When a difference occurs in the output of the equipment, a non-contact, high-resolution electron beam scans the inside of the amphibious conductor device, and voltage abnormalities in the corresponding area are automatically detected and displayed by comparing the voltage images. This function and effect are very effective in locating defective parts of semiconductor devices to be diagnosed, and such functions and effects cannot be obtained with conventional mechanical metal probe probes.

In addition, after estimating the chip area that is the cause of the defect from the discrepancy map obtained by comparing the voltage images of the normal and diagnosed semiconductor devices, it is possible to measure the voltage of the defective location using an electron beam with higher accuracy. Detailed failure analysis can be performed.

[Brief explanation of drawings]

Figure 1 is a system configuration diagram that is an embodiment of the present invention;
The figure is a detailed view of the dry nozzle in Figure 1, Figure 3 is a layout diagram of each chip of the semiconductor device mounted on the printed board, Figure 4 is a detailed view of the electron beam deflection control device in Figure 1, FIG. 5 is a detailed view of the nokuturn contorter shown in FIG. 1, FIG. 6 is a diagram showing the state of reading the contents of the random access memory shown in FIG. 5, and FIG. 7 is displayed on the display device shown in FIG. 1. FIG. 8 is a diagram showing an example of a mismatch area map, FIG. 8 is a diagram showing a voltage image of a semiconductor device displayed on the display device of FIG. 1, and FIG. 9 is a characteristic diagram for measuring wiring voltage. In the figure, 1 is an electron beam, 2 is an Emiko gun, 3 is a beam blanker, 4 is a focusing lens, and 5 is an objective lens. 6 is an x-V deflection coil, 7 is a sample chamber, 8 is x-7 is an electric field blocking energy analyzer, 14 is an x-y stage for moving secondary electrons, and 17 is a control guidebook. 18 is a beam blanking bow controller, 19 is a deflection control device, 20 is a secondary multiplexer, 22 is a secondary multiplexer signal processing circuit, 23 is a voltage controller, 24 is an auxiliary storage device, 2
5 is a semiconductor device driver, 2661x-'I stage driver, and 27.28 is a display device. 2q, 30 is a cursor console, 31 is a pattern comparator, 56.57 is a random access memory, and 58 is a comparator section. 5th eye, 6th eye, 7th eye (A none β diagram)

Claims (1)

[Claims] When a test voltage pattern is commonly applied to a normal semiconductor device and a semiconductor device to be diagnosed, and a mismatch is detected by comparing the output states of the amphibonic conductor device, the test voltage pattern in which the mismatch was detected is applied to the amphibatic conductor device. Each semiconductor device is scanned by an electron beam at the laboratory, and the 2
By obtaining a voltage image by detecting secondary electrons and comparing the voltage images of the bidirectional conductor device in the region of each semiconductor device divided into a plurality of regions, an abnormal state of the region of the semiconductor device is displayed, and the abnormal state is A method for diagnosing semiconductor devices characterized by making it possible to measure wiring voltage in the area where the problem occurs.