JP2901172B2 - Charged particle beam test device and semiconductor integrated circuit test device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention irradiates a semiconductor integrated circuit with a charged particle beam such as an electron beam or an ion beam, measures the amount of secondary electrons generated, and converts the potential distribution of the semiconductor integrated circuit into a grayscale image. The present invention relates to a test apparatus which is used to determine a defective portion by displaying the same.

[0002]

2. Description of the Related Art For example, a semiconductor integrated circuit (hereinafter referred to as an IC) operating in an electron beam test apparatus is irradiated with an electron beam, and the amount of secondary electrons generated at that time is measured. An electron beam irradiation position is sequentially shifted with respect to a pattern, and a grayscale image corresponding to the amount of secondary electrons is displayed. In the display image in this case, for example, as shown in FIG. 6A, wiring pattern images 1 to 4 of the IC appear, but the number of secondary electrons from the wiring to which a high-level potential is applied is small, and the pattern image 1 , 2 are displayed in black. On the other hand, the secondary electrons from the wiring to which the low level potential is applied are large, and are displayed in white in the display image as the pattern images 3 and 4, and the portions 5 other than the wiring 5
Is generated between the secondary electrons in the high-level portion and the low-level portion, and the generated secondary electrons are displayed in gray. The image of FIG. 6A is called a strobe image.

Since an applied test pattern corresponding to the displayed image is known, that is, the normal potential of each wiring is known, it is possible to check whether the IC is operating properly by looking at the displayed image. It is possible to determine which part is abnormal or the like. In addition, the electron beam is horizontally scanned between the timing points set by the test signal and the set timing points, and the horizontal scanning lines are sequentially shifted at each of the two timing points to perform vertical scanning. For example, as shown in FIG. An image is formed in which the axis indicates the position of the horizontal scanning line and the time axis of the test signal. Wiring pattern image in Figure 7A test signal 1a shown in FIG. 7B the corresponding wiring is applied, the wiring pattern image 1 changes with time of the potential of the wiring in from the timing point T ₀ to T ₁ represents, therefore from T ₀ The low-level portion ΔT ₁ is displayed in the wiring pattern image 1 as the first white portion L ₁ , and the next high-level portion ΔT 1
₂ is displayed as the black portion to the next part L ₂ of the wiring pattern image 1, the low level portion of the following is displayed as the next white parts L ₃ of the wiring pattern image 1. The wiring pattern image 2 and 3 are applied test signals 2a and 3a are the corresponding wires respectively, an image corresponding to between the timing points T ₀ to T _1. An image in which the time change of the test signal is also displayed is called an LSM image. This allows the user to know the state of the temporal change on one screen.

[0004]

When the image shown in FIG. 6A is obtained, in order to increase the S / N ratio, when the same image is repeatedly obtained, electric charges accumulate in the insulating protective film on the surface of the IC and are shown in FIGS. 6B and 6C. As described above, the high-level wiring pattern image cannot be distinguished from the low-level wiring pattern image, and the same gray display is finally obtained. Therefore high SN
No ratios could be obtained.

Further, as shown in FIG. 6A, when data in a set pattern of a test signal is taken in, it is impossible to know the time-dependent state of a change based on the application of the test pattern. However, although this can be known in the LSM image, as described above with reference to FIG. 6 , when the LSM image is obtained repeatedly under the same conditions, the image becomes unclear, and S
The N ratio could not be improved.

Further, a plurality of sequential circuits for holding the operation and a plurality of logic circuits for not holding the operation are successively provided.
In C, it was necessary to acquire many images in order to know the stage (place) where the failure occurred and the timing of occurrence of the failure in the test signal.

[0007]

According to the present invention, the trigger signal received from the test signal generator is delayed by the delay means to generate a charged particle beam pulse. It is set corresponding to the horizontal or vertical scanning position for the IC. In addition, I
Every time a condition signal indicating that the operating condition of C has been changed is received, the storage area of the image data is switched to the same.
The image data of the operating condition is accumulated in the corresponding storage area.
Stacked and accumulated. The change of the operating condition is performed every time a predetermined amount of image data, for example, data for one screen is obtained.

When displaying the image data currently being acquired, when displaying the difference between the two image data in the two storage areas, the image data of this difference and the IC pattern shape information are superimposed. May be displayed. The delay by the delay means adds a predetermined delay amount to the set delay amount for each horizontal or vertical scanning unit movement. Alternatively, the scanning of the IC is performed at random, the delay device reads out the delay data stored in advance at the horizontal or vertical position, and sets the delay data in the delay circuit.

[0009]

FIG. 1 shows an embodiment of the present invention. When an electron beam test device is used as the charged particle beam test device 11, a test signal generator 12 is connected to the test device 11. In the electron beam test apparatus 11, an electron beam 14 is generated in a pulse shape in a vacuum chamber 13 and irradiated to an IC 15 in the chamber 13. Secondary electrons generated by the irradiation are detected by the secondary electron detector 16 and are switched as image data by the switching means 17 to the image memory 18,
19 is stored.

Test pattern generator 2 in test signal generator
The test pattern signal, power supply signal, and the like generated from 1 are supplied to the IC 15 as test signals, and the IC 15 operates based on this. In synchronization with the repetition of the test pattern signal, that is, at the beginning of each test pattern signal, a trigger signal is supplied from the trigger signal generator 22 to the delay means 23 in the electron beam test apparatus 11. Furthermore, IC such as operating power supply voltage
15 is changed, a condition signal indicating the change is sent from the condition signal generator 24 to the electron beam test apparatus 1.
1 control unit 25. Although not shown, various test conditions of the electron beam test apparatus 11 can be set in the control unit 25, and the control unit 25 is set in accordance with the setting.
Controls each part. The X scanning means 26 and the Y scanning means 27 are also controlled by the control unit 25, and these scanning means 26 and 27
Controls the electron beam 14 to scan the set portion of the IC 15 horizontally and vertically.

For example, a test signal shown in FIG. 2A is generated,
At the repetition time point, a trigger signal is generated as shown in FIG. 2B, and the trigger signal is set in the control unit 25 in response to the trigger signal as the acquisition of data from timing points T ₀ to T ₁ as shown in FIG. 2C. When the number of data to be taken in per scanning line is set to N, a unit time Δt of (T ₁ −T ₀ ) / (N−1) is obtained, and the delay amount of the delay unit 23 is t _1.
= T ₀ is initially set. The first trigger signal is delayed by t ₁ = T ₀ by the delay means 23 and input to the pulse generator 29, and the pulse generated thereby causes the electron beam 14
Are emitted, and the secondary electrons of the IC 15 are detected. Hereinafter, for each trigger signal, t ₁ = T as shown in FIG. 2D.
Electron beam pulses that are sequentially delayed by Δt from ₀ are emitted, and image data is captured. The electron beam 14 is moved by one pixel in the horizontal direction each time one image data is taken. That is, every time the electron beam 14 is moved by one pixel in the horizontal direction by the X scanning means 26, the delay amount set by the delay means 23 is added by Δt.

Thus, the timing T in one horizontal scan
The image data at _{0 to} T ₁ is captured, similarly, the image data is captured for each horizontal scan, and when the capture of image data for one screen is completed, an acquisition completion signal is sent to the test signal generator 12. . Upon receiving this acquisition signal, the test signal generator 12 changes the IC operating conditions, for example, changes the power supply voltage from 5 V to 4 V to generate a condition signal, and again generates a test signal and a trigger signal, and generates an electron beam. Test equipment 1
As described with reference to FIG. 2, 1 emits an electron beam pulse sequentially shifted in timing for each trigger signal to capture image data.

Similarly, an acquisition completion signal is generated each time image data for one screen is acquired, and an operating condition is alternately changed each time the acquisition completion signal is received to generate a condition signal, a test signal, and a trigger signal. Is repeated. In addition, every time the condition signal is received, the fetching of the image data is alternately switched between the image memories 18 and 19. Timing point when the operation power supply voltage of the IC15 is 5V T ₀ through T ₁ wiring between 1 ', 2',
The potential change on 3 'changes to curves 1a, 2a, 3a in FIG. 3A, which is normal operation. In contrast, line 1 between the timing points T ₀ through T ₁ when the power supply voltage is condition change to 4V ', 2', 3 'potential change on the as shown in curve 1a, 2a, 3a of Figure 3B Let's say That is, the wiring 1 ′ has the polarity of the potential pattern inverted, the wiring 2 ′ has the same potential pattern, and the wiring 3 b is at the timing point T ₂
Polarity is reversed only ~T _3.

When image data is repeatedly acquired in such a state and each image data is displayed on the display unit 31, the acquired image in the normal state of FIG. 3A is as shown in FIG. 3C. That is, the wiring pattern image 1 is displayed in white at the low level of the curve 1a and displayed in black at the high level. The wiring pattern image 2 is gray regardless of whether the curve 2a is at a low level or a high level. This is the same potential curve even when the operating power supply voltage is switched to 4V. That is, since the potential state with respect to the location and time in the wiring 2 'does not change, the protection insulating film is charged. That is, this is the same as the case pointed out in the problem of the prior art. Wiring pattern image 3 becomes a white low-level interval L ₂₃ corresponding to the timing point T ₂ through T _3, the other parts, where, since no change occurs in the switching of the operating conditions for time, a gray .

On the other hand, the image acquired in the abnormal state shown in FIG.
As shown in 3D. That is, the wiring pattern image 1 is a curve 1
Black is displayed at high level and white is displayed at low level.
Image 2 is gray because there is no change as in the case of FIG. 3C.
The wiring pattern image 3 is a tune that has changed due to operation switching.
Section T of line 3a_Two~ T_ThreeL corresponding to the high level of _{twenty three}
Then, it becomes black and the other parts become gray.

As shown in FIGS. 3C and 3D, when the operation state is changed and the power supply voltage is reduced to 4 V in this example, the wiring 1 '
In this case, the display is completely reversed from that in the normal state, and it is understood that the display has become abnormal. Further, it is understood that the display is always different from the normal state in terms of location and time. However, it is also found that no abnormality occurs in the wiring 2 ', and the wiring L' has a portion L on the wiring 3 '.
In _23, it becomes abnormal only section of the timing T ₂ through T ₃ from the low level to the high level is understood.

Further, from the image data shown in FIG.
4A is obtained by subtracting the image data shown in FIG. 4A and displaying the difference image data. That is, the wiring pattern image 1 has a portion L ₀₄ where the normal low level has become the high level,
L ₅₆ is a black, high levels of normal portions L _45, L ₆₁ became low level is displayed in white. The wiring pattern image 2 that did not become abnormal even when the operating conditions were changed does not appear on the display surface at all. Wiring 3 'will only portions L ₂₃ became from a low level to a high level and black, other portions do not appear at all. In the display of FIG. 4A, only the abnormal display appears more clearly than the display of FIGS. 3C and 3D. FIG.
In the display states of C and D, the display state of the abnormality is slightly inferior to the display of FIG. 4A, but the image of each wiring pattern also appears.

When the potential of the wiring 1 'is at the operating power supply voltage of 5 V, FIG.
In the case of B of the curve 1a, reducing the operating power supply voltage to 4V, so that the curve 1a 'of FIG. 4B, when taken remains low, the difference image data image of the image L ₂₃ in FIG. 4C high levels of portions T ₂₃ became low level is displayed in white as. Further if the first half T ₂₄ high-level portion in the curve 1a as curve 1a "becomes low level by the power supply voltage drops, a difference image is only partial T ₂₄ appears as an image L ₂₄ white. Moreover curve When the late T ₄₃ high-level portion of the curve 1a as 1a '''goes low, the difference image appears as only a portion T ₄₃ is the image L ₄₃ white. in this way the present invention, the wiring potential The curves 1 a ″ and 1 a ′ ″ show black and white in the strobe image, respectively.

In a state where the IC 15 is not operated, the surface of the IC 15 is scanned with an electron beam to detect secondary electrons, or a test signal is applied. The shape information (image data) of the surface of the IC 15 is obtained by obtaining a strobe image, etc., that is, for the IC portion corresponding to the display of FIG. 3C, for example, the wirings 1 ', 2', 3 as shown in FIG. 'Can be displayed in two lines, respectively, and the shape information is stored in the memory 32, and the shape information and the difference image data (corresponding to FIG. 4A) are stored. By superimposing and displaying, a notable part can be clearly displayed, and the location on the IC can be easily read.

In the above description, the irradiation timing of the electron beam is increased by Δt at the same time as the movement of the electron beam in the horizontal direction. That is, the image data is acquired so that the horizontal direction on the display surface is the time axis. Image data may be acquired so as to be on a time axis. In this case, on the same horizontal scanning line of the electron beam, the electron beam irradiation timing with respect to the trigger signal is set to a fixed value t _i, and on the next horizontal scanning line, the electron beam irradiation timing is delayed by Δt, and t _i + Δt Irradiation of the electron beam is performed at the timing shown in FIG. Note that in one horizontal scan, the start of the horizontal scan may be earlier by Δt each time one image data is acquired so as not to irradiate the same point.

If the irradiation timing of the electron beam is increased by Δt during one horizontal scan, the vertical scan may be performed randomly. That is, the numbers of the horizontal scan lines are randomly arranged, and the arranged horizontal scans are performed. Line numbers are sequentially selected for each horizontal scan. As described above, when acquiring image data so that the time axis is in the vertical direction, each horizontal scan is performed by randomly arranging each pixel position number on the line, and arranging the electron beam at the selected pixel position in the arrangement order. May be irradiated. By performing the horizontal or vertical scanning at random as described above, it is possible to avoid continuously irradiating an electron beam to an approaching portion and to reduce the influence of the charge of the protective insulating film. This method is particularly effective when increasing the position resolution.

Similarly, the horizontal and vertical scanning may be randomized. For example, as shown in FIG. 5, data necessary to deflect the electron beam to each point on the horizontal scan is stored in the horizontal deflection register 34, and data necessary to deflect the electron beam to each point on the vertical scan is stored. Data that is stored in the vertical deflection register 35 and that indicates the electron beam irradiation timing (delay amount with respect to the trigger signal) for each pixel point on one horizontal scanning line is stored in the delay register 36. A number indicating the position of each point on the entire scanning plane is generated from the random generator 37 , the horizontal deflection register 34 and the delay register 36 are read out using the lower bits as addresses, and the vertical deflection registers 35 are read out using the upper bits as addresses. The data read from the deflection register 34 is converted to an analog signal by a DA converter 38 and supplied to a horizontal direction deflector, and the data read from the vertical deflection register 35 is converted to an analog signal by a DA converter 39 and converted to a vertical signal. The data supplied to the deflector and read from the delay register 36 is set in a delay circuit 41 for delaying a trigger signal.
1 is supplied to the pulse generator 29.

In the above description, the image data under the two operating conditions is alternately obtained. However, the image data under the same operating condition can be added and averaged to improve the SN ratio. The time required to capture one screen of image data depends on the set conditions, but the maximum time is expected, and the test signal generator 12 automatically changes the operating conditions to obtain the electron beam test equipment 11. The acquisition end signal need not be generated on the side. Although the operating condition is changed every time data of one screen is obtained, the operating condition may be changed every time data of a predetermined screen is obtained, such as when data of a half screen is obtained.

[0024]

As described above, according to the present invention, the operating conditions such as the power supply voltage and the test pattern clock frequency can be changed.
Since the LSM image data for a predetermined screen is alternately switched every time the image is acquired, a point of interest can be clearly obtained without being affected by the insulating protective film.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a relationship among a test signal, a trigger signal, an image data acquisition period, and an electron beam pulse irradiation timing in the operation of FIG.

FIGS. 3A and 3B are diagrams showing examples of signals on a wiring, and FIGS.
FIG. 4 is a diagram showing a display example of corresponding acquired image data.

4A is a diagram showing a display example of difference image data, FIG. 4B is a diagram showing a normal signal on wiring and various abnormal signals thereof, FIG. 4C is a diagram showing a display image corresponding to each abnormal signal in B, and FIG. Is I
It is a figure showing an example of a display screen of surface shape information on C.

FIG. 5 is a block diagram showing an example of a random scanning signal generating unit and a corresponding delay unit 23;

FIG. 6 is a view showing a strobe image display example for explaining a problem in the conventional device.

FIG. 7A is a diagram showing an example of LSM image display, and FIG. 7B is a diagram showing a signal on a corresponding wiring.

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Akira Goishi 1-32-1, Asahimachi, Nerima-ku, Tokyo Advantest Co., Ltd. (56) References JP-A-5-322996 (JP, A) JP-A Sho 59-181630 (JP, A) (58) Field surveyed (Int. Cl. ⁶ , DB name) G01R 31/302 G01N 23/225 H01L 21/66

Claims (7)

(57) [Claims] 1. A charged particle beam test apparatus for irradiating a charged particle beam to an operating semiconductor integrated circuit in a pulsed manner and detecting secondary electrons thereof to obtain an image of a potential distribution of the semiconductor integrated circuit. Each time a condition signal indicating that the operating condition of the semiconductor integrated circuit has been changed is received from the test signal generator, a trigger signal is received from a test signal generator that supplies an operation test signal to the semiconductor integrated circuit, and the trigger signal is received. A delay means for generating a charged particle beam pulse by giving a delay corresponding to a horizontal or vertical scanning position of the semiconductor integrated circuit by the charged particle beam, and switching a storage area of image data obtained from the detected secondary electrons. Means and an image of the same operating condition output from the switching means
Means for accumulating and accumulating data, respectively . 2. A test signal generator and a charged particle beam test device, wherein an operation test signal is supplied from the test signal generator to a semiconductor integrated circuit in the charged particle beam test device, and the semiconductor integrated circuit is provided. During operation, the charged particle beam test apparatus irradiates the semiconductor integrated circuit in a pulsed manner with the charged particle beam, detects secondary electrons, and obtains an image of the potential distribution of the semiconductor integrated circuit. In the integrated circuit test apparatus, each time the test signal is repeated by the test signal generator,
Means for transmitting a trigger signal indicating the reference to the charged particle beam test device; and means for transmitting a condition signal indicating the change to the charged particle beam test device when the operating condition of the semiconductor integrated circuit is changed. The trigger signal received after receiving the condition signal to the charged particle beam test apparatus, the charged particle beam pulse by giving a delay corresponding to the horizontal or vertical scanning position with respect to the semiconductor integrated circuit by the charged particle beam delay means for generating and means for switching the storage area of the image data obtained from the detection of secondary electrons, an image of the same operating conditions that are output from said switching means
Means for accumulating and accumulating data, respectively . 3. The test apparatus according to claim 1, further comprising means for displaying a difference between the two image data stored in the image data storage area. 4. The test apparatus according to claim 3, further comprising: means for storing pattern shape information of the semiconductor integrated circuit; and means for superimposing and displaying the pattern shape information and the difference image data. 5. The delay unit according to claim 1, wherein the delay unit is configured to add the predetermined delay amount to the set delay amount by a predetermined delay amount for each horizontal or vertical scanning unit movement to perform the delay. 5. The test apparatus according to any one of 4. 6. The test apparatus according to claim 5, wherein the vertical or horizontal scanning is made random. 7. A means for randomly scanning the semiconductor integrated circuit, wherein the delay means reads out delay data stored in advance in accordance with a horizontal or vertical position in the random scanning, and outputs the trigger signal. 5. The test apparatus according to claim 1, wherein the test apparatus is a means for setting a delay circuit to be delayed.