JPH07318619A - Failure analyzer for ic and charged particle beam tester - Google Patents

Abstract

PURPOSE:To obtain the potential contrast image of a passed product under same conditions by adding the stage position information to a fetched data comprising the address information of a test pattern every time when a potential contrast image is fetched and storing the fetched data. CONSTITUTION:Means 310 fetches stage position information from a stage controller 309 and delivers the information to an image data fetching unit 305. A potential contrast image, fetched at each stage, is added with the stage position information and means 311 fetches a pattern address signal from a test pattern generator 200 and delivers the pattern address signal to the unit 305. The pattern address information is added, along with the stage position information, to the potential contrast image and stored in a large capacity memory 308. The stage position information added to each potential contrast image stored in the memory 308 is fed to the stage controller 309 and the stage 303 is returned back to a target position.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC defect analysis device and a charged particle beam tester capable of analyzing a defective position inside an IC.

[0002]

2. Description of the Related Art An IC tester tests whether or not a circuit connected to each terminal pin led to the outside of a patchage of an IC operates normally. Therefore, it is possible to know which terminal pin is defective in the IC determined to be defective by the IC test apparatus. However, it is not possible to know where in the IC the defect is. Inside the IC,
A charged particle beam tester is generally used to check which part has a defect. The charged particle beam tester irradiates a chip of a device under test with a charged particle beam such as an electron beam, scans the irradiation point to perform surface scanning, and obtains the amount of secondary electrons emitted at each irradiation point. By capturing the signal as a potential contrast image, storing the potential contrast image in a large-capacity storage means such as a hard disk, and reading it as necessary, the potential contrast image at a desired in-chip position can be displayed.

FIG. 2 shows a schematic structure of a conventional IC failure analysis apparatus of this type. In the figure, 100 indicates the entire IC failure analysis apparatus. The IC failure analysis device 100 is roughly divided into a test pattern generator 200 and a charged particle beam tester 30.
0 and. An electron beam is generally used as the charged particle beam, but other charged particle beams may be used in some cases.

The test pattern generator 200 gives a test pattern signal to the device under test DUT mounted on the charged particle beam tester 300. The test pattern generator 200 includes a start switch 201 for starting generation of a test pattern,
The stop switch 202 used to stop the generation of the test pattern at an arbitrary time, the stop pattern setting means 203 for stopping the update of the test pattern when the specified test pattern occurs, and the stop pattern setting means 203. A pattern holding unit 204 for detecting the occurrence of the set test pattern and stopping the update of the test pattern, and controlling the generation start of the test pattern signal, the stop control, and the update operation of the test pattern in the specific test pattern. Is configured so that it can be controlled to stop.

On the other hand, the charged particle beam tester 300 includes a lens barrel portion 3 for irradiating the device under test DUT with the charged particle beam EB.
01, a chamber 302 provided under the lens barrel 301 for placing the device under test DUT in a vacuum, and a chamber 302 provided inside the chamber 302 for moving the position of the device under test DUT in the XY direction. The stage 303 to be operated, the sensor 304 for measuring the amount of secondary electrons generated from the device under test DUT, and the test pattern generated by the pattern generator 200 for the electric signal detected by the sensor 304 reaches a predetermined test pattern. Image data acquisition device 305 and image data acquisition device 3 that are captured as image data
A monitor 306 that displays the image data captured in 05 as a potential contrast image, and a lens barrel controller 307 that controls the emission of the charged particle beam EB and its emission amount (current value), accelerating voltage, scanning speed, scanning area, and the like. , A large-capacity storage means 308 such as a hard disk for storing the image data captured by the image data acquisition device 305 screen by screen.
And a stage controller 309 for moving the stage 303 arranged inside the chamber 302, and a stage position information acquisition means 310.

Acquisition of the potential contrast image is performed as follows, for example. For the device under test identified as a defective product, the electrode position in the chip can be identified from the defective pin number. In many cases, the search for the defective portion in the chip is started from this potential position. The stage 303 is controlled by the stage controller 309, and the stage 303 is moved to a position where the specified electrode 1 enters the irradiation region of the charged particle beam EB.

A1 shown in FIG. 3 shows a potential contrast image obtained at the electrode portion in the chip. Reference numeral 1 is an electrode formed on the chip, and 2 is a bonding wire for electrically connecting the electrode 1 and the terminal pin implanted on the patchage side. The stage position information (X _A , Y _A ) of the stage 303 in the state in which the potential contrast image A1 is acquired is acquired by the stage position information acquisition unit 310, and the stage position information (X _A ,
Y _A ) is stored in the mass storage means 308 added to the potential contrast image A1 by the image data acquisition device 305. The stage position information can be acquired, for example, by the number of pulses given to the pulse motor that moves the stage 303.

The test pattern generator 2 is attached to the device under test DUT.
Test patterns are sequentially given from 00 to operate the device under test DUT. At this time, several hundreds of test patterns are given to the device under test DUT to stop at a certain specified test pattern, and the test pattern is started / started.
The wiring pattern that performs the same operation at the time of 5V operation and at the time of 4V operation in which the power supply voltage is switched to, for example, the normal 5V at each stop, becomes gray and is difficult to see as a potential contrast image. Become. On the other hand, 5V
The wiring pattern in which the potential difference between the time and the time of 4V appears emphasized in white or black depending on the potential change from H to L or from L to H, for example. When various kinds of test patterns to be stopped are selected, the degree of emphasis changes, so the test patterns set in the stop pattern setting means 203 are changed variously to select a pattern that looks good. An IC test apparatus utilizing this phenomenon has already been proposed by the present applicant in "Japanese Patent Application No. 5-301618".

Therefore, the potential contrast image is acquired in the order of A2, A3, A4 by following the wiring pattern 3 which appears white or black, and the defective portion is identified. The stage stop information at the time of acquisition of each potential contrast image A1, A2, A3, A4 is (X _A , Y _A ), (X _B , Y _B ), (X _C , Y _C ),
(X _D , Y _D ) Stage position information acquisition means 310
The image data of each potential contrast image is added to the image data and stored in the mass storage unit 308.

As described above, by capturing and storing the stop position information of the stage 303 each time each potential contrast image is acquired, for example, when acquiring the potential contrast image of the same wiring pattern 3 for a good product,
By using this stage position information, the potential contrast images A1, A2, A3, A at the same position for a good product and a defective product
4 can be acquired. Therefore, it is possible to easily find a defective portion by comparing each potential contrast image between a good product and a defective product.

As another method of use, if the wiring pattern 3 is branched at a point B in the process of sequentially acquiring the potential contrast images along the wiring pattern 3 which is suspected to be defective, the branch point B is branched to one side. As a result of branching and searching for a defective portion like the potential contrast image A4, if no defective portion is found, it is necessary to return to the branch point B, but the potential contrast image A including the branch point B
3 has already been acquired, and the stage position information in that case has been stored as (X _C , Y _C ).
3 can be immediately returned to this branch point B.

Therefore, by storing the stage position information each time the potential contrast image is acquired, there is an advantage that the work for finding the defective portion can be simplified.

[0013]

Conventionally, the data added to the potential contrast image is only the position information of the stage 303. Therefore, when the potential contrast images of the defective products are sequentially acquired and then the potential contrast images of the non-defective products are acquired at the same stage position, the test pattern, which is one of the acquisition conditions, cannot be matched with the same test pattern. Occurs. In other words, if the test pattern applied when acquiring the potential contrast image does not match between the good product and the defective product, the potential given to the wiring pattern does not match between the good product and the defective product, so it is suspected to be defective. Since the white and black highlighting of the wiring pattern also do not match, there is the inconvenience that the defect determination becomes difficult.

It is an object of the present invention to provide an IC failure analysis apparatus capable of acquiring a potential contrast image of a good product and a defective product at the same stage position and with the same test pattern.

[0015]

According to the present invention, when the potential contrast images are sequentially captured in the large-capacity storage means, in addition to the stage position information, the address information relating to the test pattern is added to the potential contrast images and stored. It is to be configured. According to the configuration of the present invention, for example, when a potential contrast image is sequentially acquired along a wiring pattern suspected of being a defective product, stage position information at the time of acquisition and address information of a test pattern are acquired in each potential contrast image. Memorize As a result, when a non-defective product is placed on the stage and a potential contrast image is acquired from the non-defective product at each same stage position, the test pattern signal given at that time can be the same test pattern signal. There is an advantage that comparison of contrast images can be easily performed.

Further, when the wiring pattern suspected of being defective is branched, the test pattern when the potential contrast image is acquired at the branch point can be known even when returning to the branch point, and therefore, the other branch point can be used. Since the test pattern at the starting point when the potential contrast image is obtained along the branched wiring pattern can be immediately specified, it is not necessary to examine the test pattern of the potential contrast image previously obtained at the branch point. Therefore, the work for finding the defective portion can be performed quickly.

[0017]

FIG. 1 shows an embodiment of the present invention. In the present invention, the stage position information output from the stage controller 309 is acquired by the stage position information acquisition means 310 and input to the image data acquisition device 305, and the stage position information is added to the potential contrast image acquired at each stage position. At the same time, the pattern address signal output from the test pattern generator 200 is acquired by the address information acquisition means 311 and input to the image data acquisition device 305, and the pattern address information is added to the potential contrast image together with the stage position information. It is configured to be stored in the mass storage means 308.

Other additional data include numbers assigned to the device under test, codes indicating non-defective products and defective products, numbers indicating the acquisition order of potential contrast images, and the lens barrel controller 307.
It is possible to store the magnification data determined by the scanning width of the charged particle beam EB output from the device and various constants required for the image averaging process performed to improve the resolution when acquiring the potential contrast image.

Since the stage position information and the test pattern address information are added to each potential contrast image stored in the large capacity storage means 308, for example, at the branch point B shown in FIG. 3 or the position of the first electrode 1. Upon returning, the stage position information added to the potential contrast image A1 is given to the stage controller 309, so that the stage 3
03 can be returned to its target position. The address information of the read test pattern is the image data acquisition means 3
It is possible to automatically set the stop pattern of the test pattern at the target position by transferring it from 05 to the stop pattern setting means 203 and storing it in the stop pattern setting means 203 as the stop pattern.

Therefore, for example, when a potential contrast image of a defective product is sequentially acquired along a wiring pattern suspected to be defective, and then a non-defective product is mounted on the stage 303 to acquire a potential contrast image of the same position in the non-defective product as well. Since the stage position information and the address information of the test pattern are stored in the potential contrast image of the defective product, the potential contrast image of the non-defective product can be captured under the same acquisition condition by using these information.

Further, by storing the magnification, which is the control condition of the lens barrel controller 307, and the coefficient required for the averaging process for improving the image quality of the potential contrast image, these conditions are automatically met. Can be made.

[0022]

As described above, according to the present invention, the defective portion of the device under test can be easily searched and the defective portion can be specified in a short time. The advantage of being able to shorten the time, or to quickly identify the cause of a large number of defects in a mass production line, etc. is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram for explaining a conventional technique.

FIG. 3 is a plan view for explaining the operation of the conventional technique.

[Explanation of symbols]

 100 IC failure analysis device 200 Test pattern generator 203 Stop pattern setting means 204 Pattern holding means 300 Charged particle beam tester 301 Lens barrel part 302 Chamber 303 Stage 304 Sensor 305 Image data acquisition device 306 Monitor 307 Lens barrel controller 308 Mass storage memory Means 309 Stage controller 310 Stage position information acquisition means 311 Address information acquisition means A1 to A4 Potential contrast image

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Claims (3)

[Claims] 1. A device under test is irradiated with a charged particle beam,
The surface of the irradiation point is surface-scanned, and the amount of secondary electrons emitted from the wiring pattern existing in the scanning region is captured as an image signal to obtain the potential of each wiring pattern as a potential contrast image, and at the same time, the device under test. It is possible to acquire the potential contrast image at a desired position in the device under test by moving the stage by moving the stage by moving the stage. In the IC failure analysis apparatus having the structure, acquisition condition data including stage position information indicating the stop position of the stage in each potential contrast image and address information of the test pattern at the time of acquiring the potential contrast image, every time the potential contrast image is acquired. And an IC defect analysis device characterized in that the data is stored in a large-capacity storage means. 2. By designating one of the potential contrast images stored in the mass storage means according to claim 1,
An IC defect characterized in that the position of the stage and the test pattern to be given to the device under test can be set to the same conditions as the acquisition of the potential contrast image by the acquisition condition data added to the specified potential contrast image. Analyzer. 3. The IC failure analysis apparatus according to claim 1, further comprising: a test pattern generator for applying a test pattern to the device under test,
A charged particle beam tester, and a pattern address acquisition means for acquiring an address signal of a test pattern output from the test pattern generator each time a potential contrast image is acquired on the charged particle beam tester, and a stage controller for output. A charged particle beam tester, comprising: stage position information acquisition means.