JPS60121583A - Memory control circuit - Google Patents

Abstract

PURPOSE:To simplify the constitution of a memory control circuit and to reduce power consumption by driving at least two memories with the output of a switch for write/read addresses. CONSTITUTION:A write address signal (e) produced from a write address generator 4 is set as e=0, e=1, e=2... at time points t0, t1, t2... by a write clock signal (d) supplied from an input terminal 301. The signal obtained by deleting only 2<4> bits out of the signal (e) is supplied in common to memories 2 and 2' as an address signal among control signals (h). While the signal of 2<4> bits is supplied to memories 2 and 2' in common as a write permission signal. Then latch output signals b and b' of latches 1 and 1' are written to memories 2 and 2'. While data can be read out in almost same way as writing with changeover of a switch 6 and extracted through output terminals 201 and 202 as signals c and c' respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to a memory control circuit used for converting digital signals into two channels and writing and reading them into a memory.

<Prior Art and Problems> Conventional memory control circuits of this type include those shown in FIGS. 1 to 4, for example.

This conventional memory control circuit includes a first latch 111', second launches 3, 3', memories 2, 2', i-input address generators 4, 4', read address generator 5,
It is configured to include switchers 6 and 6'.

The latches 1, 1' and the memories 2, 2' convert the input digital signal a inputted through the input terminal 101 into the write clock signal d inputted through the input terminal 301 at the latches 1, 1'. The signals are latched and written into the memories 2 and 2' as latch output signals s and b' synchronized with the write clock signal d. Also, memory 2, 2' and latch 3, 3/melt, memory 2,
The signal read from 2' is latched by the latches 3 and 3/ in response to the read clock signal f supplied via the input terminal 401, and outputted to the output terminals 201 and 202 as output signals e and e', respectively. It is connected to the.

The write address generators 4, 4r generate write address signals e, e' based on the write clock signal d. Further, the read address generator 5 receives a read clock signal f
A read address signal g is generated accordingly. Furthermore, when the switching devices 6 and 61 are supplied with the spare and inclusive address signals e and e' and the read address signal g, the switches 6 and 61 switch between these two signals e l
Make a note of e' l g as memory control signals h and h'! j 2 , 2'.

The operation of this conventional memory control circuit will be explained with reference to FIGS. 1 to 4.

The input digital signal a is at times jo, jl, t2・
Data Do + Dll D2 in ...
. . . is connected to the latch 1 through the input terminal 101,
l'.

Note that the input digital signal a is time-divided into two channels of 16 channels each. The latch 1.1' receives a latch signal b [data Do to D, Da?] synchronized with the write clock signal d. -D4a:) b' (Data D? Data: l is supplied to the memories 2 and 2'. On the other hand, the write address generators 4 and 4 are supplied with the write clock signal d.
I write address e (Ao-Ay, but 8 bits)
With the address signal, Ao = 2, Al = 21...
...is... ), e' (AO~ATζ content is Ao
- Same as A7. ) occurs.

The correspondence between Zunawaji time to-taa and write addresses e and e' is e, ts6~ta in tO-tls.
ll-ie'.

-t47 is e l t48-t63. is e'...
. . . They occur alternately at regular intervals. Contents of write addresses e and e' and time to
The relationship with -tω is as shown in Figure 3, where e='f
L, tx′t′e=l.

e=2 at t2. e = 3 at t3, e = at --tls
15.

e'=Q at t16, e'=1 at tr7, t
e'=2 in 18, e'=15 in -"-txt, t
e = 16 in az, e = 17° in taa・-・-・
e = 31 at t47, e' = 16 at t4s, t
49, it is generated so that e'=17°...

When writing to the memory 2.2', turn the switch 6°6' to the A side in the figure, and write address signals e, e.
Memory 2.21 with ' as memory control signals h and h'
supply to Therefore, data DO is written to address X of memory 2, data D11 is written to address 1, data D2 is written to address 2, and so on. Similarly, data D16 is stored at address X of memory 2', data D17 is stored at address 1, and data D is stored at address 2.
18... is written.

On the other hand, from the read clock signal f supplied via the input terminal 401, the read address generator 5 generates the time t o'.
, t 1 '..., and a read address signal g having the following relationship is generated. That is, g='TL in to'.

g=l at tII, g=2 at t2'. At tJ', g=3...
. . . A read address signal g is generated, the switch 6.6- is turned to the opening side in the figure, and the read address signal g is supplied to the memo IJ 2 and 2'. Then, at time to I, data DO is sent to the output terminal 201, data D16 is sent to the output terminal 202, and similarly, at time tl', data DI is sent to the output terminal 201, and data DI is sent to the output terminal 202.
02, data D17..., each time to'
, t1', . . . and are taken out as output signals c, c' in FIG.

However, in the above conventional memory control circuit,
As explained above, since two write address generators 4, 4' and switchers 6, 6' were required to correspond to the memory 2.2', the input digital signal a was converted into two channels and the time axis When performing the conversion, there is a drawback that the control of the memories 2 and 2' is complicated and the power consumption increases throughout the multiple circuits.

<Object of the Invention> The object of the present invention is to reduce the number of components of the pledge address generator and switch which were required in the past, to simplify the circuit, and to reduce the power consumption. An object of the present invention is to provide a memory control circuit with improved performance.

<Configuration of the Invention> The memory control circuit according to the present invention includes at least two first
a latch, at least two memories fed with the output of the first latch, at least two second launches fed with the output of the memories, and a write address output from a write address generator. and a switch for switching the read address output from the read address generator, and the memory is driven by the output of the switch.

<Embodiment of the Invention> An embodiment of the present invention will be described below. Incidentally, in the following description, the same or similar parts as in the prior art are given the same reference numerals.

FIG. 5 is a block diagram showing an embodiment of the present invention. FIG. 6 is an explanatory diagram showing an example of a write address signal of a write address generator. The memory control circuit in the illustrated embodiment includes the second latches 1, 1', memories 2, 2',
second latch 3°3', one write address generator 4
, a read address generator 5, and one switch 6.

And latches l, 1' of 2g1 and memories 2, 2'
are connected so that the input digital signal a input through the input terminal 101 is latched by the first latch 1, l' and written to the memories 2, 2' as the launch output signals b, b'. . In addition, the memory 2.21 and the second latches 3, 3' are such that the output signal read from the memory 2.2' is launched by the second latch 3, 3', and the output signal e
, (!') are connected to output terminals 201 and 202.

The write address generator 4 generates a 13' write address signal e based on the write clock signal d inputted through the input terminal 301. Also, read.

The address generator 5 generates a read address signal g based on the read clock signal f inputted through the input terminal 401. Further, the switch 6 switches between the write address signal e and the read address signal g and outputs the signal as a memory control signal to the memories 2 and 2'.

Now, regarding the write address signal e generated from the write address generator 4 shown in FIG. 6+1+, each time to, tl, tz, . . . . . , each '9-included address signal e is to, e=0°11, e=1. t2
Writing is generated as follows: 6=2... This write address signal ei: f) A4 fz
In other words, Figure 6 (2) shows that only 24 bits have been removed.
This signal is 15 to 15 from time tO to txs, 15 to 159 from time t16 to t31, 16 to 322 from time taz to t47, and 16 to 32 from time t4g to t63.
It changes like ゜... On the other hand, for A4, 24 bits, as shown in Figure 6 (3), the time to-txs
in\.

From time t+e to tax, 11 from time taz to t47, 1 from time t48 to tsa, and so on. Therefore, the signal shown in FIG. 6(2) is used as an address signal among the control signals for the memories 2 and 2'.
6 (3) in common to the memories 2 and 2.
It is commonly supplied to the memories 2 and 2' as a write permission signal for '. Then, the launch output signals b, b' of the first latches l, 1' are memo! Written to J 2 , 2'.

Note that the reading of data from the memories 2 and 2' is performed using the switch 6.
, the writing is performed in substantially the same manner as the writing described above, and output signals c and c' are taken out from the output terminals 201 and 202. Also, in the case where there are three or more first and second lunches and memories, the structure may be configured in the same manner as above.

<Effects of the Invention> Since the memory control circuit according to the present invention is as described above, it is possible to perform memory control with fewer components than conventional memory control circuits, and the circuit can be simplified. This has the effect of reducing power consumption.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional memory control circuit, FIG. 2 is an explanatory diagram showing the contents of each signal in the example in FIG. 1, and FIGS. 3 and 4 illustrate the operation of the example in FIG. 1. FIG. 5 is a block diagram showing an embodiment of the present invention, and FIG. 6 is an explanatory diagram of the operation of the write address generator in FIG. 5. 1.1/...first lunch 2,2'-...memory 3
．． 3'...Second launch 4.4'...Write address generator 5...Read address generator 6.61...Switcher e...Full address g...
・Read address signal Applicant: NEC Corporation S Tame Figure 4, Figure 6

Claims (1)

[Claims] at least two first latches, at least two memories fed with the outputs of the first launches, at least two second latches fed with the outputs of the memories, and a write address generator. The write address output from
A memory control circuit comprising a switch for switching read addresses output from a read address generator, and driving the memory with the output of the switch.