JPH04195266A - Bit conversion circuit - Google Patents

Abstract

PURPOSE:To shorten processing time by designating an address to control the switching of the bit arrangement of first and second bit column conversion means and read and write columns in (n) bit row memory by a conversion address generating means. CONSTITUTION:A first bit column conversion means 1 inputs the content of (n) bits of each column in original bit data developed in two-dimensional fashion in (n) rows and (m) columns, and switches the bit arrangement under the control of the conversion address generating means 4. The (n) bits switching the bit arrangement of the means 1 are written on a write column address generated by the means 4 of (n) bit row memory 21, 22,..., 2n, and are called to a row in accordance with a second bit column conversion means 3, respectively. The means 3 inputs the content of (n) bits in each column of (n) bit row memory, and switches the arrangement of bits under the control of the conversion means 4, and outputs them as the data in each column after conversion in parallel. Thereby, it is possible to provide universality for all kinds of bit conversion.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a bit conversion circuit that performs bit conversion of bit data of 0 row and m column expanded in two dimensions, has versatility for all bit conversions, and can process in a short time. The purpose of the bit conversion circuit is to provide a bit conversion circuit that performs bit conversion of original bit data of row 0 and column m expanded two-dimensionally, comprising first and second bit string conversion means; The first bit string converting means inputs the contents of n bits of each column of the original bit data developed two-dimensionally in the 0th row and m columns. Then, under the control of the translation address generation means 4, the bit arrangement is switched, and the n bits whose bit arrangement has been switched in the first bit string conversion means are converted into the translation address of the n bit row memories. Written to the write column address generated by the generating means,
The bit data written in each column of the n bit row memories is read out to a corresponding row of the second bit string converting means, and the second bit string converting means:
The contents of n bits of each column of the n (via) row memory are input, and under the control of the conversion address generation means, the arrangement of the bits is exchanged and output in parallel as data of each column after conversion. , the conversion address generating means converts the first and second bit strings in response to control inputs corresponding to writing each column of original data into the bit row memory and reading data from each column of the bit row memory. The address for controlling the permutation of the bit arrangement of the converting means and the write column and read column in the n bit row memories are configured to generate column addresses that respectively designate them.

(Industrial Application Field) The present invention relates to a bit conversion circuit that performs bit conversion of bit data of 0 rows and m columns expanded in two dimensions.

For example, when processing digital data such as image processing,
It is necessary to perform bit conversion processing such as vertical/horizontal conversion on the two-dimensionally expanded bit data. Since such bit conversion processing often requires a long time to process since it handles a large amount of data, there is a need for a technique to shorten the processing time of bit conversion processing.

[Prior Art and Problems to be Solved by the Invention] Conventionally, when performing bit conversion of bit data of 0 row and m column expanded in two dimensions, for example, the bit operation functions of a microprocessor (shift, comparison, AND , and OR etc.)
This was done using software. For example, as an example, 8 bits x 8 bits with a bit arrangement as shown in the 6th
If we consider the case where bit data is vertically and horizontally converted to obtain 8 bits x 8 bits data with the same arrangement of bits as shown in Figure 7, processing by conventional software is as shown in Figure 8, for example. It is carried out in accordance with the following steps.

As is clear from the procedure shown in FIG. 8, the conventional software-based bit conversion process has a problem in that it takes a long time.

Therefore, conventionally, in order to perform bit conversion processing at high speed, a hardware logic circuit dedicated to individual bit conversion, such as a hardware logic circuit that only performs vertical and horizontal conversion for data of a predetermined width, has been required. is being configured.

However, there is a problem in that hardware logic circuits dedicated to individual bit conversions are not versatile and must be designed and manufactured for each individual bit conversion.

The present invention has been made in view of the above-mentioned problems, and it is an object of the present invention to provide a bit conversion circuit that has versatility for all kinds of bit conversions and can perform processing in a short time. .

[Means to solve the problem]

FIG. 1 is a basic configuration diagram of the present invention. The configuration shown in FIG. 1 is a bit conversion circuit that performs bit conversion of original bit data expanded two-dimensionally in rows 0 and columns m.

In FIG. 1, ■ is the first bit string conversion means, 21.
22, . . . 2n are bit row memories, 3 is second bit string conversion means, and 4 is conversion address generation means.

In a first embodiment of the present invention, the first bit string conversion means 1 inputs the contents of n bits of each column of the original bit data expanded two-dimensionally in the 0th row and mth column, and Under the control of the generating means 4, the arrangement of the bits is changed.

The n bits whose bit arrangement has been swapped in the first bit string converting means 1 are stored in the n bit row memories 28, 22,
. . 2n, the bit data written to the write column address generated by the conversion address generation means 4 and written to each column of the n bit row memories 21, 22, . . . 2n are as follows: Said second bit string conversion means 3
is read out in the corresponding line.

The second bit string converting means 3 inputs the contents of n bits of each column of the n bit row memory, and under the control of the conversion address generating means 4, rearranges the bit arrangement and performs conversion. output in parallel as data for each column.

The above conversion address generation means 4 writes each column of original data to the bit row memory via the first bit string conversion means l, and writes the data of each column of the bit row memory to the second bit string. An address for controlling the swapping of the bit arrangements of the first and second bit string converting means 1 and 3, and the n bit rows described above, in accordance with a control input corresponding to reading through the converting means 3. memory 2
Column addresses specifying the write columns and read columns at 1.22, . . . 2, respectively are generated.

In the second embodiment of the present invention, the first bit string conversion means l inputs the contents of n bits of each column of the original bit data expanded two-dimensionally in the 0th row and mth column, and converts the converted address to the converted address. Under the control of the generating means 4, the arrangement of the bits is changed.

The n bits whose bit arrangement has been swapped in the first bit string converting means 1 are stored in the n bit row memories 23, 22,
. . 2n are written in columns equal to each column of the original bit data, and the n bit row memories 21, 22, . . .
- The bit data written to the read column address generated by the conversion address generation means 4 corresponding to each column of converted data of 2n is respectively written to the corresponding row of the second bit string conversion means 3. Read out.

The second bit string conversion means 3 inputs the bit data written to the read column address generated by the conversion address generation means 4 corresponding to each column of the converted data, and generates the conversion address. Under the control of the means 4, the arrangement of the bits is changed and outputted in parallel as data of each column after the conversion.

The above conversion address generation means 4 writes each column of data of the original data to the bit row memory via the first bit string conversion means 1, and writes each of the converted data in the bit row memory. Controls swapping of bit arrangements of the first and second bit string converting means 1 and 3 in accordance with a control input corresponding to reading of data corresponding to a column via the second bit string converting means 3; address and the above n bit row memories 2I, 2
The write column and read column in 2, . . . 2n are
Generates each specified column address.

[Effect]

According to the first aspect of the present invention, first, when writing each column of original data to the bit row memory, the conversion address generating means 4 is configured to write each column of original data to the bit row memory. By giving a control input to each column of the original data, the bit string converting means 1 converts each column of the original data to After the bit arrangement (row) is converted, it is written to the column position (column address) in the bit row memory of the converted row according to the control input. Next, when reading data in each column of bit row memory,
By applying a control input corresponding to reading of data in each column of the bit row memory to the conversion address generation means 4, the data in each column of the bit row memory is read out in parallel for each column by the second bit string conversion means. 3, and here, the bit arrangement (row) in each column is further converted according to the control input corresponding to the reading of the data in each column described above, and then the data in each column after conversion is output in parallel.

According to the second embodiment of the present invention, first, when writing each column of original data to the bit row memory, the conversion address generating means 4 is configured to write the original data to the bit row memory of each column. By giving a control input to each column of the original data, the bit string converting means 1 converts each column of the original data to After the bit arrangement (row) is converted, it is written to each column position (column address) mentioned above in the bit row memory of the converted row.

Next, when reading data in each column of the bit row memory, a control input corresponding to reading each column of the converted data is given to the conversion address generating means 4, so that the bits corresponding to the control input are The data in each column of the row memory is read out in parallel to the second bit string conversion means 3,
Here, the bit arrangement (row) within each column is further determined according to the control input corresponding to reading the data of each column above.
After the data is converted, it is output in parallel as data for each column after conversion.

According to the configuration of the present invention, from the conversion address generation means 4, the address for controlling the swapping of the bit arrangement of the first and second bit string conversion means 1 and 3, and the above n
In the bit row memories 21° 22, . . . 2n,
The write column according to the first aspect of the present invention or the first write column according to the present invention
By giving a column address that specifies a readout column in the form (depending on the strength of the address), arbitrary bit conversion is possible. The method of giving the address may be calculated and set in advance depending on the type of conversion. It is also possible to set a plurality of address generation modes in advance in the translated address generation means 4, and select one of them in response to a predetermined mode designation input.

Further, after the data in each column of the two-dimensionally expanded bit data of 0 rows and m columns is subjected to bit string conversion by the first bit string converting means 1, n bit row memories 28, 22, . . .
2nl, the n bit row memories 2I, 22,
...By reading the data written in 2n and converting the bit string by the second bit string converting means 3, the data becomes 0.
Since arbitrary bit conversion of the bit data developed in two dimensions in rows and m columns is completed, the delay time required for processing is basically as follows.

This becomes the sum of the time for writing to the memory and the time for reading it, and the processing time can be greatly reduced.

〔Example〕

FIG. 2 is a diagram showing the configuration of an embodiment (of the first form) of the present invention. FIG. 2 shows the configuration of a bit conversion circuit for bit conversion of 8 rows and 8 columns of data expanded two-dimensionally. In the configuration of FIG. 1 described above, n=8
．． It is called m-8. Furthermore, the configuration shown in FIG. 2 is a special example of the configuration shown in FIG. 1, in which the first and second bit string conversion circuits each perform bit conversion using only cyclic permutation. be.

In the configuration shown in FIG. 2, 11 is a first bit string conversion circuit, 121, 122, . . . 12s is a RAM as a bit row memory, 13 is a second bit string conversion circuit, and
14 is a conversion address generation circuit.

Since the addresses in the eight RAMs each designate one of the bits in each column of each row, 3 bits (AO, AI, A2) are sufficient, and the first and second bit string conversion circuits 11 Since the addresses that control the bit conversion of and 13 are also limited to cyclic permutation as described above,
Again, 3 bits (AO, AI, A2) are sufficient.

The conversion address generation circuit 14 in FIG. 2 inputs 3-bit control inputs AO', AI', A2' and write/read control manual input R/W, and converts 3-bits each according to these control inputs. Consisting of RAM 121, 12
2,...128 control addresses <AI>, <A2>,
<A3>, <A4>, <A5>, <A6>, <A7>,
<A8>, the control address <A9> of the first bit string conversion circuit 11, and the control address <AIO> of the second bit string conversion circuit 13 are output. The above control input is given from a CPU (not shown).

FIG. 3 shows the input/output relationship in the conversion address generation circuit 14 when the bit conversion is vertical/horizontal conversion, and FIG. 4 shows the input/output relationship when the first bit string conversion circuit 11 performs only cyclic permutation. , the bit conversion results for the control address <A9>, and FIG. 5 shows the bit conversion results for the control address <AI
The bit conversion result for O> is shown. In Figure 3,
The CPU address during writing (W) indicates each column (number) 0 to 7 of the original data, and the CPU address during reading (R) corresponds to each column (number) 0 to 7 of the converted data. Also, the control addresses <Al>, <A2>, <A3> in FIG.
>, <A4>, <A5>, <A6>, <A7>, <A8
> are the corresponding RAMs 121, 122, . . .
- Indicates the column address of 12s (at the time of writing and reading). According to the first aspect of the invention, R.A.
The read addresses from M122 122, . . . , 128 are equal to each column (number) 0 to 7 of the converted data.

First, the CPU performs write/read control human power R/W.
is in the write (W) state, the CPU address in FIG. 3 is set to 00, and the 0 column of the original data is transferred to the 8-bit data input terminal 00.01 of the first bit level conversion circuit 11 in FIG.
．． ...Apply to D7. Here, since the <A9> output in response to the above control input in FIG. 3 is 00, the 0 column of the original data is output as is from the first bit level conversion circuit 11 as shown in FIG. , RAM12n.
122.

. . 12n, < for the control input of ' above in Fig. 3
AI>, <A2>, . . . Column address determined by A8> output, 00, 01. ...07, respectively. Next, with the CPU address in FIG. 3 set to 01, one column of the original data is transferred to the 8-bit data input terminals DO, Di of the first bit level conversion circuit 11 in FIG.
...Apply to D7. Here, since the A9> output in response to the above control input in FIG. 3 is 01, as shown in FIG.
Bit cyclically shifted first bit level conversion circuit 1
1 and is output from RAM12n. 122,...12g
<A I > for the above control inputs of FIG.

<A2>, ...<A7>, <A8> Column address determined by output, 01.02n ...07
00, respectively. Similarly, up to 7 columns of original data are stored in RAMI21, 122,...12n.
Next, the CPU reads the write/read control manual R/W (R) state by changing the CPU address in FIG. Control address output <AI>, <A
2>, ...<A8>=00,01. ...0
7, the 8-bit data at the addresses in columns 0 to 7 of the data in the RAMs 121, 122, .

Here, since the above CPU address changes from OO to 07 and <AIO> changes from 00 to 07, the above RAM 12n. The 8-bit data at the addresses in columns 0 to 7 of the data 122, . . . 12n are the second
In the bit string conversion circuit 13 of FIG.
=00 to 07, the second bit string conversion circuit 1308 bit data output terminal Do',
Di', . . . D7' output the converted column data onto the CPU bus. In this way, according to the above procedure, the original data as shown in FIG. 6 is vertically and horizontally converted and converted into data as shown in FIG. 7.

Note that the examples shown in FIGS. 3 to 5 correspond to the first embodiment of the present invention, but even if the conversion in FIG. 3 is changed to correspond to the second embodiment of the present invention, Vertical and horizontal conversion is performed in exactly the same way. According to the second embodiment of the present invention, the RAMs 121, 122
, . . , the write address from 128 becomes equal to each column (number) O to 7 of the converted data.

In the configuration shown in FIG. 2 described above, the conversion address generation circuit 1
If the input/output relationship of 4 and the conversion in the first and second bit string conversion circuits 11 and 13 are appropriately determined,
All kinds of bit conversions can be performed. In addition,
The first and second bit string conversion circuits 11 and 13 are
The conversion address generation circuit 14 may be configured by a hardware logic circuit, or if configured by a memory circuit, the input/output relationship can be easily adjusted in response to changes in the type of bit conversion. can be changed to

〔Effect of the invention〕

The bit conversion circuit of the present invention has versatility for all bit conversions and can perform processing in a short time.

[Brief explanation of the drawing]

FIG. 1 is a basic configuration diagram of the present invention, FIG. 2 is a configuration diagram of an embodiment of the present invention, and FIG. 3 is a diagram showing the input/output relationship in the above-mentioned conversion address generation circuit 14 during the above-mentioned vertical/horizontal conversion. 4 is a diagram showing the bit conversion result for the control address <A9> when the first bit string conversion circuit 11 performs only cyclic permutation. FIG. 5 is a diagram showing the bit conversion result for the control address <A9> 13 is a diagram showing the name bit conversion result for the control address <AIO> when only cyclic permutation is performed. FIG. 6 is a diagram showing the bit arrangement of the original data of 8 bits x 8 bits. FIG. 6 is a diagram showing the bit arrangement as a result of vertical/horizontal conversion of the data, and FIG. 8 is a diagram showing the procedure of vertical/horizontal conversion processing by conventional software. [Description of symbols] 1--1 first bit string conversion means, 21, 22, . . .
21, ---bit row memory, 3.--second bit string conversion means, 4, conversion address generation means, 11--first bit string conversion circuit, 12n. 1221...12s・-RA
M, 13-second bit string conversion circuit, 14-conversion address generation circuit;

Claims (1)

[Scope of Claims] A bit conversion circuit that converts original bit data of n rows and m columns expanded in one or two dimensions,
the first bit string converting means (1, 3), n bit row memories (2_1, 2_2, . . . 2_n), and a conversion address generating means (4); ) inputs the content of n bits in each column of the original bit data developed in two dimensions in the n rows and m columns, and rearranges the arrangement of the bits under the control of the conversion address generation means 4;
The n bits whose bit arrangement has been swapped in the first bit string converting means (1) are stored in the n bit row memory (2_1).
, 2_2, .
The n bit row memories (2_1, 2_2,...2_
The bit data written in each column of n) is, respectively,
The second bit string converting means (3) reads each column of the n bit row memories (2_1, 2_2...2_n). n of
The contents of the bits are input and the converted address generating means (
Under the control of 4), the bit arrangement is swapped and output in parallel as data of each column after conversion, and the conversion address generation means (4) converts the first bit string conversion means of each column of original data. (1) in response to a control input corresponding to writing to said bit row memory via said second bit string converting means (3) and reading data in each column of said bit row memory via said second bit string converting means (3); an address for controlling the permutation of the bit arrangement of the first and second bit string converting means (1, 3), and a write column and a read column in the n bit row memories (2_1, 2_2, . . . 2_n); A bit conversion circuit characterized in that it generates a column address specifying each of . 2. In a bit conversion circuit that converts original bit data of n rows and m columns expanded in two dimensions, a first and a second
the first bit string converting means (1, 3), n bit row memories (2_1, 2_2, . . . 2_n), and a conversion address generating means (4); ) inputs the content of n bits in each column of the original bit data developed in two dimensions in the n rows and m columns, and rearranges the arrangement of the bits under the control of the conversion address generation means 4;
The n bits whose bit arrangement has been swapped in the first bit string converting means (1) are stored in the n bit row memory (2_1).
, 2_2, .
2_1, 2_2, ... 2_n), the bit data written to the read column address generated by the conversion address generating means (4) corresponding to each column of converted data is The second bit string converting means (3) reads out the converted address generating means (4) corresponding to each column of the converted data.
The bit data written in the read column address where the conversion address is generated is input, and under the control of the conversion address generation means (4), the arrangement of the bits is changed and outputted in parallel as the data of each column after the conversion. , the conversion address generation means (4) writes data of each column of original data into the bit row memory via the first bit string conversion means (1), and performs the conversion in the bit row memory. said first and second bit string converting means (1, 3) in response to a control input corresponding to reading of data corresponding to each column of subsequent data via said second bit string converting means (3); and a column address that respectively specifies a write column and a read column in the n bit row memories (2_1, 2_2, . . . 2_n). Bit conversion circuit. 3. The bit conversion circuit according to claim 1, wherein the conversion address generating means (4) is constituted by a memory, and the contents of the memory can be changed depending on the type of bit conversion.