JPS60121332U - 8-phase shift pulse generation circuit - Google Patents
8-phase shift pulse generation circuitInfo
- Publication number
- JPS60121332U JPS60121332U JP764984U JP764984U JPS60121332U JP S60121332 U JPS60121332 U JP S60121332U JP 764984 U JP764984 U JP 764984U JP 764984 U JP764984 U JP 764984U JP S60121332 U JPS60121332 U JP S60121332U
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- stage
- output
- phase shift
- generation circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図、第2図は従来の8相シフトパルス発生回路、1
は2人力論理積回路、2は電源波人時の 。Figures 1 and 2 show a conventional 8-phase shift pulse generation circuit.
is a 2-person logical product circuit, and 2 is a power wave human-powered logic circuit.
Claims (1)
用い前段のQ端子と次段のD端子とを接続゛し、かつ最
終段のQ端子の否定出力を初段のD端子に接続し、かつ
クロック端子を共通接続として該クロック端子へクロッ
クパルスを与える4段のフリップフロップ回路に於て、
強制制御端子として共通接続されたセット端子又はリセ
ット端子を用い、1段目のQ端子出力と2段目のQ端子
の否定出力と3段目のQ端子出力の論理積出力を該セッ
ト又はリセット端子に接続したことを特徴とする8相シ
フトノタルス発生回路。The Q terminal is used as an output terminal, the D terminal is used as an input terminal, the Q terminal of the previous stage is connected to the D terminal of the next stage, and the negative output of the Q terminal of the final stage is connected to the D terminal of the first stage, and In a four-stage flip-flop circuit that connects clock terminals in common and supplies clock pulses to the clock terminals,
Using a commonly connected set terminal or reset terminal as a forced control terminal, set or reset the AND output of the first stage Q terminal output, the negative output of the second stage Q terminal, and the third stage Q terminal output. An 8-phase shift notarus generating circuit characterized in that it is connected to a terminal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP764984U JPS60121332U (en) | 1984-01-25 | 1984-01-25 | 8-phase shift pulse generation circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP764984U JPS60121332U (en) | 1984-01-25 | 1984-01-25 | 8-phase shift pulse generation circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60121332U true JPS60121332U (en) | 1985-08-16 |
Family
ID=30486195
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP764984U Pending JPS60121332U (en) | 1984-01-25 | 1984-01-25 | 8-phase shift pulse generation circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60121332U (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5332642A (en) * | 1976-09-07 | 1978-03-28 | Hitachi Ltd | Timing generating circuit |
JPS58161534A (en) * | 1982-03-19 | 1983-09-26 | Nec Home Electronics Ltd | Signal selecting circuit |
-
1984
- 1984-01-25 JP JP764984U patent/JPS60121332U/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5332642A (en) * | 1976-09-07 | 1978-03-28 | Hitachi Ltd | Timing generating circuit |
JPS58161534A (en) * | 1982-03-19 | 1983-09-26 | Nec Home Electronics Ltd | Signal selecting circuit |
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