JPS60120598U

JPS60120598U - memory circuit

Info

Publication number: JPS60120598U
Application number: JP13690784U
Authority: JP
Inventors: 白土　元
Original assignee: 日本電気株式会社
Priority date: 1984-09-10
Filing date: 1984-09-10
Publication date: 1985-08-14

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図は従来の１トランジスタメモリシステムのブロッ
ク図、第２図は第１図の１トランジスタメモリ回路の１
部を示す図、第３図、第４図は増幅器周辺の波形図、第
５図は本考案の実施例の１トランジスタメモリシステム
ブ冶ツク図、第６図は第５図の１都を示す図、第７図、
第８図は本考案の実施例の増幅周辺の波形図である。図において、１０はメモリセル、１１はダミーセル、１
３．１３’はＩ　／　ｏバス、１２，１４は増幅器、１
５．１５’はデコーダ、１６は桁線をそれぞれ示す。Figure 1 is a block diagram of a conventional one-transistor memory system, and Figure 2 is a block diagram of the one-transistor memory circuit in Figure 1.
Figures 3 and 4 are waveform diagrams around the amplifier, Figure 5 is a block diagram of a one-transistor memory system according to an embodiment of the present invention, and Figure 6 shows one part of Figure 5. Figure 7,
FIG. 8 is a waveform diagram around the amplification of the embodiment of the present invention. In the figure, 10 is a memory cell, 11 is a dummy cell, 1
3.13' is I/O bus, 12,14 is amplifier, 1
5.15' indicates a decoder, and 16 indicates a digit line.

Claims

[Scope of utility model registration request]

a first cell having memory cells arranged in rows and columns, the memory cell arrays being arranged in geometrically distinct regions;
and a second group of rows of memory cells, each having a first and a second input, the first input being connected to the first
The row group is supplied with read information from the memory cells belonging to the first row group and belonging to each column, and the second input is supplied with the read information from the memory cells belonging to the second row group and belonging to the first row group. a plurality of differential amplifier circuits configured to be supplied with read information from memory cells belonging to columns corresponding to the columns of the first row group; a first input/output bus line; and a second input/output bus line. a bus line, an output amplification circuit whose first and second inputs are supplied with signals from the first and second input/output bus lines, respectively, and a selected one of the differential amplification circuit. a first decoding means for supplying a first output of the differential amplifier circuit to the first input/output bus line; and a first decoding means for supplying a second output of the selected differential amplifier circuit to the second input/output bus line. and second decoding means for supplying a second decoding means.