JPS6155299U - - Google Patents
Info
- Publication number
- JPS6155299U JPS6155299U JP6911885U JP6911885U JPS6155299U JP S6155299 U JPS6155299 U JP S6155299U JP 6911885 U JP6911885 U JP 6911885U JP 6911885 U JP6911885 U JP 6911885U JP S6155299 U JPS6155299 U JP S6155299U
- Authority
- JP
- Japan
- Prior art keywords
- pair
- input
- potential
- differential amplifier
- output terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003321 amplification Effects 0.000 claims 1
- 238000003199 nucleic acid amplification method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 6
Description
第１図は従来の１トランジスタメモリシステム
のブロツク図、第２図は第１図の１トランジスタ
メモリ回路の１部を示す図、第３図、第４図は増
巾器周辺の波形図、第５図は本考案の実施例の１
トランジスタメモリシステムブロツク図、第６図
は第５図の１部を示す図、第７図、第８図は本考
案の実施例の増幅器周辺の波形図である。
図において、１０はメモリセル、１１はダミー
セル、１３，１３′はＩ／Ｏバス、１２，１４は
増巾器、１５，１５′はデコーダ１６は桁線をそ
れぞれ示す。
Fig. 1 is a block diagram of a conventional one-transistor memory system, Fig. 2 is a diagram showing a part of the one-transistor memory circuit shown in Fig. 1, Figs. 3 and 4 are waveform diagrams around the amplifier, and Figs. Figure 5 shows an example of the present invention.
A transistor memory system block diagram; FIG. 6 is a diagram showing a part of FIG. 5, and FIGS. 7 and 8 are waveform diagrams around the amplifier of the embodiment of the present invention. In the figure, 10 is a memory cell, 11 is a dummy cell, 13 and 13' are I/O buses, 12 and 14 are amplifiers, and 15 and 15' are decoders 16 and digit lines, respectively.
Claims (1)
その記憶情報を該桁線に与える複数のメモリセル
を有し、該桁線は２本毎に桁線対を構成するよう
になされたメモリ回路において、一対の入出力端
子を有し該一対の入出力端子の内高い方のレベル
にある一方を第１の電位に、該一対の入出力端子
の内低い方のレベルにある他方を第２の電位にそ
れぞれ増幅しうる複数の差動増幅回路と、該差動
増幅回路の一対の入出力端子を該桁線対にそれぞ
れ接続する手段と、一対の入力端子を有する出力
差動増幅回路と、該差動増幅回路を選択し、選択
された差動増幅回路の一対の入出力端子を該出力
差動増幅回路の一対の入力端子に接続する手段と
、該差動増幅回路の増幅動作に先立つて各桁線を
第３の電位に設定する手段とを備え、該第３の電
位は該第１の電位よりも低くかつ該第２の電位よ
りも高い値であることを特徴とすをメモリ回路。 A plurality of memory cells are connected to the word line and the digit line and provide stored information to the digit line when the word line is energized, such that every two digit lines form a digit line pair. The memory circuit has a pair of input/output terminals, one of which is at a higher level of the pair of input/output terminals is at a first potential, and one of the input/output terminals of the pair of input/output terminals is at a lower level. a plurality of differential amplifier circuits each capable of amplifying the other to a second potential; means for respectively connecting a pair of input/output terminals of the differential amplifier circuits to the pair of digit lines; and an output difference having a pair of input terminals. a dynamic amplifier circuit, means for selecting the differential amplifier circuit and connecting a pair of input/output terminals of the selected differential amplifier circuit to a pair of input terminals of the output differential amplifier circuit, and the differential amplifier circuit. means for setting each digit line to a third potential prior to the amplification operation, and determining that the third potential is lower than the first potential and higher than the second potential. Features and a memory circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6911885U JPS6155299U (en) | 1985-05-10 | 1985-05-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6911885U JPS6155299U (en) | 1985-05-10 | 1985-05-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6155299U true JPS6155299U (en) | 1986-04-14 |
Family
ID=30604493
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6911885U Pending JPS6155299U (en) | 1985-05-10 | 1985-05-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6155299U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4873031A (en) * | 1971-09-30 | 1973-10-02 |
-
1985
- 1985-05-10 JP JP6911885U patent/JPS6155299U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4873031A (en) * | 1971-09-30 | 1973-10-02 |
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