JPS591198U

JPS591198U - memory circuit

Info

Publication number: JPS591198U
Application number: JP715983U
Authority: JP
Inventors: 白土　元
Original assignee: 日本電気株式会社
Priority date: 1983-01-20
Filing date: 1983-01-20
Publication date: 1984-01-06

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図は従来の１トランジスタメモリシステムのブロッ
ク図、第２図は第１図のブロック図の１部部回路を示す
図、第３図、第４図は増巾型周辺の波形図、第５図は本
考案の一実施例のブロック図、第６図は第５図の１部回
路図、第７．８図は来者４案の実施例の増巾型周辺の波
形図である。図において、１０．１０’・・・メ裕リセル、１１゜１
１′・・・ダミーセル、１３．１３’・・・Ｉ１０バス
、１３．１４・・・増巾器、１５．１５’−・・・列デ
コーダ、１６．１６’・・・桁線、１７．１７’・・・
語線、１８・・・行デコーダを示す。Fig. 1 is a block diagram of a conventional one-transistor memory system, Fig. 2 is a diagram showing a partial circuit of the block diagram in Fig. 1, Figs. 3 and 4 are waveform diagrams around the amplified type, and Figs. FIG. 5 is a block diagram of an embodiment of the present invention, FIG. 6 is a partial circuit diagram of FIG. 5, and FIGS. 7 and 8 are waveform diagrams around the amplified type of the embodiment of the present invention. In the figure, 10.10'... Mellycell, 11°1
1'...Dummy cell, 13.13'...I10 bus, 13.14...Amplifier, 15.15'-...Column decoder, 16.16'...Digit line, 17. 17'...
Word line, 18 . . . indicates a row decoder.

Claims

[Scope of utility model registration request]

a first memory cell having memory cells arranged in rows and columns, the memory cell arrays being arranged in geometrically distinct regions;
and a group of memory cells divided into a second group of rows, each having a first and a second input, and the first input has a group of memory cells belonging to the first group of rows and belonging to each column. read information from memory cells belonging to the second row group and corresponding to each column of the first row group is supplied to the second input. a plurality of differential amplifier circuits to which output information is supplied, a first input/output bus line, a second input/output bus line, and a first input/output bus line;
and an output amplifier circuit whose second inputs are supplied with signals from the first and second input/output bus lines, respectively; and means for supplying a second output of the selected differential amplifier circuit to the second input/output bus line. memory circuit.