JPS60120600U

JPS60120600U - memory circuit

Info

Publication number: JPS60120600U
Application number: JP13690984U
Authority: JP
Inventors: 白土　元
Original assignee: 日本電気株式会社
Priority date: 1984-09-10
Filing date: 1984-09-10
Publication date: 1985-08-14

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は従来の１トランジスタメモリシステムのブロッ
ク図、第２図は第１図の１トランジスタメモリ回路の１
部を示す図、第３図、第４図は増幅周辺の波形図、第５
図は本考案の実施例の１トランジスタメモリシステムブ
ロック図、第６図は第５図の１部を示す図、第７図、第
８図に本考案の実施例の増幅器周辺の波形図である。図において、１０はメモリセル、１１はダミーセル、１
３．１３’はＩ１０バス、１２．１４は増幅器、１５．
１５’はデコーダ１６は桁線をそれぞれ示す。味− Ｌ−一− ペ酬と不３日　　　′− ！　　ｉ−１、汁７，７゜！ｉ、Ｉ　　　Ｉ　　　　Ｉ　　ψ２！１ｍ１−］ｉＴ　Ｉ　□ｉ　　　゛１■ｌ。・１ｒ　　　　　’１〜　　■■ よ２７［］１一一一一一十ゝ、ゝ、ゝ、猪腕ｌ；へろ− べ°ルアラフ。！　　　　−ｍ− ２−一一一一一＼Figure 1 is a block diagram of a conventional one-transistor memory system, and Figure 2 is a block diagram of the one-transistor memory circuit in Figure 1.
Figures 3 and 4 are waveform diagrams around the amplification area.
The figure is a block diagram of a one-transistor memory system according to an embodiment of the present invention, FIG. 6 is a diagram showing a part of FIG. 5, and FIGS. 7 and 8 are waveform diagrams around an amplifier according to an embodiment of the present invention. . In the figure, 10 is a memory cell, 11 is a dummy cell, 1
3.13' is the I10 bus, 12.14 is the amplifier, 15.
15' indicates the digit line of the decoder 16, respectively. Taste-L-1-Pe exchange and non-3 days'-! i-1, soup 7.7°! i, I I I ψ2!1m1-] iT I □i ゛1■l.・ 1 R '1 ~ ■■ Yo 27 [] 1 1 1111110, ゝ, boar arm L; ! -m- 2-1111\

Claims

[Scope of utility model registration request]

having memory cells arranged in rows and columns, the memory cell array having a group of memory cells divided into first and second groups of rows, and first and second inputs, respectively; The first input is supplied with read information from memory cells belonging to the first row group, and the second input is supplied with read information from memory cells belonging to the second row group. a plurality of differential amplifier circuits, a first input/output path line, a second input/output path line,
an output amplifier circuit whose first and second inputs are respectively connected to the first and second input/output path lines via the first and second switches; means for supplying a first output of the selected differential amplifier circuit to the first input/output path line; and means for supplying a second output of the selected differential amplifier circuit to the second input/output path line. and write input supply means connected to the first and second input/output path lines via third and fourth switches, respectively.