JPH035299U - - Google Patents
Info
- Publication number
- JPH035299U JPH035299U JP6656389U JP6656389U JPH035299U JP H035299 U JPH035299 U JP H035299U JP 6656389 U JP6656389 U JP 6656389U JP 6656389 U JP6656389 U JP 6656389U JP H035299 U JPH035299 U JP H035299U
- Authority
- JP
- Japan
- Prior art keywords
- potential
- bit line
- input
- pair
- sense amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011159 matrix material Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
Description
第１図は本考案センスアンプの回路図、第２図
は従来のセンスアンプ及びメモリセルを示す回路
図、第３図はセンスアンプの出力の波形図、第４
図はノイズ除去回路の回路図である。
３……ビツト線、４，５……ＭＯＳトランジス
タ、６，７……ＮＯＲゲート、８……差動アンプ
、２０……ＭＯＳトランジスタ。
Figure 1 is a circuit diagram of the sense amplifier of the present invention, Figure 2 is a circuit diagram showing a conventional sense amplifier and memory cell, Figure 3 is a waveform diagram of the output of the sense amplifier, and Figure 4 is a circuit diagram of the sense amplifier of the present invention.
The figure is a circuit diagram of a noise removal circuit. 3... Bit line, 4, 5... MOS transistor, 6, 7... NOR gate, 8... Differential amplifier, 20... MOS transistor.
Claims (1)
レス情報に従つて特定のメモリセルが指定され、
指定されたメモリセルに接続されるビツト線の電
位の変動を検知するセンスアンプであつて、 直列接続されて一方が電源に接続されると共に
他方が上記ビツト線に接続される一対のＭＯＳト
ランジスタと、 入力の一方に上記ビツト線が接続されて他方に
動作制御信号が入力され、出力がビツト線側の上
記ＭＯＳトランジスタのゲートに接続される論理
ゲートと、 上記動作制御信号に従つて上記ビツト線の電位
を接地電位にせしめるスイツチ手段と、 上記一対のＭＯＳトランジスタの接続点の電位
を判定する判定手段と、 を備えてなることを特徴とするセンスアンプ。 (2) 上記判定手段は、 上記一対のＭＯＳトランジスタ間の電位を基準
電位と比較する差動増幅回路と、 この差動増幅回路の出力を入力の一方とすると
共に上記動作制御信号を入力の他方とする論理ゲ
ートと、 からなることを特徴とする請求項第１項記載の
センスアンプ。[Claims for Utility Model Registration] (1) A specific memory cell is designated according to address information from a plurality of memory cells arranged in a matrix,
A sense amplifier that detects changes in the potential of a bit line connected to a designated memory cell, and includes a pair of MOS transistors connected in series, one of which is connected to a power supply and the other connected to the bit line. , a logic gate having one input connected to the bit line and an operation control signal input to the other, and an output connected to the gate of the MOS transistor on the bit line side; A sense amplifier comprising: switch means for setting the potential of the MOS transistor to ground potential; and determination means for determining the potential of the connection point of the pair of MOS transistors. (2) The determination means includes a differential amplifier circuit that compares the potential between the pair of MOS transistors with a reference potential, and the output of the differential amplifier circuit as one input and the operation control signal as the other input. 2. The sense amplifier according to claim 1, comprising: a logic gate; and a logic gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6656389U JPH035299U (en) | 1989-06-06 | 1989-06-06 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6656389U JPH035299U (en) | 1989-06-06 | 1989-06-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH035299U true JPH035299U (en) | 1991-01-18 |
Family
ID=31599376
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6656389U Pending JPH035299U (en) | 1989-06-06 | 1989-06-06 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH035299U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63110541U (en) * | 1987-01-10 | 1988-07-15 |
-
1989
- 1989-06-06 JP JP6656389U patent/JPH035299U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63110541U (en) * | 1987-01-10 | 1988-07-15 |
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