JPH0412556B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention divides each bit line into a plurality of blocks, allows the bit lines of each block to be connected in series by a switch, and provides a sense amplifier to each block. With regard to the provided semiconductor memory device, it is an attempt to further speed up the read operation and further improve the degree of integration.

[Conventional technology]

As the capacity of semiconductor memory increases, each word line
Although the number of memory cells connected to a bit line increases, this increases the load capacitance of the word line and bit line, which hinders high-speed operation. To improve this point, the word line or bit line may be divided.

FIG. 4 shows an example in which the bit lines in each column are divided into a plurality of parts, and BL ⁰ _i , ⁰ _i , BL ¹ _i , ¹ _i , . . . are the divided bit line pairs in the column. _C00 ～ _C0o ， _C10
~C _1o , ... are memory cells belonging to the same column, but C ₀₀ ~C _0o are connected to the bit line pair BL ⁰ _i , ⁰ _i and
C ₁₀ to C _1o are connected to bit line pairs BL ¹ _i , ¹ _i and divided into blocks. BK ₀ , BK ₁ , ... represent such blocks. Each block BK ₀ , BK ₁ ,
. . are respectively provided with sense amplifiers SA ₀ , SA ₁ , . . . and are activated by block selection signals BS ₀ , BS ₁ , . S ⁰ _i and S ⁰ _i ′, S ¹ _i and S ¹ _i ′, ... are switches that connect and open the bit lines of the block in series, and Q ₁ and Q ₂ are controlled by the column selection signal Y. The transfer gate, DB, is a data bus. Figure 5 is a detailed diagram of each part, (a) is the bit line precharge circuit provided in each block, (b)
and (c) is a bit line connection switch. The precharge circuit PRE ₀ in (a) is composed of transistors Q ₃ to _{Q 5} and precharges the bit line pair BL ⁰ _i and ⁰ _i to the same potential (Vcc-Vth) when a precharge signal p is applied. The same applies to the precharge circuits of other blocks. The switch in (b) turns on transistor _Q6 with clock φ,
The switch (c) turns on the opposite conductivity type transistor _Q7 connected in parallel with _Q6 at the same time.

In the memory with the above configuration, when the word line of block BK ₀ is selected and the i-th column cell belonging to the word line is selected, only the sense amplifier SA ₀ is activated by the block selection signal BS ₀ . . As a result, the voltage difference between the bit lines BL ⁰ _i and ⁰ _i is expanded, and
In this state, all switches S ⁰ _i , S ⁰ _i ′, S ¹ _i , S ¹ _i ′,...
is turned on to connect each bit line in series, and gates Q ₁ and Q ₂ are opened by column selection signal Y to connect these bit line pairs to data bus DB.
Read data onto the data bus.

[Problem that the invention seeks to solve]

The advantage of the bit line division described above is that the load capacitance of each sense amplifier during sensing operation is small (only for one divided bit line pair). However, when the switches S ⁰ _i , S ⁰ _i ′, S ¹ _i , S ¹ _i ′, . . . are turned on to connect the bit line pairs, the load capacitance of the sense amplifier increases to the value before the bit line division.
Therefore, the time it takes to finally generate the required voltage difference on the data buses DB and DB' is not so shortened. The present invention aims to improve this problem by limiting the bit line connections after the sense operation to only those necessary and by devising the sense amplifier, and also aims to improve the degree of integration and reduce power consumption. be.

[Means for solving problems]

The present invention divides each bit line into a plurality of blocks, allows the bit lines of each block to be connected in series with a switch, and each block is provided with a sense amplifier, so that following word line selection, the selected word line is connected in series. Only the sense amplifier in the block to which it belongs is operated, and the switch on the data bus side of the selected block is turned on to transmit the bit line potential of the selected block to the data bus, and the sense amplifier of each block is turned on. The feature is that the drive capacity is set to be larger as the distance from the data bus increases.

[Effect]

When the bit line connection switch is off, each block is separated and the load capacitance is small, so the sense amplifier in the selected block can be operated to quickly expand the bit line potential difference, and the selected By limiting the switches that are turned on to connect the bit lines of blocks to the data bus from the selected block to the data bus side, it is possible to minimize the increase in load capacitance for the sense amplifiers in the selected block. By setting the drive capability of a device farther from the data bus in terms of its circuit to a larger value, reading speed can be further increased. This will be explained in detail below with reference to illustrated embodiments.

〔Example〕

In the present invention, the word line (not shown) of block BK ₁ in FIG.
Assuming that a column is selected, first, the differential voltage generated on the bit line pair BL ¹ _i , ¹ _i by word line selection is converted into a signal.
The sense amplifier SA ₁ is activated and increased by BS ₁ , and then the switches S ¹ _i , S ¹ _i ', ... are closed to connect the bit lines BL ¹ _i , ¹ _i of the selected block to the data bus.
Connect to DB. The switch to be closed is a switch located on the data bus side from the selection block in terms of circuitry, so in this example, the switches S ⁰ _i and S ⁰ _i ' are not closed but remain open. Selected block is BK ₀
If ^the selected block is the final block on _the data bus side, then only one switch is closed ( _the final block is the gate ^Q ₁ , Q If it is directly connected to ₂ , the switch that will be closed is 0). A circuit for generating signals for such control is shown in FIG.

The circuit in Fig. 1 is connected to the switches S ⁰ _i , S ⁰ _i ′, S ¹ _i ,
Generate clocks φ ₀ , φ ₁ , etc. that turn on S ¹ _i ′, . These clocks φ ₀ , φ ₁ , . . . are the same as the clocks φ explained in FIGS. 5b, 5c, etc. in terms of timing. However, all clocks φ ₀ to _{φ o-1} are generated simultaneously only when the block BL ₀ furthest from the data bus DB is selected; otherwise, the selected block is the data bus DB,
As DB approaches, the generated clocks become non-generated in order from _φ0 . For example, as mentioned above, when block BK ₁ is selected, clock φ ₀ is not generated, and when block BK _o-1 (the block closest to the data bus) is selected, only clock φ _o-1 is generated. Not done. This includes φ ₀ as BS ₀ as shown.
, φ ₁ is generated at BS ₀ and BS ₁ , and so on. OG ₁ to OG _o-1 are OR gates for taking such logic, BS ₀ to _{BS o-1} are block selection signals that activate the aforementioned sense amplifiers SA ₀ to _{SA o-1} , and AG ₀ ~AG _o-1 is an AND gate that allows clock φ to pass when the condition is met.

By using a clock generation circuit with such a limiting function, only the bit line from the selected block to the data bus side is connected after the sense operation, so compared to the case where all switches are turned on, the sense amplifier of the selected block is The increase in load capacity is kept to a minimum. For example, when block BK ₁ is selected, the bit lines BL _0,0 of block _{BK 0} do not need to load the sense amplifier SA ₁ .

Since blocks higher than the selected block (used to mean farther away than the data bus) are not used in this access, it is also possible to perform control without precharging (or bit line reset) as explained in Figure 5. By doing so, you can also save on power consumption.

As described above, when only the sense amplifier of the selected block is operated and only the switch on the data bus side of the selected block is closed, the bit line of the unselected block between the selected block and the data bus is connected to the bit line of the selected block. When connected to a line, its capacitance and potential reduce the potential difference between the bit lines of the selected block, increasing access time. The degree of this varies depending on the position of the selected block, and the higher the position, the longer the access time will be. In other words, the bit line capacity of the kth block is
C _BL and data bus capacity C _DB , when the jth block is selected, its sense amplifier SAj
Since the load capacitance C _SAj driven by is C _SAj = ( _o 〓 ^k=j C _BL ^(k) ) + C _DB (n is the number of bit line divisions in one column),
The higher the sense amplifier in the block, the larger the load capacitance. Therefore, if the drive capability of the sense amplifiers of each block is made the same, the farther the sense amplifier is from the data bus, the harder it is to drive the load, that is, the bit line and data bus, and the expansion of the potential difference between them becomes slower. Therefore, in the present invention, the drive capability of the sense amplifier of each block is made different, and increases as the distance from the data bus DB increases. In the example of FIG. 4, the driving capacity of SA ₀ is the maximum, and decreases as SA ₁ , . . . SA _o-1 approach the data bus. As a result, the increase in load capacity can be offset by the increase in drive capacity, and the access times of all blocks can be made equal.

FIG. 2 shows details of the sense amplifier SA provided in each block of FIG. 4. In the figure,
Q ₁₀ , Q ₁₂ are p-channel MOS transistors, Q ₁₁ ,
Q ₁₃ to Q ₁₄ are n-channel MOS transistors.
Q ₁₀ , Q ₁₁ and Q ₁₂ , Q ₁₃ each constitute a CMOS inverter, and these two inverters are also cross-connected to constitute a flip-flop.
Transistor _Q14 is turned on by block selection signal BS and is activated when this sense amplifier is selected. In the present invention, these transistors Q ₁₀
~ Q ₁₄ size (channel width) sense amplifier
Maximize at SA ₀ and decrease as you get closer to the data bus. To give a numerical example, about 64K
In the case of RAM, the data bus capacity is about half the bit line capacity, so the load capacity of the sense amplifier of the block furthest from the data bus is 3, that of the nearest block is 1, and that of the middle block is 2. The transistor size (channel width) of the sense amplifier can be determined based on this ratio; the farthest one is 3, the middle one is 2, and the closest one is 1. The farther the transistor is, the longer the sense amplifier length along the bit line is. .

To explain an example of the operation of this memory with reference to the time chart in Figure 3, at time t ₀ the address is
When Add changes, a precharge signal p is generated, and all bit line pairs BL ⁰ _i , ⁰ _i , . . . are precharged to the same potential (for example, Vcc-Vth). Next, if word line WL ₀ (see FIG. 5) is selected at time t ₁ , cell C ₀₀ is selected in the column of FIG. 4, and bit line pair BL ⁰ of block BK ₀ is selected according to the cell information. A minute potential difference occurs between _i and ⁰ _i . Therefore, at time _t2, the block selection signal BS ₀
When BL 0 i and BL 0 i are set to H to activate the sense amplifier SA ₀ (transistor Q ₁₄ is turned on in FIG. 2), the potential difference between the bit line pair BL ⁰ _i and BL ⁰ _i is amplified. When a sufficient voltage difference is applied to BL _i and BL _i by this sensing operation, the clock φ is set to H at time t ₃ and the switches S ⁰ _i , S ⁰ _i ′, S ¹ _i , S ¹ Turn on all _i ′,…. In this case, the clock φ is a general term for the output clocks φ ₀ to _{φ o-1} in FIG. Also, all switches are turned on by setting the selection block to the top level.
This is because this is an example of operation with BK ₀ .

Immediately after turning on these switches, the potentials of the other bit lines BL ¹ _i , ¹ _i , ... are precharged intermediate values, so the bit lines of the selection block BK ₀
The H side of BL ₀ , ₀ decreases, and the L side increases. However, in this example, the power capacity of the sense amplifier SA ₀ is large, so even in this case where the load is maximum, the bit line pair BL ⁰ _i , ⁰ _i (the same goes for BL ¹ _i , ¹ _i and below)
The potential difference quickly returns to the value just before _t3 . The broken line in FIG. 3 shows the conventional bit line potential change. As a result, the time _t5 at which the address Add can be changed next is brought forward, and the speed is increased.

If the selected block is located far from the data bus, there is also a method of activating the sense amplifiers of unselected blocks between them, but with this method, the control of the sense amplifiers becomes somewhat complicated. In this regard, the method of the present invention, in which only the sense amplifiers of the selected block are driven, and the drive capability of the sense amplifiers of the blocks further from the data bus is increased, has the advantage that the sense amplifiers can be easily controlled.

In addition to changing the drive capacity of the sense amplifier for each block, it is also possible to set the drive capacity of the sense amplifiers of all blocks to the maximum value (the value required for the farthest block). However, in this case, a block close to the data bus will naturally have too much capacity, and will not only be wasteful, but also
If a close block is selected, the sense amplifier in question will drive too little load, so the potential difference between the bit lines will rapidly increase.
There are drawbacks such as the peak current becoming large and causing noise generation.

Bit line division is performed not only in static RAM but also in dynamic RAM. In the case of static RAM, the memory cells C ₀₀ ,
... is a flip-flop whose pair of input and output ends are connected to bit line pairs BL ⁰ _i , ⁰ _i , ...,
In the case of a dynamic RAM, the memory cells C ₀₀ , . . . are generally one-transistor, one-capacitor type cells, and are connected to one of the bit line pairs BL ⁰ _i , ⁰ _i , . In the case of dynamic RAM, if it is an open type, the pair of bit lines extends to both sides of the sense amplifier, and if it is a folded type, the pair of bit lines extends to one side of the sense amplifier, as shown in Figure 4, so bit line division is performed. The folded type is easier to do. In the folded type, the structure shown in FIG. 4 is exactly the same except that the memory cell is connected to only one bit line.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to increase the read speed of a bit line division type semiconductor memory device, it is possible to achieve high integration by saving space, it is possible to improve the speed-power product, and it is possible to reduce noise. There are advantages such as no occurrence of such occurrences.

[Brief explanation of drawings]

1 and 2 are main circuit diagrams showing one embodiment of the present invention, FIG. 3 is an operating waveform diagram, FIG. 4 is an explanatory diagram of a conventional bit line segmented memory, and FIG. 5 is its operation waveform diagram. It is a detailed diagram of each part. In the figure, BK ₀ , BK ₁ , ... are blocks, BL ⁰ _i ,
BL ¹ _i ,... are bit lines, S ⁰ _i , S ¹ _i ,... are bit line connection switches, SA ₀ , SA ₁ ,... are sense amplifiers,
DB is a data bus.

Claims (1)

[Claims] 1 Each bit line is divided into a plurality of blocks, the bit lines of each block can be connected in series by a switch, and each block is provided with a sense amplifier, so that following word line selection, the bit lines in the block to which the selected word line belongs The sense amplifier of each block is operated, and the switch located on the data bus side of the selected block is turned on to transmit the bit line potential of the selected block to the data bus, and the drive capacity of the sense amplifier of each block is controlled. A semiconductor memory device characterized in that a device farther from a data bus is set larger.