JPS60117970A - Clamping circuit - Google Patents

Abstract

PURPOSE:To ensure the extremely high accuracy with a clamping action by providing a charging circuit and a discharging circuit to a clamping capacitor and a differential amplifier which controls the working states of both charging and discharging circuits in response to the difference between a reference potential and the capacitor potential. CONSTITUTION:In a clamping mode a clamp pulse input terminal [base of a transistor (TR) 9] is set at a low level and the TR9 is cut off. A collector current flows to a TR8. The TRs 8 and 7 whose bases and emitters are short- circuited respectively form a so-called current mirror. The collector current equal to that of the TR8 flows to the TR7. The TR7 drives with a constant current the common emitter of differential amplifiers TRs 5 and 6 by the constant current characteristics of said collector current. The base potential V0 of the TR5 is set equal to the potential (reference potential to be clamped) at a base point A of the TR6.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a 7271 circuit for clamping a video signal to a predetermined reference potential.

(Prior art) Conventionally, this type of device has been used to, for example, clamp the television video signal to a certain level, thereby regenerating the DC component of the video signal that was lost due to AC coupling, or reducing the hum superimposed on the video signal. It is used to make a person's appearance.

FIG. 1 is a diagram for explaining the principle of a clamp circuit, which includes a capacitor C connected in series to a signal source A, a switch S that is closed in synchronization with, for example, the horizontal retrace period of a video signal, It consists of a clamp power supply E. In addition, 几@, at,
, indicates the Rdl resistance.

In the above configuration, the switch S has a charging time constant τc−C(
If the capacitor Ct-t is kept open for a long time compared to Ra + d)K, it will be charged to the voltage E, and its discharge time constant τd=C(几8+)LL) is sufficiently large compared to the horizontal scanning period. In this case, the level of the video signal during the retrace period is always clamped to approximately the clamp voltage E.

FIG. 2 is a diagram showing an example of a specific circuit of a conventional clamp circuit, in which a transistor T constituting a truncated transmitter follower is shown.
An input signal is applied to the base input terminal l of r1. This signal is applied via a capacitor C to the base of a transistor Tr2 constituting an emitter follower, and an output terminal 2 is provided at its emitter. On the other hand, transistor T
A switching transistor Illrr5 connected to the switch S is connected to the base of r2, a clamp pulse input terminal 3 is provided at its base, and a circuit consisting of a capacitor C11 and a resistor R2 is connected to its emitter. The clamp voltage is given by 'jl.

In the above configuration, when a clamp pulse is applied to terminal 3, transistor Tr3 becomes conductive, and transistor Tr2
The base of is clamped to the clamp voltage E, which is equal to 0. Therefore,
Regardless of the level of the input signal applied to the terminal 1, the input signal is clamped to the clamp voltage E during the period in which the clamp pulse exists.

Therefore, as mentioned above, the clamp circuit using a transistor as a switch has good clamping operation in one direction, but cannot sufficiently perform the reverse direction and the input signal from terminal l (accurately). When the input signal voltage appearing at the emitter (input signal voltage appearing at the emitter) is larger than the clamp voltage E, the amplification degree of the transistor Tr3 is large, so it is possible to perform a good ramp operation, but when the input signal is smaller than the clamp voltage, the voltage flows through the transistor Tr3. The current flows in the opposite direction to the above-mentioned combination i, and the amplification is small enough to not perform the lamp operation. That is, the operation of the transistor Tr3 differs depending on the direction of the operating current. Furthermore, in the case of the reverse direction, the current required for clamping is supplied from the base of the transistor Tr3, so there is a problem in that the drive circuit requires a large power source.

Furthermore, there is a potential difference of one pn junction between the clamped voltage and the output terminal 2, and the clamp voltage applied to the output terminal 2 also has the disadvantage of varying with temperature.

(Objective) The present invention has been made in view of the above-mentioned drawbacks of the conventional example.An object of the present invention is to ensure that the level of the signal to be clamped is always good regardless of the magnitude of the clamp voltage level, so that lamp operation can be performed. The present invention is to provide a clamp circuit.

Another object of the present invention is to provide a two-amp circuit that can always fix the clamp level to a constant level regardless of changes in temperature or other conditions.

(Example) The contents of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 3 is a circuit diagram showing one embodiment of the present invention. Transistor Tri between positive and negative power supply ■ and -■
A series circuit of resistor R1, resistor 2 and transistor Tr9
A series circuit of resistors R3 and R4, a series circuit of transistors Tr3, Tr5, and Tr7, a transistor Tr
2 and a series circuit of resistor R5 are connected in parallel.

The transistors Tr1 and Tr2 form an emitter follower, and the input terminal 1 is connected to the base of the transistor l1lr1, and the input signal from the input terminal l is sent to the transistor Tr20 via a capacitor C connected to the emitter of the transistor TFI. applied to the pace. Further, a transistor Tr8 whose base and emitter are connected is connected in parallel with the transistor '1''r9.

Further, the bases of transistors Tr8 and Tr7 are connected. Transistor '1rr3. A transistor Tr4 whose base and collector are short-circuited is connected in parallel with the series circuit of Tr5.
A series circuit of transistor Tr6 and transistor Tr6 are connected. Transistor Tr3. The connection point between the collectors of Tr5 is connected to the base of transistor Tr2. Further, the base of the transistor Tr5 is connected to the output terminal 2 together with the emitter of the transistor Illr2. Note that the potential at point B and the potential at output terminal 2 can be considered to be the same. The base of the transistor Tr9 is connected to the clamp pulse input terminal 3, and the base of the transistor Tr60 is connected to the resistor R.
3. The voltage is fixed to the clamp potential as a reference potential by the capacitor 4.

To further explain the active elements in the figure, the transistor T
ri, Tr2 form an emitter follower, and transistors Tr5. Tr6 forms a differential amplifier. Also, transistors '1' r 4 , T r 3 and 1' r
7 and T r 8 form a so-called current mirror circuit, and if the current gain of these transistors is sufficiently large and the characteristics are uniform, the transistor T r 3 *
The collector currents of T r 4, '1' r 7 and T r 8 are equal. Further, the transistor Tr3. Tr4
is differential amplifier transistor Tr5. It is a load on Tr6. The transistor Tr3 constitutes a charging circuit for the capacitor C, and the transistor Tr5 constitutes a discharging circuit for the capacitor C.The device of the present invention has the above-mentioned configuration, and its operation will be explained below.

First, during the clamping period, the clamp pulse input terminal 3, that is, the base of the transistor Tr9 becomes low level, and the transistor 11r9 is cut on. Then, if the base current is ignored, a collector current given by the following equation flows through the transistor Tr8.

■BE8: Transistor Tr8 whose base and emitter are short-circuited when the base and emitter of Tr8 are connected.
．． Tr7 forms a so-called current mirror, and a collector current given by the equation 0, which is equal to that of transistor Tr8, flows through transistor Tr7, and due to the constant current characteristics of the collector current, transistor Tr7 becomes differential amplifier Tr5. Tr
6 common emitters are driven with a constant current.

By the voltage division of R3 and R4, the base of the transistor Tr6, that is, the potential at point A in FIG. 3 is set to the reference potential to be clamped. Let us consider the case where this voltage is lower than the base potential of the other transistor Tr5 forming the differential amplifier, that is, the output voltage (this is taken as VO). In this case, the transistor/transistor Tr6t is cut off and the transistor Tr5 is turned on. Due to the cutoff of the transistor Tr6, no collector current flows through the diode-coupled transistor Tr4, which is its load. As a result, almost no collector current flows in the other transistor Tr3 forming the current mirror. On the other hand, since the transistor Tr6 is cut off, the transistor Tr8 is in the on/off state.
Almost all of the collector current of transistor Tr8 flows, and the collector current of transistor Tr8 has a value almost given by equation 0. However, the transistor Tr commonly connected to it
Due to the above-mentioned reason, current does not flow through the collector of #3, and there is also a commonly connected transistor Tr.
Assuming that the current gain of transistor Tr2 is sufficiently large, almost no current will flow through the base of this transistor Tr2. Therefore, the charge of the capacitor C is discharged by the collector current of the transistor Tr5, which is approximated by equation 0, and the transistor Tr
The base potential of transistor T2 decreases, and accordingly, the base potential of transistor T
The emitter potential of r2, that is, the potential of output terminal 2 also decreases, and the difference between VO and VC decreases.0 As a result, V
□=V c. On the other hand, if we consider the case where Vc is higher than Vo, contrary to the above, in the differential amplifier, transistor Tr6 is off, Tr5
turns off 0 Tr6 turns on and transistor Tr5 turns off, so a collector current that is almost the same as that of formula 0 flows through transistor Tr 6 0 Therefore, almost the same current as that of formula 0 flows in transistor Tr 4 which is its load 0 As a result 0 also at the collector of transistor Tr3, which forms a current mirror together with Tr4.
Almost the same current flows as in the equation. Considering the current at point B, which is the base of transistor Tr2, based on these, if the current gain of transistor Tr2 is sufficiently large, its base current can be ignored, and the collector current of transistor Tr5, which is cut off, is also approximately It can be considered to be zero. As a result, a current approximated by the equation 0 is supplied from the transistor Tr3 and flows in, charging the capacitor C.
As the base potential of the transistor Tr2 increases, the emitter potential of the transistor Tr2, that is, the potential of the output terminal 2 also increases, reducing the difference between VO and VC.

Due to such an action, Vc and (1)0 eventually become equal.

Next, consider operation during periods other than the clamp period.

During this period, the base of the transistor Tr9 at the input terminal 3 of the circuit becomes a no-yield, and the transistor Tr9 is turned on. Then, the transistor/transistor Tr connected to the collector and emitter of the transistor 11r9
70 base and emitter shorted, transistor T
r7 is cut off. As a result, transistors Ty5. Both transistors Tr6 are cut-on, and no collector current flows through either transistor, which is the load of the transistor Tr3. Since no current flows through transistor Tr4 either, transistor Tr3. Tr4 serves as a cutoff. Therefore, no current flows through the collectors of transistors Tr3 and Tr5, and the potential at point B is completely unaffected by these two transistors.

For the above-mentioned reason, the existence of transistors Tr3 to Tr9 can be ignored in periods other than the cycle/pull period.

A video signal input from the transistor Tri is transmitted to the output terminal through the capacitor C and the transistor Tr2.

In this way, according to this embodiment, in the operation to reduce the difference between V, c, and VO, charging and discharging of C is constant current charging and discharging, which is expressed by equation It takes less time to clamp within a high precision range than in the conventional case.

Further, the load of the differential amplifier consisting of transistors T r 5 + T r 6 is transistor Ty3. Since it is an active load like Tr4, the gain of the differential amplifier is very high.

When a differential amplifier is regarded as an error amplifier, its high gain means that its error detection ability is high, so the clamp voltage can be set to the target value with extremely high accuracy.

Furthermore, since the reference voltage Vc and the output voltage VO themselves are compared and controlled so that they match, the output voltage itself is fixed at the target clamp level, and the pace/emitter voltage of the transistor (and its temperature characteristics) is fixed as in the conventional device. )
It becomes possible to set the clap/clamp level at a high fli1 degree without causing any errors due to this.

Also, error amplifier transistor Tr5. The symmetrical configuration of Tr6 makes it possible to cancel the effects of clamp level changes due to temperature characteristics of the transistor and other changes in ambient conditions.

Further, the embodiment of the present invention is particularly suitable for integrated circuits, and constant current circuits such as R2, T r 7 ' + T r 8, etc., can be used as those prepared elsewhere. Compared to the conventional example shown in the figure, the substantial increase in the number of elements is almost negligible, and since more transistors are used than resistors compared to the case shown in FIG. 2, the circuit can be highly integrated on a small area.

FIG. 4 is a circuit diagram showing an embodiment of the mud 2 of the present invention. In FIG. 4, elements corresponding to those in FIG. 3 are designated by the same symbol i. In the example of FIG. 4, the resistor R1 of FIG. 3 is removed and transistors Trto to Tri5 are added.

The transistor TrlO has its pace and emitter connected to the pace and emitter of the transistor Tr5, respectively, and its collector is connected to the pace of the transistor Trll.

The =+rector and pace of the transistor Ty11 are short-circuited. The emitter of transistor Trll is in positive electric image ■
connected to.

The emitter and pace of transistor Trll are connected to the emitter and pace of transistor Tr12, respectively, and the collector of transistor Tr12 is connected to the emitter of transistor Tri. The transistor Tr 13 has its pace and emitter connected to the transistor Tr 40 pace and emitter, respectively, and its collector has the transistor Tr
140 base. The collector and pace of the transistor Tr14 are short-circuited, and the emitter is connected to the negative power supply -2. The emitter and pace of transistor Tr15 are connected to the emitter and pace of transistor Tri4, respectively, and its collector is connected to the emitter of transistor Tri. Transistor Tr5. TrlO and Tr
ll, Tr12 and Tr4. Tr13 and T r
14, '1' r 15 forms a current mirror.

Next, its operation will be explained. During the clamp period, the third
As in the case shown in the figure, the transistor Tr9 is turned off, and the collector current of the transistor Tr7 approximated by equation (2) drives the differential amplifier formed by the transistors T r 5 + T r 6 at a constant current. If the output potential VO is higher than the potential VC at point A, the transistor T constituting the discharge circuit
This is the same as in FIG. 3 in that the charge on the capacitor C is discharged by the collector current of r5. Transistors Tr5 and T
Since rlO constitutes a current mirror circuit, their currents are equal, the collector currents of transistor Trll, which is its load, are also equal, and the collector currents of transistor Tr12, which constitutes transistor Trll and the current mirror circuit, are also equal. On the other hand, the other one that constitutes the differential amplifier
The transistor Tr6 is cut off, and the transistor Tr14 serving as its load is also cut off. Therefore, along with this, the transistor Tr13 forming a current mirror is also cut off, and since almost no current flows through the transistor Tr14, which is a large load, the transistor Tr15 is also cut off. According to the above explanation, the capacitor C supplied by the transistor T r 5
A current equal to the discharge current of is supplied by the transistor Tr12.

■When VC is higher than 0, a current equal to the charging current of the capacitor C supplied by the transistor Tr3 forming the charging circuit is generated by the transistor Tr15.
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In this way, the output voltage is fixed at the crank potential in the same manner as in the case of FIG. 3 by simply changing the current supply source on the emitter side of the transistor Tri of the capacitor C.

In periods other than clamping, transistors Tr3 to Tr15
are all cut on, and it becomes the same as if they did not exist. Therefore, the video signal is transmitted from the input to the output in the same manner as in the case of FIG.

In particular, in the case of this embodiment, since the number of resistors is reduced by one, the mounting area of the circuit can be reduced when integrated circuits are integrated, and the charging/discharging current of the capacitor C can also be reduced by the transistor Tr15.
Because this is done with Tr12, almost no current flows through the transistor Tri, making it possible to make the input current/peak/speed extremely high.As long as the output current/speed/speed of the previous stage is not very high, the follower transistor Tr1 can be omitted. You can also do that.

(Effects) As explained above, the clamp circuit of the present invention provides a charging circuit and a discharging circuit for the clamp capacitor, and operates the charging circuit and discharging circuit according to the difference between the reference potential and the capacitor potential. Since a differential amplifier is provided to control the state, the clamping operation can be performed with extremely high precision.

Furthermore, the time required for the clamping operation can be significantly shortened compared to the conventional method. 'Furthermore, the clamp level can always be fixed at a constant level regardless of changes in temperature and other conditions.

[Brief explanation of the drawing]

Figure 1 is a diagram explaining the principle of a conventional clap/clamp circuit, and Figure 2 is a diagram showing a specific example of a conventional clap/clamp circuit.
The figure is a circuit diagram showing the first embodiment of the present invention, and FIG.
FIG. 2 is a circuit diagram showing an example. C... Capacitor as a capacitor, Tr3
...Transistor that constitutes the charging circuit, Tr5
...Transistor that constitutes the discharge circuit, Tr6
. . . A transistor that constitutes a differential amplifier together with the transistor T r 5.

Claims (1)

[Scope of Claims] A capacitor arranged in series in a signal path, a charging circuit for charging the capacitor, a discharging circuit for discharging the capacitor, and a charging circuit according to the difference between a reference potential and the potential of the capacitor. and a differential amplifier that controls the operating state of the discharge circuit.