JPH0348683B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a power amplifier that has both low distortion when amplifying small signals and high efficiency when amplifying large signals.

Class A amplifiers have the advantage of extremely low distortion rates, so if they are used as power amplifiers for audio, extremely good sound quality can be obtained. However, due to its operating principle, class A amplifiers have the disadvantage of extremely low power efficiency, which makes it difficult to achieve high output.

Conventionally, a power amplifier that takes advantage of the advantages of class A amplifiers and overcomes the disadvantages of class A amplifiers has been designed to
A device is known in which a class motion and a class B motion can be selected. That is, in this power amplifier, when the manual switch is set to one switching position, the bias amount of the power amplification stage is increased to select class A operation, and the power supply voltage supplied to the power amplification stage is decreased. This prevents the loss from becoming excessive, and when the manual switch is set to the other switching position, the bias amount is reduced and class B operation is selected, and the power supply voltage is increased to obtain high output. This is how it was done. However, in such a power amplifier, when class A operation is selected, the power supply voltage is lowered as described above, so that only a signal with a lower maximum signal level can be amplified than when class B operation is selected. There was a problem that the dynamic range became narrower.

On the other hand, in recent years, audio equipment has become increasingly digital, and there is a strong desire to develop a power amplifier that can achieve both low distortion and a wide dynamic range.

In view of the above circumstances, the present invention has been made for the purpose of providing a power amplifier that can efficiently amplify large signals while maintaining a low distortion rate for small signals. a signal level detection means for detecting a signal level based on an output signal generated by the signal; and a bias for increasing a bias amount of the power amplification stage when the signal level is small and decreasing the bias amount when the signal level is large. and a power supply voltage control means for decreasing the power supply voltage supplied to the power amplification stage when the signal level is small and increasing the power supply voltage when the signal level is large. It is characterized by

Embodiments of the power amplifier according to the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an embodiment of a power amplifier according to the present invention. In this diagram,
NPN transistor 1a and PNP transistor 1b are transistors that constitute a power amplification stage of this power amplifier, and these transistors
The emitter resistors 2a and 2b of transistors a and 1b are commonly connected to the output terminal 3, and between the bases of these transistors 1a and 1b, in order to flow an equal amount of bias current I _B to these transistors 1a and 1b. A bias circuit (for example, a constant voltage circuit) 4 is inserted. This bias circuit 4 sets the bias current I _B to a large value I _B1 that biases the transistors 1a and 1b to class A (or class AB) according to the output of a bias control circuit 10 (bias control means) to be described later. , or a small value I _B2 at which these transistors 1a and 1b are biased to class B.
It is configured so that it can be switched to

Next, the power supply 5a (voltage E ₁ ) and the power supply 6a (voltage E ₂ ) connected in series are power supplies for supplying the positive power supply voltage +B to the collector of the transistor 1a, and the negative side of the power supply 5a The terminal is grounded, the connection point between the positive side terminal of the power source 5a and the negative side terminal of the power source 6a is connected to the collector of the transistor 1a through a diode 7a in the forward direction, and the positive side terminal of the power source 6a is connected to the switch circuit 8a. It is connected to the collector of the transistor 1a through the transistor 1a.

On the other hand, the power supply 5b (voltage E ₁ ) and power supply 6b (voltage E ₂ ) connected in series are power supplies for supplying the negative power supply voltage -B to the collector of the transistor 1b, and the positive terminal of the power supply 5b is The connection point between the negative terminal of the power supply 5b and the positive terminal of the power supply 6b is connected to the collector of the transistor 1b through a diode 7b in the opposite direction, and the negative terminal of the power supply 6b is connected to the collector of the transistor 1b through a switch circuit 8b. It is connected to the collector of transistor 1b. The signal level detection circuit 9 is
When the absolute value of the voltage e ₀ of the output signal obtained at the output terminal 3 is greater than a predetermined level set slightly smaller than the voltage E ₁ , and when the absolute value of the voltage e ₀ is less than the predetermined level. It is configured to output a detection signal within a predetermined time after the voltage drops to . The detection signal output from the signal level detection circuit 9 is supplied to a bias control circuit 10 and a power supply voltage switching circuit 11 (power supply voltage switching means). The bias control circuit 10 controls the bias circuit 4 so that when the detection signal is not supplied, the transistors 1a and 1b are biased to class A (or class AB), that is, the bias current I _B is set to the value I _B1 , and when the detection signal is supplied, transistor 1
This is a circuit that controls so that a and 1b are biased to class B, that is, so that the bias current I _B has a value I _B2 . Further, the power supply voltage switching circuit 11 opens both the switch circuits 8a and 8b if the detection signal is not supplied from the signal level detection circuit 9, and opens the switch circuits 8a and 8b if the same detection signal is supplied. Both circuits are closed.
Note that the terminal 12 is a ground terminal corresponding to the output terminal 3.

Next, to explain the operation of this power amplifier with the above configuration, when the absolute value of voltage e ₀ is below a predetermined level corresponding to voltage E ₁ , as before time t ₁ in the time chart shown in FIG. That is, in the case of small signal amplification, the signal level detection circuit 9 does not output a detection signal. Therefore, in this case, since the power supply voltage switching circuit 11 opens the switch circuits 8a and 8b, the voltages +E ₁ and -E ₁ of the power supplies 5a and 5b are connected to the diode 7 as voltages +B and -B.
a, 7b (see A in Figure 2).
Further, in this case, the bias control circuit 10 controls the bias circuit 4 so that the bias current I _B becomes the value I _B1 . In this way, before time _t1 , transistors 1a and 1b are biased to perform class A operation, and voltages + _E1 and _-E1 are supplied as voltages +B and -B. Next, when the absolute value of the voltage e ₀ exceeds the predetermined level at time t ₁ , the signal level detection circuit 9 begins to output a detection signal. Therefore, in this case, the power supply voltage switching circuit 11 shifts the switch circuits 8a and 8b to the closed state, and as a result, the voltages +B and -B are the voltages +(E ₁ +E ₂ ) and -(E ₁ +E ₂ ). will be supplied. Note that at this time, the diodes 7a and 7b are in a reverse bias state. Further, in this case, the bias control circuit 10 switches the bias current I _B to the value I _B2 (I _B2 < I _B1 ). Thus, at time _t1 , the biases of transistors 1a and 1b are switched so that they perform class B operation, and voltages +B and -B are respectively increased. Next, at time t ₂ , the voltage e ₀
If the absolute value of decreases below the predetermined level,
The signal level detection circuit 9 detects a period T ₁ from this time t ₂
At the elapsed time _t3 , the detection signal is no longer output. Therefore, in this case, the switch circuits 8a, 8
b transitions from the closed state to the open state at time _t3 ,
As a result, the voltages +B, -B are +(E ₁ +E ₂ ), -(E ₁
+E ₂ ) to +E ₁ and −E ₁ respectively. Also at this time, the bias current I _B is increased from the value I _B2 to the value I _B1 . Thus, at time _t3 , transistors 1a and 1b are shifted from the class B bias state to the class A bias state, and +B and -B are respectively decreased. Note that the period T ₁ is provided to prevent the bias current I _B and the voltages +B and -B from being frequently increased or decreased when the voltage e ₀ is frequently increased or decreased. Thereafter, following exactly the same operation, the voltages +B, -
B and bias current I _B are increased or decreased in accordance with the increase or decrease in the absolute value of voltage e ₀ .

In this way, according to this embodiment, if the signal level of the signal to be amplified is small, the power amplification stage is biased to class A and the power supply voltage is reduced, and if the signal level of the signal to be amplified is large, the power amplification stage is The power supply voltage can be increased while biasing the stage to class B. Since the signal level detection circuit 9 operates based on the output signal obtained at the output terminal of the power amplification stage, it can accurately detect the operating state of the power amplification stage itself, and can also control the bias and power supply voltage. It becomes certain. In other words, even if there is too much or too little phase compensation in the voltage amplification stage, etc. that precedes the power amplification stage, and phase rotation occurs during signal amplification, the power amplification stage itself will always be compensated without making mistakes in control timing such as switching. The amount of bias and power supply voltage can be supplied according to the operation of the device. In addition, in the above embodiment, the timing at which the bias current I _B is switched and the voltage +
Although we have explained that the timing at which B and -B switch is the same timing, the timing at which bias current I _B switches is that voltages +B and -B are always decreased while bias current I _B is increased. You may change it arbitrarily as long as the conditions are met. For example, the bias current shown in Figure 2 C
Like the switching timing of _IB , the bias current
The timing at which I _B is increased may be shifted backward by a period T ₂ from the timing at which voltages +B and -B are decreased. Furthermore, in the embodiment described above, the bias current I _B was explained as switching between the transistors 1a and 1b performing class A operation or class B operation. 1b switches to perform either class AB operation or class B operation, or switches to perform either class A operation or class AB operation, or simply increases or decreases without completely switching the operation mode. You can do it like this.

Next, FIG. 3 is a circuit diagram showing a specific example of a power amplifier according to the present invention, and in this diagram,
Components corresponding to those in FIG. 1 are given the same reference numerals and their explanations will be omitted. In FIG. 3, the signal level detection circuit 9 includes an absolute value circuit 13 that converts the voltage e ₀ of the output signal at the output terminal 3 into the absolute value |e ₀ | of the same voltage e ₀ and outputs it, and this absolute value circuit 13
The output |e ₀ | is compared with the reference voltage Vr, and |e ₀ |≧Vr
A comparator 14 that outputs a high level signal if |e ₀ | 16-1
8, a diode 19 connected in parallel to resistors 16 and 17, a capacitor 20 connected between the connection point of resistors 16 and 17 and the ground, and a PNP transistor whose base is connected to the collector of transistor 15. If |e ₀ |<Vr, the collector voltage of transistor 21 becomes the ground level, and if |e ₀ |≧Vr,
The collector voltage of 1 becomes high level, and |e ₀
When the time T ₁ determined by the resistance values of the resistors 16 to 18 and the capacitance of the capacitor 20 elapses while the state changes from |≧Vr to |e ₀ |<Vr, the collector voltage of the transistor 21 changes from the high level to the ground level. It is starting to shift to The power supply voltage switching circuit 11 includes an NPN transistor 22 driven by the collector current of the transistor 21;
It consists of a PNP transistor 23 etc. driven by the emitter current of this transistor 22, and if the collector voltage of the transistor 21 is at a high level, the PNP transistor 8a and
The PNP transistor 8b is made conductive, and when the collector voltage of the transistor 21 is at the ground level, the transistors 8a and 8b are made non-conductive. Note that transistors 8a and 8b correspond to switch circuits 8a and 8b shown in FIG. 1, respectively. The bias control circuit 10 conducts when a potential difference occurs between the positive terminal of the power source 6a and the collector of the transistor 1a, that is, when the transistor 8a is non-conductive, and connects the positive terminal of the power source 6a and the collector of the transistor 1a. If no potential difference occurs between the PNP transistor 24, which becomes non-conductive when the transistor 8a becomes conductive, and the collector current of the transistor 24, the PNP transistor 24 becomes non-conductive.
It consists of an NPN transistor 25, an NPN transistor 26, etc., which becomes conductive when the collector voltage of the transistor 25 is at a high level, and becomes non-conductive when the collector voltage of the transistor 25 is at the ground level, and when the transistor 8a becomes conductive. When the transistor 26 becomes conductive and the transistor 8a becomes non-conductive, the transistor 26 becomes non-conductive. The bias circuit 4 is
PNP transistor 27 and this transistor 2
This is a constant voltage circuit consisting of resistors 28 to 30 connected in series between the emitter and collector of transistor 27, and the emitter of transistor 27 is connected to constant current source 31.
is connected to the output terminal of transistor 1.
The collector of the transistor 27 is connected to the negative terminal of the power supply 6b via the NPN transistor 33 and the resistor 34 in order, and the collector of the PNP transistor 32b that drives the transistor 1b is connected to the base of the NPN transistor 32a that drives the transistor 1b. connected to the base. In this bias circuit 4, when the transistor 26 becomes conductive, the collector-emitter voltage of the transistor 27 decreases, and the bias current of the transistors 1a and 1b decreases.
When I _B is decreased and transistor 26 becomes non-conductive, the collector-emitter voltage of transistor 27 increases, increasing the bias current I _B. Note that a terminal 35 connected to the base of the transistor 33 is an input terminal of this power amplifier.

According to the specific circuit shown in FIG. 3, the same operation as in the embodiment shown in FIG. 1 can be performed.

Next, FIG. 4 is a circuit diagram showing another specific example of the power amplifier according to the present invention. In this diagram,
The bias control circuit 10, as shown in FIG.
When the absolute value of the voltage _e0 of the output signal at the output terminal 3 exceeds a predetermined level corresponding to the voltage _E1 , the bias current _IB becomes the value _IB2 , and the absolute value of the voltage _e0 is below the predetermined level. If so, the bias current I _B
bias circuit 4 so that the value I _B1 (I _B1 > I _B2 )
control. The power supply voltage control circuit 11 also includes a resistor 36a inserted between the positive terminal of the power supply 6a and the base of the transistor 8a, and a Zener diode 37a inserted between the base and the output terminal 3.
(Zener voltage Vz), a Zener diode 37b (Zener voltage Vz) inserted between the output terminal 3 and the base of the transistor 8b, and a resistor 36b inserted between the base and the negative terminal of the power supply 6b. When the absolute value of the voltage _e0 of the output signal at the output terminal 3 exceeds a predetermined level corresponding to the voltage _E1 , the Zener voltage Vz and the voltage
e ₀ makes transistor 8a (or transistor 8b) conductive, thereby causing voltage +B
(or voltage -B) is changed according to voltage |e ₀ +Vz|, as shown in FIG. 5A.

However, even with the specific circuit shown in FIG. 4, the same effects as in the embodiment shown in FIG. 1 can be obtained.

Note that in the embodiments and specific examples described above, the voltages +B, -B and the bias current I _B were mainly changed in a stepwise manner.
These voltages +B, -B and bias current I _B may be changed in an analog manner as shown in A and B of FIG. 6, respectively.

As is clear from the above description, according to the power amplifier according to the present invention, bias control means and power supply voltage control means are respectively provided, and based on the signal to be amplified, when the signal level of the signal to be amplified is small, In this method, the amount of bias in the power amplification stage is increased and the power supply voltage is decreased, and when the signal level is large, the amount of bias is decreased and the power supply voltage is increased, so that small signals can be amplified with an extremely low distortion factor. At the same time, large signals can be amplified with extremely high power efficiency, thereby making it possible to achieve both a low distortion rate and a wide dynamic range. Further, since the control timing of each control means is detected based on the output signal of the power amplification stage itself, it is always accurate and accurate without being affected by phase changes of other circuits.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a time chart for explaining the operation of the embodiment, and FIG. 3 is a circuit diagram showing a specific example of the invention. 4 is a circuit diagram showing another specific example of the present invention, FIG. 5 is a time chart for explaining the operation of the specific example shown in FIG. 4, and FIG. 6 is a diagram showing bias current, power supply voltage, etc. in this invention. This is a time chart showing the control method. 1a, 1b...power amplification stage (transistor), 4
...Bias circuit, 5a, 5b, 6a, 6b...Power source, 8a, 8b...Switch circuit, 9...Signal level detection means (signal level detection circuit), 10...Bias control means (bias control circuit), 11...Power supply voltage control means (power supply voltage control circuit).

Claims (1)

[Scope of Claims] 1. Signal level detection means for detecting a signal level based on an output signal obtained at an output terminal of a power amplification stage, and increasing a bias amount of the power amplification stage when the signal level is small; Bias control means reduces the amount of bias when the signal level is high, and reduces the power supply voltage supplied to the power amplification stage when the signal level is low, and reduces the power supply voltage when the signal level is high. A power amplifier comprising power supply voltage control means for increasing the voltage.